MC68HC908GR16 Data Sheet

Transcription

1 MC68HC908GR16 Data Sheet M68HC08 Microcontrollers MC68HC908GR16 Rev /2007 freescale.com

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3 MC68HC908GR16 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date February, 2003 May, 2003 Revision Level Description Page Number(s) N/A Initial release N/A 1.0 Reorganized to meet latest publication standards for M68HC08 Family documentation N/A Chapter 16 Serial Peripheral Interface (SPI) Module Removed all references to DMAS 193 Figure -2. CGM External Connections Figure updated for consistency 65 Table -. Example Filter Component Values Table updated to reflect new resistor values 76 Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash technology licensed from SST. Freescale Semiconductor, Inc., 200, All rights reserved. Freescale Semiconductor 3

4 Revision History Revision History (Continued) Date September, 200 March, 2005 January, 2007 April, 2007 Revision Level o Description Figure 1-1. MCU Block Diagram Removed data bus switch module 22 Figure 2-2. Control, Status, and Data Registers and Figure 5-1. Configuration Register 2 (CONFIG2) Changed name of bit 0 from SCIBDSRC to ESCIBDSRC 29 and ESCI Prescaler Register Updated description in this subsection ESCI Arbiter Control Register Updated description of ACLK bit Bit Time Measurement Updated bit time measurement mode for ACLK = Added dc injection current values to: Vdc Electrical Characteristics Vdc Electrical Characteristics CGM Component Specifications Corrected series resistor values Memory Characteristics Table updated to reflect new values Clock Generator Module (CGM) Updated description to remove erroneous information Clock Generation Module Characteristics Updated to reflect correct values. 260 Table Interrupt Source Flags Changed IF7 to TIM2 channel instead of Reserved. 1 Table 2-1. Vector Addresses Changed address $FFEE to TIM2 Channel 1 Vector (High) and $FFEF to TIM2 Channel 1 Vector (Low) from Reserved 37 Figure 2-2. Control, Status, and Data Registers Changed addresses $0033 to $0035 to show TIM2 Channel 1 registers. 29 Figure 2-2. Control, Status, and Data Registers Replaced TMCLKSEL with TMBCLKSEL to be compatile with development tool nomenclature 32 Chapter 5 Configuration Register (CONFIG) Changed COPCLK to CGMXCLK, replaced TMCLKSEL with TMBCLKSEL to be compatible with development tool nomenclature, and replaced exponents for COP timeout 79 period 6.2 Functional Description Replaced exponents for COP timeout period Stop Mode Changed COPCLK to CGMXCLK 113 Figure 1-2. ESCI Module Block Diagram Replaced BUS_CLK with BUS CLOCK and removed reference to rx BUSCLK 19 Figure 1-5. ESCI Transmitter and Figure 1-6. ESCI Receiver Block Diagram Added CGMXCLK OR to BUS CLOCK designator ESCI Baud Rate Register Replaced description of the LINT and LINR bits Figure Timebase Block Diagram and 17.5 TBM Interrupt Rate Replaced TBMCLKSEL with TMBCLKSEL to be compatible with development tool nomenclature Page Number(s) Freescale Semiconductor

5 List of Chapters Chapter 1 General Description Chapter 2 Memory Chapter 3 Analog-to-Digital Converter (ADC) Chapter Clock Generator Module (CGM) Chapter 5 Configuration Register (CONFIG) Chapter 6 Computer Operating Properly (COP) Module Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 Low-Power Modes Chapter 11 Low-Voltage Inhibit (LVI) Chapter 12 Input/Output Ports (PORTS) Chapter 13 Resets and Interrupts Chapter 1 Enhanced Serial Communications Interface (ESCI) Module Chapter 15 System Integration Module (SIM) Chapter 16 Serial Peripheral Interface (SPI) Module Chapter 17 Timebase Module (TBM) Chapter 18 Timer Interface Module (TIM) Chapter 19 Development Support Chapter 20 Electrical Specifications Chapter 21 Ordering Information and Mechanical Specifications Freescale Semiconductor 5

6 List of Chapters 6 Freescale Semiconductor

7 Table of Contents Chapter 1 General Description 1.1 Introduction Features Standard Features of the MC68HC908GR Features of the CPU MCU Block Diagram Pin Assignments Pin Functions Power Supply Pins (V DD and V SS ) Oscillator Pins (OSC1 and OSC2) External Reset Pin (RST) External Interrupt Pin (IRQ) CGM Power Supply Pins (V DDA and V SSA ) External Filter Capacitor Pin (V CGMXFC ) ADC Power Supply/Reference Pins (V DDAD /V REFH and V SSAD /V REFL ) Port A Input/Output (I/O) Pins (PTA7/KBD7 PTA0/KBD0) Port B I/O Pins (PTB7/AD7 PTB0/AD0) Port C I/O Pins (PTC6 PTC0) Port D I/O Pins (PTD7/T2CH1 PTD0/SS) Port E I/O Pins (PTE5 PTE2 and PTE0/TxD) Chapter 2 Memory 2.1 Introduction Unimplemented Memory Locations Reserved Memory Locations Input/Output (I/O) Section Random-Access Memory (RAM) FLASH Memory (FLASH) Functional Description FLASH Control Register FLASH Page Erase Operation FLASH Mass Erase Operation FLASH Program/Read Operation FLASH Block Protection FLASH Block Protect Register Wait Mode Stop Mode Freescale Semiconductor 7

8 Table of Contents Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction Features Functional Description ADC Port I/O Pins Voltage Conversion Conversion Time Conversion Accuracy and Precision Result Justification Monotonicity Interrupts Low-Power Modes Wait Mode Stop Mode I/O Signals ADC Analog Power Pin (V DDAD ) ADC Analog Ground Pin (V SSAD ) ADC Voltage Reference High Pin (V REFH ) ADC Voltage Reference Low Pin (V REFL ) ADC Voltage In (V ADIN ) I/O Registers ADC Status and Control Register ADC Data Register High and Data Register Low Left Justified Mode Right Justified Mode Left Justified Signed Data Mode Eight Bit Truncation Mode ADC Clock Register Chapter Clock Generator Module (CGM).1 Introduction Features Functional Description Crystal Oscillator Circuit Phase-Locked Loop Circuit (PLL) PLL Circuits Acquisition and Tracking Modes Manual and Automatic PLL Bandwidth Modes Programming the PLL Special Programming Exceptions Base Clock Selector Circuit CGM External Connections Freescale Semiconductor

9 . I/O Signals Crystal Amplifier Input Pin (OSC1) Crystal Amplifier Output Pin (OSC2) External Filter Capacitor Pin (CGMXFC) PLL Analog Power Pin (V DDA ) PLL Analog Ground Pin (V SSA ) Oscillator Enable Signal (SIMOSCEN) Oscillator Stop Mode Enable Bit (OSCSTOPENB) Crystal Output Frequency Signal (CGMXCLK) CGM Base Clock Output (CGMOUT) CGM CPU Interrupt (CGMINT) CGM Registers PLL Control Register PLL Bandwidth Control Register PLL Multiplier Select Register High PLL Multiplier Select Register Low PLL VCO Range Select Register PLL Reference Divider Select Register Interrupts Special Modes Wait Mode Stop Mode CGM During Break Interrupts Acquisition/Lock Time Specifications Acquisition/Lock Time Definitions Parametric Influences on Reaction Time Choosing a Filter Chapter 5 Configuration Register (CONFIG) 5.1 Introduction Functional Description Chapter 6 Computer Operating Properly (COP) Module 6.1 Introduction Functional Description I/O Signals CGMXCLK STOP Instruction COPCTL Write Power-On Reset Internal Reset Reset Vector Fetch COPD (COP Disable) Freescale Semiconductor 9

10 Table of Contents COPRS (COP Rate Select) COP Control Register Interrupts Monitor Mode Low-Power Modes Wait Mode Stop Mode COP Module During Break Mode Chapter 7 Central Processor Unit (CPU) 7.1 Introduction Features CPU Registers Accumulator Index Register Stack Pointer Program Counter Condition Code Register Arithmetic/Logic Unit (ALU) Low-Power Modes Wait Mode Stop Mode CPU During Break Interrupts Instruction Set Summary Opcode Map Chapter 8 External Interrupt (IRQ) 8.1 Introduction Features Functional Description IRQ Pin IRQ Module During Break Interrupts IRQ Status and Control Register Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction Features Functional Description Keyboard Initialization Low-Power Modes Wait Mode Freescale Semiconductor

11 9.5.2 Stop Mode Keyboard Module During Break Interrupts I/O Registers Keyboard Status and Control Register Keyboard Interrupt Enable Register Chapter 10 Low-Power Modes 10.1 Introduction Wait Mode Stop Mode Analog-to-Digital Converter (ADC) Wait Mode Stop Mode Break Module (BRK) Wait Mode Stop Mode Central Processor Unit (CPU) Wait Mode Stop Mode Clock Generator Module (CGM) Wait Mode Stop Mode Computer Operating Properly Module (COP) Wait Mode Stop Mode External Interrupt Module (IRQ) Wait Mode Stop Mode Keyboard Interrupt Module (KBI) Wait Mode Stop Mode Low-Voltage Inhibit Module (LVI) Wait Mode Stop Mode Enhanced Serial Communications Interface Module (ESCI) Wait Mode Stop Mode Serial Peripheral Interface Module (SPI) Wait Mode Stop Mode Timer Interface Module (TIM1 and TIM2) Wait Mode Stop Mode Freescale Semiconductor 11

12 Table of Contents Timebase Module (TBM) Wait Mode Stop Mode Exiting Wait Mode Exiting Stop Mode Chapter 11 Low-Voltage Inhibit (LVI) 11.1 Introduction Features Functional Description Polled LVI Operation Forced Reset Operation Voltage Hysteresis Protection LVI Trip Selection LVI Status Register LVI Interrupts Low-Power Modes Wait Mode Stop Mode Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction Port A Port A Data Register Data Direction Register A Port A Input Pullup Enable Register Port B Port B Data Register Data Direction Register B Port C Port C Data Register Data Direction Register C Port C Input Pullup Enable Register Port D Port D Data Register Data Direction Register D Port D Input Pullup Enable Register Port E Port E Data Register Data Direction Register E Freescale Semiconductor

13 Chapter 13 Resets and Interrupts 13.1 Introduction Resets Effects External Reset Internal Reset Power-On Reset (POR) Computer Operating Properly (COP) Reset Low-Voltage Inhibit (LVI) Reset Illegal Opcode Reset Illegal Address Reset System Integration Module (SIM) Reset Status Register Interrupts Effects Sources Software Interrupt (SWI) Instruction Break Interrupt IRQ Pin Clock Generator (CGM) Timer Interface Module 1 (TIM1) Timer Interface Module 2 (TIM2) Serial Peripheral Interface (SPI) Serial Communications Interface (SCI) KBD0 KBD7 Pins Analog-to-Digital Converter (ADC) Timebase Module (TBM) Interrupt Status Registers Interrupt Status Register Interrupt Status Register Interrupt Status Register Chapter 1 Enhanced Serial Communications Interface (ESCI) Module 1.1 Introduction Features Pin Name Conventions Functional Description Data Format Transmitter Character Length Character Transmission Break Characters Idle Characters Inversion of Transmitted Output Transmitter Interrupts Receiver Freescale Semiconductor 13

14 Table of Contents Character Length Character Reception Data Sampling Framing Errors Baud Rate Tolerance Receiver Wakeup Receiver Interrupts Error Interrupts Low-Power Modes Wait Mode Stop Mode ESCI During Break Module Interrupts I/O Signals PTE0/TxD (Transmit Data) PTE1/RxD (Receive Data) I/O Registers ESCI Control Register ESCI Control Register ESCI Control Register ESCI Status Register ESCI Status Register ESCI Data Register ESCI Baud Rate Register ESCI Prescaler Register ESCI Arbiter ESCI Arbiter Control Register ESCI Arbiter Data Register Bit Time Measurement Arbitration Mode Chapter 15 System Integration Module (SIM) 15.1 Introduction SIM Bus Clock Control and Generation Bus Timing Clock Startup from POR or LVI Reset Clocks in Stop Mode and Wait Mode Reset and System Initialization External Pin Reset Active Resets from Internal Sources Power-On Reset Computer Operating Properly (COP) Reset Illegal Opcode Reset Illegal Address Reset Low-Voltage Inhibit (LVI) Reset Monitor Mode Entry Module Reset (MODRST) Freescale Semiconductor

15 15. SIM Counter SIM Counter During Power-On Reset SIM Counter During Stop Mode Recovery SIM Counter and Reset States Exception Control Interrupts Hardware Interrupts SWI Instruction Interrupt Status Registers Reset Break Interrupts Status Flag Protection in Break Mode Low-Power Modes Wait Mode Stop Mode SIM Registers Break Status Register SIM Reset Status Register Break Flag Control Register Chapter 16 Serial Peripheral Interface (SPI) Module 16.1 Introduction Features Pin Name Conventions Functional Description Master Mode Slave Mode Transmission Formats Clock Phase and Polarity Controls Transmission Format When CPHA = Transmission Format When CPHA = Transmission Initiation Latency Queuing Transmission Data Error Conditions Overflow Error Mode Fault Error Interrupts Resetting the SPI Low-Power Modes Wait Mode Stop Mode SPI During Break Interrupts I/O Signals MISO (Master In/Slave Out) Freescale Semiconductor 15

16 Table of Contents MOSI (Master Out/Slave In) SPSCK (Serial Clock) SS (Slave Select) CGND (Clock Ground) I/O Registers SPI Control Register SPI Status and Control Register SPI Data Register Chapter 17 Timebase Module (TBM) 17.1 Introduction Features Functional Description Interrupts TBM Interrupt Rate Low-Power Modes Wait Mode Stop Mode Timebase Control Register Chapter 18 Timer Interface Module (TIM) 18.1 Introduction Features Pin Name Conventions Functional Description TIM Counter Prescaler Input Capture Output Compare Unbuffered Output Compare Buffered Output Compare Pulse Width Modulation (PWM) Unbuffered PWM Signal Generation Buffered PWM Signal Generation PWM Initialization Interrupts Low-Power Modes Wait Mode Stop Mode TIM During Break Interrupts I/O Signals I/O Registers TIM Status and Control Register TIM Counter Registers Freescale Semiconductor

17 TIM Counter Modulo Registers TIM Channel Status and Control Registers TIM Channel Registers Chapter 19 Development Support 19.1 Introduction Break Module (BRK) Functional Description Flag Protection During Break Interrupts CPU During Break Interrupts TIM During Break Interrupts COP During Break Interrupts Break Module Registers Break Status and Control Register Break Address Registers Break Auxiliary Register Break Status Register Break Flag Control Register Low-Power Modes Monitor ROM (MON) Functional Description Normal Monitor Mode Forced Monitor Mode Monitor Vectors Data Format Break Signal Baud Rate Commands Security Chapter 20 Electrical Specifications 20.1 Introduction Absolute Maximum Ratings Functional Operating Range Thermal Characteristics Vdc Electrical Characteristics Vdc Electrical Characteristics Volt Control Timing Volt Control Timing Clock Generation Module Characteristics CGM Component Specifications CGM Electrical Specifications Volt ADC Characteristics Volt ADC Characteristics Freescale Semiconductor 17

18 Table of Contents Timer Interface Module Characteristics Volt SPI Characteristics Volt SPI Characteristics Memory Characteristics Chapter 21 Ordering Information and Mechanical Specifications 21.1 Introduction MC Order Numbers Freescale Semiconductor

19 Chapter 1 General Description 1.1 Introduction The MC68HC908GR16 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.2 Features For convenience, features have been organized to reflect: Standard features of the MC68HC908GR16 Features of the CPU Standard Features of the MC68HC908GR16 Features of the MC68HC908GR16 include: High-performance M68HC08 architecture optimized for C-compilers Fully upward-compatible object code with M6805, M16805, and M68HC05 Families 8-MHz internal bus frequency Clock generation module supporting 32-kHz to 100-kHz crystals FLASH program memory security (1) On-chip programming firmware for use with host personal computer which does not require high voltage for entry In-system programming (ISP) System protection features: Optional computer operating properly (COP) reset Low-voltage detection with optional reset and selectable trip points for 3.3-V and 5.0-V operation Illegal opcode detection with reset Illegal address detection with reset Low-power design; fully static with stop and wait modes Standard low-power modes of operation: Wait mode Stop mode Master reset pin and power-on reset (POR) 16 Kbytes of on-chip 100k cycle write/erase capable FLASH memory 1. No security feature is absolutely secure. However, Freescale s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor 19

20 General Description 1 Kbyte of on-chip random-access memory (RAM) 06 bytes of FLASH programming routines read-only memory (ROM) Serial peripheral interface (SPI) module Enhanced serial communications interface (ESCI) module LIN specific enhanced features: Generation of LIN 1.2 break symbols without extra software steps on each message Break detection filtering to prevent false interrupts Two 16-bit timer interface modules (2-channel TIM1 and 2-channel TIM2) with selectable input capture, output compare, and pulse-width modulation (PWM) capability on each channel Up to 8-channel, 10-bit successive approximation analog-to-digital converter (ADC) depending on package choice BREAK (BRK) module to allow single breakpoint setting during in-circuit debugging Internal pullups on IRQ and RST to reduce customer system cost Up to 37 general-purpose input/output (I/O) pins, including: 28 shared-function I/O pins Up to nine dedicated I/O pins, depending on package choice Selectable pullups on inputs only on ports A, C, and D. Selection is on an individual port bit basis. During output mode, pullups are disengaged. High current 10-mA sink/source capability on all port pins Higher current 20-mA sink/source capability on PTC0 PTC Timebase module (TBM) with clock prescaler circuitry for eight user selectable periodic real-time interrupts with optional active clock source during stop mode for periodic wakeup from stop using an external crystal User selection of having the oscillator enabled or disabled during stop mode Up to 8-bit keyboard wakeup port depending on package choice 5 ma maximum current injection on all port pins to maintain input protection Available packages: 32-pin LQFP 8-pin low-profile quad flag pack (LQFP) Specific features of the MC68HC908GR16 in 32-pin LQFP are: Port A is only bits: PTA0 PTA3; -pin keyboard interrupt (KBI) module Port B is only 6 bits: PTB0 PTB5; 6-channel ADC module Port C is only 2 bits: PTC0 PTC1 Port D is only 7 bits: PTD0 PTD6; shared with SPI, TIM1, and TIM2 modules Port E is only 2 bits: PTE0 PTE1; shared with ESCI module Specific features of the MC68HC908GR16 in 8-pin LQFP are: Port A is 8 bits: PTA0 PTA7; 8-pin KBI module Port B is 8 bits: PTB0 PTB7; 8-channel ADC module Port C is only 7 bits: PTC0 PTC6 Port D is 8 bits: PTD0 PTD7; shared with SPI, TIM1, and TIM2 modules Port E is only 6 bits: PTE0 PTE5; shared with ESCI module 20 Freescale Semiconductor

21 MCU Block Diagram Features of the CPU08 Features of the CPU08 include: Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the HC05) 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908GR Pin Assignments Figure 1-2 and Figure 1-3 illustrate the pin assignments for the 32-pin LQFP and 8-pin LQFP respectively. Freescale Semiconductor 21

22 General Description CPU REGISTERS M68HC08 CPU CONTROL AND STATUS REGISTERS 6 BYTES USER FLASH 15,872 BYTES USER RAM 102 BYTES MONITOR ROM 350 BYTES FLASH PROGRAMMING ROUTINES ROM 06 BYTES USER FLASH VECTOR SPACE 36 BYTES OSC1 OSC2 CGMXFC RST (3) IRQ (3) V DDAD /V REFH V SSAD /V REFL V DD V SS V DDA V SSA ARITHMETIC/LOGIC UNIT (ALU) CLOCK GENERATOR MODULE khz OSCILLATOR PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE POWER INTERNAL BUS PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE SERIAL PERIPHERAL INTERFACE MODULE MONITOR MODULE MEMORY MAP MODULE CONFIGURATION REGISTER 1 2 MODULE DDRA PORTA DDRB PORTB DDRC DDRD DDRE PORTC PORTD PORTE PTA7/KBD7 PTA0/KBD0 (1) SECURITY MODULE PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB/AD PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6 (1) PTC5 (1) PTC (1), (2) (1), (2) PTC3 (1), (2) PTC2 PTC1 (1), (2) PTC0 (1), (2) PTD7/T2CH1 (1) PTD6/T2CH0 (1) PTD5/T1CH1 (1) PTD/T1CH0 (1) PTD3/SPSCK (1) PTD2/MOSI (1) PTD1/MISO (1) PTD0/SS (1) PTE5 PTE2 PTE1/RxD PTE0/TxD MONITOR MODE ENTRY MODULE 1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device Figure 1-1. MCU Block Diagram 22 Freescale Semiconductor

23 Pin Assignments OSC1 OSC2 CGMXFC V SSA V DDA PTC1/CAN RX PTC0/CAN TX PTA3/KBD3 RST PTA2/KBD2 PTE0/TxD 2 23 PTA1/KBD1 PTE1/RxD 3 22 PTA0/KBD0 IRQ 21 V SSAD /V REFL PTD0/SS 5 20 V DDAD /V REFH PTD1/MISO 6 19 PTB5/AD5 PTD2/MOSI 7 18 PTB/AD PTD3/SPSCK PTB3/AD3 V SS V DD PTD/T1CH0 PTD5/T1CH1 PTD6/T2CH0 PTB0/AD0 PTB1/AD1 PTB2/AD2 Figure Pin LQFP Pin Assignments 37 RST PTE0/TxD 2 PTE1/RxD 3 PTE2 PTE3 5 PTE 6 PTE5 7 IRQ 8 PTD0/SS 9 PTD1/MISO 10 PTD2/MOSI OSC2 CGMXFC V SSA V DDA PTC1/CAN RX PTC0/CAN TX PTA7/KBD7 PTA6/KBD6 PTA5/KBD5 PTA/KBD PTA3/KBD3 11 PTD3/SPSCK OSC1 PTA2/KBD2 35 PTA1/KBD1 3 PTA0/KBD0 33 PTC6 32 PTC5 31 V SSAD /V REFL 30 V DDAD /V REFH 29 PTB7/AD7 28 PTB6/AD6 27 PTB5/AD PTB/AD PTB3/AD3 V SS V DD PTD/T1CH0 PTD5/T1CH1 PTD6/T2CH0 PTD7/T2CH1 PTC2 PTC3 PTC PTB0/AD0 PTB1/AD1 PTB2/AD2 Figure Pin LQFP Pin Assignments Freescale Semiconductor 23