L1Calo Status Report. efex jfex gfex L1Topo ROD Hub TREX FOX Mapping FTM Link-Speed Tests. 15 October 2015 Ian Brawn, on behalf of L1Calo 1

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1 L1Calo Status Report efex jfex gfex L1Topo ROD Hub TREX FOX Mapping FTM Link-Speed Tests 15 October 2015 Ian Brawn, on behalf of L1Calo 1

2 Sent to manufacture 24/7/15 Bare board (for impedance testing) expected ~today Assembled module expected 30th October efex Firmware All IBERT cores generated Control FPGA FPGA interface in development All L1Calo modules IPBus Common Register definition proposed at L1Calo Weekly meeting Incorporating feedback efex layout Simulation results from HyperLynx for typical track, attenuation vs. frequency 15 October 2015 Ian Brawn, on behalf of L1Calo 2

3 jfex Simplified board design Eliminated Merger FPGA Control mezzanine Modular design for Mpod + Processor FPGA blocks Time reduction in board design Schematics almost finished; layout ongoing On schedule for Q manufacture 3D model of fibre routing developed Working on problems exposed at Join meeting Firmware in development 15 October 2015 Ian Brawn, on behalf of L1Calo 3

4 gfex Prototype 1a, no. 1 & 2: Without/w ith Proc FPGA (XC7VX550T) Pow er, clock & Zynq commissioned M GTs: 12.8 Gb/s, BER < GTH (pfpga)+ 16 GTX (Zynz) simultaneously Prototype 1b Re-w ork (CDC->SiLab clock, DDR3, PHY) M anufacture 24 Sept Prototype 2b: Full prototype Design changes 4 V7 3 Ultrascale (XCVU160) Redundant readout via Hub-ROD removed (readout via FELIX) M anufacture end of year Routing well advanced Firmw are Control Test engines Done Algorithmic GBT & TTC interfaces gfex Prototype 1a, no. 2 IBERT eye for pfpga Fibre 12.8 Gb/s 15 October 2015 Ian Brawn, on behalf of L1Calo 4

5 Expect only minor changes to Topo required at Phase-I Mezzanine upgrade for readout via 2 L1Calo Hub- RODs But also plan to implement Phase-II requirements at Phase-I Real-time RoI outputs Associated with L1As L1Topo Need to evaluate (for Phase II) Scale of required changes Optimum system architecture L1Topo upgrade plan Run-2 L1Topo Currently, L1Topo effort bound up in Run October 2015 Ian Brawn, on behalf of L1Calo 5

6 Initial layout completed in July Power-supply issue : Switching noise from GE modules few x 10 mv Solution: ferrite inductors & isolated ground planes ROD PCB manufacture underway Quotes for assembly collected ROD prototype, 3D model Fully assembled module expected end of November Firmware First draft of firmware specification circulated within L1Calo Power-Supply Test Board 15 October 2015 Ian Brawn, on behalf of L1Calo 6

7 Delicate design process required at the ROD/Hub interface Tight space limitations after making space for ROD FEX data fidelity to ROD remains the driving design philosophy Layout and routing underway Assembled modules anticipated mid December early January. TTC SFP+ connector removed from design. All optical I/O will be performed via minipod Hub Firmware design progressing in parallel to board design. Hub Layout 15 October 2015 Ian Brawn, on behalf of L1Calo 7

8 Design and production of demonstrator complete: Lar/TileFOX Demonstrator e/j/gfox Demonstrator 2U boxes with MTP connectors fanout cables, Internal LC connectors, Splitters FOX FOX, block diagram FOX Demonstrator Module Fibre fuser purchased, will start tests Mapping Georges Aad & Michael Begel have been working on mappings since Spring Work well progressed Schedule for documentation to be written in September, but not happened yet 15 October 2015 Ian Brawn, on behalf of L1Calo 8

9 TREX PDR held on 31st July PDR Agenda: Specification: 71/0.2 Report now public: Design approved TREX not part of TDR design Approval: panel recommends TREX be adopted by ATLAS Actions identified include Investigations into M GT clocking scheme Power & cooling Fibre mechanics TREX Block Diagram M anufacture Q Recruitment required 15 October 2015 Ian Brawn, on behalf of L1Calo 9

10 FTM Simpler design than efex but same PCB material & build 2 assembled FTMs delivered Initial tests underway Some problems connecting with JTAG chain Firmware development Control IPBus readout of FPGA temperatures and voltages added Work on MGTs underway FTM Prototype 15 October 2015 Ian Brawn, on behalf of L1Calo 10

11 Link-Speed Tests Hardware Schedule Slip in efex schedule link-speed tests late January LAr informed jfex will arrive too late for LAr deadline L1Calo must define how extrapolate from efex test results to jfex conclusions LAr L1Calo Meeting 15th Oct, 4pm Discussion of Schedule: to fix dates of tests Test Lab: location, identification of joint infrastructure Long-term facility for LAr-L1Calo-etc. tests Firmware: requirements, link protocol, test patterns Test Plan: Review of latest document Manufacture additional gfex to provide focus for test rig commissioning? Evaluate schedule to assess benefit 15 October 2015 Ian Brawn, on behalf of L1Calo 11