System overview Production status. MPD firmware upgrade. Front Tracker boards SID equipment Back Tracker (UVa) FIR blocks Optical interface

Transcription

1 1 GEM Readout and DAQ System overview Production status Front Tracker boards SID equipment Back Tracker (UVa) MPD firmware upgrade FIR blocks Optical interface Paolo Musico and Evaristo Cisbani

2 2 APV25 front-end Several versions developed to adapt detector readout lines 3 production versions used v 4.0 v 4.11 v 4.11SID Front Tracker GEM Back Tracker GEM (UVa) SID (same PCB, DC coupling)

3 3 Backplanes Used in the Front Tracker with RH LVPS July 20 Original design for the Back Tracker (UVa) with RH LVPS

4 4 New 5 slots backplane design Rigido-flex PCB, with reduced material budget; removed LVPS regulators Slightly better noise performances Easier assembly procedure for vertical arrangment of front-ends SID use: avoid noisy kapton adapters

5 5 New Backplanes for Back Tracker (UVa) 3-D Cad screenshots Prototypes ready to be shipped Removed LVPS regulators, reduced material

6 6 UVa EES July 20

7 7 Multi Purpose Digitizer Two versions around v 4.0 will be used in production Try to keep FPGA versions alive for both MPD v 3.0 MPD v 4.0

8 8 MPD block diagram JLAB July 2015

9 9 The 1 st Front Tracker chamber at Jlab Horizontal rigid backplane Vertical rigido-flex backplane HDMI cables patch panels Short (3m) HDMI cables

10 10 Front Tracker Board status APV Front End All boards are in lab, a lot still need testing Backplanes All rigid boards are ready for assembly Rigido-flex used on first chamber for vertical assembly; needed procurement for other chambers MPD Boards ready, firmware under revision

11 11 SID electronics Adoption of rigido-flex backplane Use of APV front-end cards with 130 pin Panasonic connector to connect the detector avoiding noisy kapton adapter Production started for 66 APV front-ends New backplanes have to be ordered

12 12 Back Tracker electronics (UVa) New design for 5 & 12 slots backplanes Reduced material budget Started prototypation for pieces Updated design for the APV front-end Already prototypied in the past, but adopted same APV footprint as front-tracker boards to optimize bonding process Started prototypation for 25 pieces p yp p

13 13 Back tracker procurement APV front-end 25 ordered, production started Asked quotation for whole production, including bonding, excluding APV and Panasonic connector: 580 pieces: each 800 pieces: each Backplanes 5 and 12 slots prototypes ordered, production almost ready Asked quotation for whole production : MPD 27 and slots: and each respectively 54 and 80 5-slots: and each respectively Asked quotation for whole production: 38 pieces: 1713,90 each 55 pieces: each

14 14 MPD Firmware status Basic firmware used up to now: Raw data readout from APV channels fifo Event building present, but never used Simple VME 32-bit block transfer only Resources used: Logic utilization: 44 % Total registers: 9565 Total block memory bits: 1,268,864 ( 50 % ) DSP block 9-bit elements: 0

15 15 MPD basic FPGA block diagram July 20

16 16 Channel Channel processor block diagram for the basic version

17 17 Basic Firmware + FIR Following Chris measurements implemented FIR filter on incoming data lines to mitigate impedance mismatching and reduce noise on long HDMI cables New resource accounting with 16 x 8 tap FIR: Logic utilization: 45 % Total registers: 9871 Total block memory bits: 1,268,864 ( 50 % ) DSP block 9-bit elements: 256 (100 %)

18 18 FIR principle July 20 APV25 sync pulse sampled by MPD Raw data: pulse response 8 tap FIR filter applied Cleaner signal, but not enough for 23 m cable

19 19 12 tap FIR 8 tap FIR gives 60 ADC counts peak noise (starting point was 120 ADC counts) To gain something more implemented 12 tap FIR: Logic utilization: 77 % Total registers: Total block memory bits: 1,268,864 ( 50 % ) DSP block 9-bit elements: 256 (100 %) This gives 30 ADC counts peak noise level but it uses too many resources!

20 20 New firmware version VME interface modified: handles also 64 bit 2eVME and 2eSST cycles Uses 128 MB DDR SDRAM for data buffering No FIR, no data compression To be extensively tested Logic utilization: 56 % Total registers: Total block memory bits: 1,808,252 ( 72 % ) DSP block 9-bit elements: 0

21 21 FPGA enhanced version July 20

22 22 Enhanced with optical readout Removed VME interface Added NIOS system to handle GBE UDP for configuration and slow accesses DDR SDRAM used by NIOS system Added HW UDP packet generator for fast data transfer No FIR Logic utilization: 66 %??? Total registers: Total block memory bits: 1,117,429 ( 44 % ) Some implementation problems to be solved

23 23 FPGA with optical interface July 20

24 24 Data compression Some thoughts about data reduction to minimize bandwith Needs to analyze up to 6 consecutive samples (for each channel) to evaluate arrival time and peak value A lot of memory (RAM/FIFO) is required Not sure to be easily implemented in the actual device: a tentataive implementation failed...

25 25 MPD Firmware summary table Logic N. Memory DSP Notes % registers % % Basic (v3) Basic + 8 tap FIR Basic +12 tap FIR Too much! Basic +10 tap FIR Enhanced, no FIR (v4) Optical, no FIR (v4) Very preliminary, still some implementation problem

26 26 Asintotic production version 10 tap FIR??? Other (simpler) alghorithm??? Optical GBE??? Aurora??? Data reduction algorithm???

27 27 Question time JLAB July 2015