Insights into MCU & Mixed Signal Design

Transcription

1 Insights into MCU & Mixed Signal Design Renesas Electronics America Inc.

2 Renesas Technology & Solution Portfolio 2

3 Microcontroller and Microprocessor Line-up bit 8/16-bit 1200 DMIPS, Superscalar Automotive & Industrial, 65nm 600µA/MHz, 1.5µA standby 500 DMIPS, Low Power Automotive & Industrial, 90nm 600µA/MHz, 1.5µA standby 165 DMIPS, FPU, DSC Industrial, 90nm 200µA/MHz, 1.6µA deep standby 25 DMIPS, Low Power Industrial & Automotive, 150nm 190µA/MHz, 0.3µA standby 10 DMIPS, Capacitive Touch Wide Industrial Format & LCDs Automotive, 130nm 350µA/MHz, 1µA standby 1200 DMIPS, Performance Automotive, 40nm 500µA/MHz, 35µA deep standby 165 DMIPS, FPU, DSC Industrial, 40nm 200µA/MHz, 0.3µA deep standby Embedded Security, ASSP Industrial, 90nm 1mA/MHz, 100µA standby 44 DMIPS, True Low Power Industrial & Automotive, 130nm 144µA/MHz, 0.2µA standby 3

4 Enabling The Smart Society Challenge: Ever increasing automotive requirements result in the demand to integrate complex MCU and Mixed Signal devices with features that are seemingly impossible to realize. What steps can be taken during development to achieve the unattainable? Solution: This class will introduce complexities dealt with during MCU and Mixed Signal development and the design steps taken to address some of these difficult automotive requirements. 4

5 Agenda: MCU MCU Introduction Development Flow Specification Front-End Back-End Challenges during development Automotive Requirement: Power Reduction Power modes Power switches Power domains 5

6 MCU Development: WHAT OUR SALES PEOPLE THINK WE DO 6

7 MCU Development: WHAT OUR SALES PEOPLE TELL OUR CUSTOMERS WE DO 7

8 MCU Development: WHAT WE THINK WE DO 8

9 MCU Development: WHAT WE ACTUALLY DO 9

10 MCU = Micro-Controller Unit 1 x Timer Array Unit (1 x 16ch TAUA) 3 x CSI with FIFO 5 x Multi LIN Master On-Chip Debug 1 x OSTM Window Watchdog 2 x CSI 4 x I 2 C 5 x UART LIN compatible 4 x I 2 S 2 x PCM A/D Converter 16ch / 10-bit 2MB CODE FLASH (ROM) External bus I/F (SRAM&SDRAM) PLL & SSCG Package: 144pin QFP 32-bit CPU 160 MHz operation I/O : V Internal : V -40 to +85C / +105C Memory 32KB Data Flash 64KB Local RAM System Protection Function 16 x DMA 2 x afcan (2 x 64msg afcan) MLB IE Bus Stand-by Control 1 x Timer Array Unit (1 x 4ch TAUJ) RTC (Watch Timer) Window Watchdog Key Return Main OSC 4 to 20MHZ Internal OSC 240kHz + 8MHZ SubClk 32kHz 10

11 MCU Development Flow 11

12 MCU Development Flow: REQUIREMENTS Customer Input Market Input System Design information SPEC FRONT- END NETLIST BACK- END MASK DATA IP Design Libraries Macros FRONT-END: Creation of NETLIST from Specification BACK-END: Creation of Layout Data (Mask Data) from NETLIST 12

13 Specification Creation: Information for Design (FE and BE) Information for User s Manual creation Information for Test Development Information for Tools Development 13

14 Front-End Development: NETLIST: ASCII representation of entire device used for functional verification, timing verification, physical layout tools. Verification: Confirm that NETLIST functionality meets system specification; confirm that timing specification can be met. Test Pattern Generation: based on functional simulation, generate patterns to be used for qualification and mass production testing. 14

15 Back-End Development: Floor plan: placement of hard macros and I/O I/O Ring development Power Grid Place/route soft macros Physical Verification (DRC/LVS) Design For Test insertion ONE KEY GOAL: Reduce Size = Reduce Cost! Hard Macro: process-specific circuit with fixed physical dimension and layout Soft Macro: process-independent circuit; physical placement modified to match floorplan requirements 15

16 Challenges Along the Way 16

17 Complexities of Functional Integration Feature Reduction: Memory Size Macro reduction 128K RAM Pin Function Assignment: Multiplex functions Power/Ground pair requirements 96K RAM Clocking/Reset Assignment: Macro clock selection Clock and reset synchronization 5 X UART LIN compatible 4 X UART LIN compatible 17

18 Pin Function Assignment Power/Ground pair requirements Multiplex functions - How many core pair required? - How many I/O pair required? - Function specific power pairs required? - Application feasibility? - Design feasibility? - Timing feasibility (cross-chip timing)? 18

19 Clock Distribution Macro clock selection Clock and reset synchronization Slow clock PLL FLASH ROM Fast clock CPU RAM REALLY Slow clock Low-performance bus High-performance bus Clock Divder PERIPHERALS RESET Reset Sync Port and macro function I/O 19

20 FRONT END: Timing Closure ON-CHIP TIMING Static Timing Analysis: Hold violations Setup violations Clock Tree Synthesis: Clock skew OFF-CHIP TIMING Application Timing Requirements: Off-chip delays Round-trip timing 20

21 Static Timing Analysis (STA) D CLK Q CLK D tsu th td tsu = setup time th = hold time td = delay time Q How many setup and hold checks are we talking about??? SIGNAL_A SIGNAL_X SIGNAL_Y SIGNAL_B MILLIONS! 21

22 Clock Skew A B A B CLK C D CLK C D CTS Buffer CLK CLK_A CLK_B CLK_C CLK_D CTS = CLOCK TREE SYNTHESIS 22

23 Application Timing Off-chip Delays: a. Capacitive load b. Size of buffer Spec Item Symbol Condition Unit MIN. TYP. MAX. IISAnWS (output) Duty Cycle % IISAnSCK Edge to IISAnWS output delay time t WSOD 25 ns IISAnSCK Edge to IISAnWS output hold time t WSOH 0 ns IISAnSCK clock period T 140 ns IISAnSCK clock low-level width t SCKL 65 ns IISAnSCK clock high-level width t SCKH 65 ns IISAnSCK Edge to IISAnSDO output delay time t SDOD 10 ns IISAnSCK Edge to IISAnSDO output hold time t SDOH 0 ns IISAnSDI Edge to IISAnSCK falling Setup t SDIS 45 ns IISAnSDI Edge to IISAnSCK falling Hold t SDIH 0 ns Round Trip Timing: External DRAM example (READ) 23

24 BACK END: Physical Constraints and Concerns Routing Congestion: Hard macro/soft macro ratio Impact to signal timing Impact to chip size Size Minimization: I/O defined or Core defined? Aspect ratio decisions Packaging Rules: Wire bonding & I/O location 24

25 PACKAGING: Wire Bonding Issues Wire length Wire angles Double bonding Non-connected pads 25

26 Power Reduction 26

27 Power Reduction Leakage current at small geometries: Temperature effects Transistor speed Power/Standby Modes: Power/clock control Transitioning between modes Leakage Current (ua) M H Power Domains: On-chip power switches Signals crossing boundaries Tj (C) 27

28 Power Mode Transitioning Power ON Power OFF Reset HALT mode (ISO1 DeepStop) AWO Iso0 Iso1 Stop mode (ISO1 DeepStop) AWO Iso0 Iso1 AWO Iso0 Iso1 Run mode (ISO1 DeepStop) AWO Iso0 Iso1 DeepStop mode Run mode AWO Iso0 Iso1 AWO Iso0 Iso1 Run mode (ISO1 Stop) AWO Iso0 Iso1 HALT mode AWO Iso0 Iso1 Stop mode AWO Iso0 Iso1 28

29 Power Switches On-chip power switches: Many switches needed Switches reduce usable area Must be timed during power sequencing Flash SRAM SRAM SRAM SRAM CPU Core SRAM SRAM VDD V14 Stack Via V14 Stack Via BURAM Flash Always-ON (1.2V) SRAM SRAM Isolation-0 (PSO: 1.2V) Isolation-1 (PSO: 1.2V) 5V for Flash Global VDD Switched VDD for Isolation-0 Switched VDD for Isolation-1 繋がない 繋がない PA M6M M5 M4 M3 M2 M1 SW Cell SW SRAM SW Cell SW VDD Cell スタンダードセル standard cell SW VSD マクロ SRAM SRAM macro SW VSD (Separated Vdd) VDD Power Switch Tr. TAP VSD スタンダードセル用電源スイッチ Power switch for standard cell マクロ専用電源スイッチ Power switch for HW macro Isolation Area GND 29

30 Power Domains and Boundaries Signals crossing boundaries: Every signal that crosses from one power domain to another must have masking logic in the event of power domain shut-off. AWO Mask signal from Power sequencer PWSEQ0 PWSEQ1 PWMASK PWMASK ISO0 ISO1 30

31 Agenda: Mixed Signal The Automotive Environment Mixed-signal Semiconductor Golden Rules Accuracy & matching Limitations Low-side Driver Circuit Design Example Basic functionality EMI Protection Detection Quality 31

32 The Automotive Environment 32

33 Dealing with a Wide Voltage Range Bus Lines Reverse Battery NOP Start Bootstrap + Double Normal Operation Load Dump Special Stop Battery Applications Alternator Output Voltage vs. Temp Battery Voltage as a Function of Car Speed Alternator Ripple 3V 33

34 Many More Challenges Temperature Range Special Body & Convenience "Under Hood" Self heating Applications (Ignition) Electro Magnetic Interference (EMI) Immunity Emissions Electro Static Discharge (ESD) 2kV HBM minimum for all pins 4kV signal lines leaving ECU 6-8kV communications bus lines 34

35 Mixed-signal Semiconductor Golden Rules 36

36 Accuracy & Matching In a semiconductor process the absolute value of parameters varies significantly but the same devices match very well Two Golden Rules of IC design: Do not rely on absolute tolerances (poor accuracy) Resistors typically ± 20% Capacitors typically ± 10% β, µ N/P typically ± 30% Rely on component matching 0.1% is possible Ratio design techniques using unit devices Matched layout techniques 37

37 Limitations Every device component has limitations 3.3V 5V 45V VGS < 4.0 < 7.0 < 7.0 VDS < 4.0 < 7.0 < 45.0 Matching Leakage Area 38

38 Achieving High Quality Starts at the Beginning! Design and system-level Failure Mode Effects Analysis (FMEA) Design For Test (DFT) Automatic Test Pattern Generation (ATPG) Full scan path for optimal test coverage Logic supply quiesent current (IDDQ) SHOrt Voltage Elevation (SHOVE) Gate stress tests Six-sigma Design Corner simulation (process, temperature, supply, load) Monte-Carlo simulation Allows Part Average Testing (PAT) and outlier screening Others Design reuse Expert reviews 39

39 Low-side Driver Circuit Design Example 40

40 Circuit Design Let s look at the design of a low-side driver Step-by-step: Basic functionality EMI Protection Detection Quality 41

41 Basic Functionality Turn on/off lowside driver Positive Supply Voltage Input Threshold Detection Gate Drive Stage Low-side Driver Output Digital Input Control Pin Power MOSFET Output Stage Supply Reference Voltage 42

42 Test Bench 1. Driver block from previous page 2. Power supplies (5V and 12V) 3. Control input 4. Application Circuitry 5. Wiring inductance 6. EMI Simulation 43

43 Basic Functionality Issues? High peak current caused by charging the EMI capacitor 44

44 Basic Functionality Issues - Zoom Fast turn-on creates a high current (I = CdV/dt) Current spike causes EMI issues 45

45 Basic + EMI Charge/discharge gate with a small constant current Reduces slew rate which improves EMI 1. Original control circuit 2. Add current mirrors 46

46 Basic + EMI 47

47 EMC Improvement - CISPR25 Class 5 limit New circuit passes CISPR25 class 5 70dBuV ( MHz) 54dBuV ( MHz) Old circuit CISPR25 class 2 only! 70dBuV ( MHz) 54dBuV ( MHz) 48

48 Basic + EMI + Short Circuit Protection Short to battery will create a high current limited only by the on resistance of the output driver Add current limitation circuit 1. Current sense 2. Voltage reference 3. Control amplifier (constant current output) Control switching 4. Current mirror 5. Control switches 49

49 Basic + EMI + Short Circuit Protection Simulation Results Increased output current Decreased gate drive voltage Normal load Short to battery Without Current Limit (No self heating) 50

50 Basic + EMI + Short Circuit Protection System considerations Power dissipation in a short circuit condition is too high for the device in many cases Power dissipation can be handled by: Thermal shutdown Auto restart for a x number of cycles before latching off Over-current detection and shut-down Short detection debounce to limit temperature increase Fast thermal transients > 60 C will reduce the lifetime of the part 51

51 Basic + EMI + Short Circuit Protection + ESD +/- 4kV HBM applied at out pin Positive ESD - Add gate trigger structure Negative ESD Use body diode of power transistor 1. Gate trigger 2. Gate charge current block 3. Gate source protection 4. Current limiting resistor 52

52 Basic + EMI + Short Circuit Protection + ESD System considerations Wiring to the load introduces an inductance Depending on the turn-off slew rate this can create a high voltage at the output The ESD protection can be used to clamp the inductive energy Energy capability changes with device size and dissipation time Energy must be within SOA of the device o Base on T-SOA measurement data o Thermal simulation If energy is too high for the power driver An external clamp or freewheel diode must be added 53

53 Open Load (OL) and Short to GND (S2GND) 1. Reference voltage generation 2. Polarization buffer (current limited) 3. Open load comparator 4. Short to ground comparator 54

54 Open Load (OL) and Short to GND (S2GND) Simulation 55

55 Open Load (OL) and Short to GND (S2GND) Problems? There s a subtle error, a snake in the grass Out pin is high voltage and low voltage circuits require protection 56

56 Open Load (OL) and Short to GND (S2GND) Simulation Protection transistor introduces small voltage drop (20mV) 57

57 Questions? 58

58 Enabling The Smart Society Challenge: Ever increasing automotive requirements result in the demand to integrate complex MCU and Mixed Signal devices with features that are seemingly impossible to realize. What steps can be taken during development to achieve the unattainable? Solution: This class will introduce complexities dealt with during MCU and Mixed Signal development and the design steps taken to address some of these difficult automotive requirements. 59

59 Renesas Electronics America Inc.

60 Josh Lawton: Sr. Staff Engineer Education BSEE: University of New Hampshire 1998 Author of Mixed-signal Portion and Originally Scheduled Presenter 12 Years Semiconductor Industry Experience 11 Yrs: Elmos North America Inc. Mixed signal design Bar code scanner, squib drivers, buckle switch interface, sensor interface, door zone module, PWM relay driver, SWCAN, compass interface, EC mirror control, ion sense IGBT driver, and window lift 1 Yr: Renesas Electronics America Inc. Mixed signal design Airbag ASSPs 61