SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions
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1 SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions Patrice Joubert Doriol 1, Aurora Sanna 1, Akhilesh Chandra 2, Cristiano Forzan 1, and Davide Pandini 1 1 STMicroelectronics, Central CAD and Solutions, Agrate Brianza, Italy 2 STMicroelectronics, Central CAD and Solutions, Greater Noida, India Signal And Power Integrity Workshop, May 16 th, 2012, Sorrento, ITALY
2 Today s I/Os Challenges 2 Higher I/O count Increasing operating frequencies Faster signal edge rates High I/O density makes it difficult to place PCB decaps close enough to the pads Automotive specific challenge: I/Os signal conducted EMI EMC and signal integrity are another mandatory objective for first silicon success
3 EMC At The End Of The Design Flow 3
4 Our Vision: EMC-Aware Design 4 Architectural Design DESIGN EMC Tools EMC Design Guidelines EMC Training Floorplan Synthesis and Place&Route Verification EMC Models EMC Simulations Compliance? NO YES FABRICATION EMC compliant
5 Gnd Reflection, Crosstalk, And SSO Noise 5 Victim +_+_+_ Trace 1 Gnd +_ Chip 2 Gnd +_+_+_ Trace 2 Gnd +_ Chip 1 +_ Gnd Trace3
6 SSO Noise And Conducted EMI 6 Switching aggressor VDD Stable victim VDD Stray capacitance I/O signal noise Ground inductance V = L di/dt Discharge current I/O signal conducted emissions
7 System-Level EMI Simulation Flow 7
8 I/O Ring Circuit 8 Any realistic signal integrity and EMI simulation must include the complete system-level macromodel (die, package, board) A full transistor-level simulation of the I/O ring is impractical even for a limited number of adjacent toggling I/Os and a given victim
9 SSO Flow 9
![I/O Bank For EMI Analysis 10 Conducted Emission Test Pin PG[11] VSS (0V) VDD (5V) PG15 PE14 PE15 PG10 PG11 PC3 PC2 PA5 PA6 TMS PC1 PAD_111 M BD2S3MS1ARUD_FC_ISO S PAD_78 BD2SS1RUD_FC_ISO PAD_79 M](/docs-images/86/93171682/images/10-3.jpg "BD2S3MS1ARUD_FC_ISO S PAD_106 BD2SS1RUD_FC_ISO PAD_107 M BD2S3MS1ARUD_FC_ISO S PAD_35 BD2SS1RUD_FC_ISO PAD_34 M BD2S3MS1ARUD_FC_ISO PAD_5 M BD2S3MS1ARUD_FC_ISO S PAD_6 BD2SS1RUD_FC_ISO PAD_TMS M")
10 I/O Bank For EMI Analysis 10 Conducted Emission Test Pin PG[11] VSS (0V) VDD (5V) PG15 PE14 PE15 PG10 PG11 PC3 PC2 PA5 PA6 TMS PC1 PAD_111 M BD2S3MS1ARUD_FC_ISO S PAD_78 BD2SS1RUD_FC_ISO PAD_79 M BD2S3MS1ARUD_FC_ISO S PAD_106 BD2SS1RUD_FC_ISO PAD_107 M BD2S3MS1ARUD_FC_ISO S PAD_35 BD2SS1RUD_FC_ISO PAD_34 M BD2S3MS1ARUD_FC_ISO PAD_5 M BD2S3MS1ARUD_FC_ISO S PAD_6 BD2SS1RUD_FC_ISO PAD_TMS M BD2S3MS1ARUD_FC_ISO F PAD_33 BD3M10FS1ARUDLP_FC_ISO VSS_HV_IO0_N0 VSSIO_ESDHV_FC_ISO VSS_HV_FLA0 VSSCO_FC_ISO VDD_HV_FLA0 VDDCO_FC_ISO VDD_HV_IO0_N0 VDDIO_FC_ISO Stable Victim Switching aggressors
11 Design Solutions For SSO Noise Reduction 11 I/Os signal skewing I/O ring fillercap insertion I/O pads reduced driving strength I/O ring power/ground supply placement
12 I/O Skewing Impact on EMI 12 Typical I/Os working frequency for automotive applications are in the range of a few KHz and do not need to toggle synchronously A relative skew in the range of about 10ns is compatible with a correct functionality of the I/O ring Harmonic amplitude reduction of several dbµvs obtained in the frequency range of 1GHz On some critical harmonics amplitude reduction of about 10dBµV
13 I/O Fillercaps Insertion And Driving Strength Reduction 13 I/O fillercap insertion did not prove to be an effective technique Huge amount of decaps and related area to achieve only few dbµv amplitude reduction Difficult to exploit this technique on typical pad-limited I/O rings I/O driving strength reduction (when compliant with the timing constraints) from MEDIUM to SLOW strength version can further reduce the SSO noise
14 SSO Flow Validation 14 The gate-level SSO flow was validated vs. full Spice-level simulations Aggr. PADs Input Victim PAD Output ELDO SSO 1 st Peak (mv) nd Peak (mv)
15 SSO Flow Validation 15 The gate-level SSO flow was validated vs. full Spice-level simulations Aggr. PADs Input Victim PAD Output ELDO SSO 1 st Peak (mv) nd Peak (mv)
16 IBIS For SSO And EMI Analysis 16 Traditionally IBIS models have been used for signal integrity simulations on system PCBs Behavioral modeling IP protection Fast simulation time Reasonable accuracy However IBIS v4.0 cannot include predriver and crossbar currents and I/O ring power/ground supply bouncing which is the dominant source of SSO and conducted EMI To validate IBIS v5.0 for EMI analysis the same STYY I/O bank was used IBIS v5.0 was compared vs. full transistor-level simulations
17 IBIS Validation Flow 17 I/Os IBIS model I/Os Spice netlist Package model (Ansys) Mentor Graphics ELDO Board model power and signal traces (Sigrity) Timedomain waveforms Frequency-domain analysis (MentorGraphics EZwave) SSO Spectra Conducted EMI
18 IBIS For SSO And EMI Analysis 18 IBIS v5.0 vs. Spice Time-domain analysis Frequency-domain analysis IBIS vs. Spice: good accuracy up to 2GHz
19 Summary 19 CAD flow and design solutions for SSO and I/O conducted EMI analysis and optimization were presented Methodology exploited on an industrial automotive microcontroller in ST 90nm with envm technology IBIS v5.0 can be used for a reliable SSO and EMI analysis
SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions
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