Low Power System Techniques

Transcription

1 June, 2010 Low Power System Techniques FTF-AUT-F0408 Carl Culshaw System Architect Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink

2 The lecture will: Introduction Focus on key low power challenges for the automotive system designer Describe the principal components of a microcontroller that help minimize power consumption Describe techniques to optimize their usage Discuss system partitioning approaches with a view to further reducing power Provide references and concepts to address the challenges identified Presenter: Carl Culshaw System Architect for Automotive Microcontroller Experience: Automotive Body, Low Power; 8, 16, and 32-bit Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 2

3 The lecture shall provide means to: Session Objectives Identify the key microcontroller elements to implement low power strategies Adopt technical approaches for their optimum usage Make the system architect aware of low power developments within the Automotive arena Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 3

4 Agenda Low Power Challenges Microcontroller Low Power Mechanisms Low Power System Techniques Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 4

5 Low Power Challenges 5

6 Power Trend Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 6

7 Semiconductor Technology Trends Source: TSMC 2009 As technology nodes increase more digital IP will be integrated but. Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 7

8 Semiconductor Technology Trends Source: TSMC 2009 the impact of Performance vs. Power trade-off is not to be underestimated. Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 8

9 CMOS Power & Energy Power Dynamic Power MCU Run Current Static Power MCU Stop Current P Where P P TOTAL DYNAMIC STATIC = P = α CV = I DYNAMIC STATIC V + P 2 f STATIC Computational Speed Supply Voltage Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 9

10 Dynamic versus Static Mode Consumption When an MCU is running Its transistors are switching Current is consumed at the point where the transistor switches. For example, in a CMOS inverter, at the point of switching both are on and an instantaneous current is drawn (crowbar effect) CMOS circuits dissipate power by charging the various load capacitances when switched. The more often the transistor switches, the more current is consumed. Dynamic current: Typically linear with operating frequency When an MCU is stopped Current is consumed due to leakage through the transistors. Sub-threshold/Channel Leakage: Occurs when the transistor gate is below the on threshold but a small current leaks from drain to source Becomes worse with reduced transistor size & higher temperature Drain to substrate leakage: The drain forms a diode with the substrate and there is a small leakage through this diode. P DYNAMIC = α Static current: Typically exponential with temperature CV 2 f P N 1 1 i Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 10

11 Increase in number of Number of Electronic Control Units ECU s (mostly MCUs) is increasing exponentially. Nodes requiring MCU functionality are replacing passive and mechanical systems throughout the vehicle. Nodes include measurement points, actuation points, or control. Often the vehicle architecture distributes some of the processing to local distributed nodes. Example Power consumption requirement is either flat or decreasing. The Low Power challenge: Power allowed per Electronic Control Unit (ECU) is decreasing. Low Power Challenge Automotive Total Sleep current requirement Source: J.Leohold, VW, 9 th International Automobile Electronics Conference, June 05 Windows & Mirrors.14 Security and Access..11 Comfort & Information..18 Lighting.22 Total.65 Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 11

12 Microcontroller Low Power Mechanisms 12

13 Reduces leakage current in low power modes Reducing Leakage Active Well Bias Changing the well voltage can reduce channel leakage by 10X. (Effectively, it increases Vth for the transistors.) Applicable to standard cell logic and RAM arrays N-Well Bias P-Well Bias Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 13

14 How it works: State Retention Power Gating Only D-Flip-Flops need to retain their state, all other logic can be powered down. In D-Flip-Flops, only the state keeping latch needs to be powered. Special power rail is only for retention latches Example: S12X core 15 µa consumption in state retention mode at 85C clki pgb clkb clk VDDC VDD d qb q Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 14

15 Power Segmentation MCU Structure Power Domains Individually disconnected from Power Eliminate leakage from areas that are turned off Power Domain PD0: Always on Wakeup periphery, e.g., CAN sampler, RTC, API, etc. Minimum RAM segment Power Domain RD1 Contains an additional RAM segment Remainder of the RAM is in the PD1 domain Power Domain PD1: Contains all cores and the majority of peripherals Can be turned off in STOP or STANDBY modes Must be turned on in RUN modes MPC5604B Power Domain Structure Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 15

16 Managing Clock Distribution Power consumption is directly linked to clock signal switching Reducing the number of clocked lines directly reduces current consumption Several methods are employed to avoid wasting power in clock edges, for example: P = a C l V dd ²f Clock freeze mode When CPU activity can be temporarily halted, e.g., while waiting for an Analog-to-Digital (ADC) conversion to complete Peripheral bus division Reduced local clock rates, e.g., for ADC and communication ports Clock gating Applied wherever possible and at the entry to each sub-module OSC 4-16MHz IRC 16MHz OSC 32KHz div 1 to 32 div 1 to 32 FMPLL irc_fast osca_cl ck oscb_clck irc_slow div 1 to 32 osca_clk_div irc_fast_div CMU System Clock Selector (ME) RESET SAFE INT system_clk div 1 to 15 div 1 to 15 div 1 to 15 irc_fact_div oscb_clk_div Core Platform Peripheral Set 1 Peripheral Set 2 Peripheral Set 3 API / RTC IRC 128KHz div 1 to 32 osca_clk irc_slow_div SWT (Watchdog) irc_fast fmplla_clk CLKOUT Selector div 1/2/4/8 CLOCK OUT MPC5603B Intelligent Clock Tree architecture Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 16

17 Fast Wake-Up: Intelligent Clocking Typical Clock Sources Increase the speed at which the device can recover from low power modes and start execution. Reconfiguration and non-timing critical operations can start as soon as a clock is present. main RAM/module registers can be re-initialized whilst the external (accurate) OSC clock is stabilizing Very fast Wake-Up requires an on-chip RC oscillator e.g., a 16 MHz Internal RC can provide Bus Clock in <5 cycles Allows near instant operation Periodic Wake-Up: Allows a reliable recovery in low power mode Minimizes average current Clock Source Start-up time Power consumption Accuracy 16MHz Internal RC Osc. L (<1us) M (<50uA) L (>10%) 32KHz / 128KHZ Internal RC Osc. L (<1us) L (<1uA) L (>10%) 32KHz Ext. Crystal Osc. H (ms) L (<10uA) H (<1%) 16MHz Ext. Crystal Osc. H (ms) H (>100uA) H (<1%) Optimum wake-up clock Internal PLL H (ms) H (>1mA) H (<1%) Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 17

18 Dynamic Voltage Frequency Scaling (DVFS) Devices typically do not require full performance all of the time Reducing frequency directly reduces power consumption (already discussed) But reducing frequency also allows the voltage to be reduced, further reducing power Solutions can be via hardware, software or combination of both System sophistication increases with DVFS Typically PLL allows frequency scaling Need to balance savings with complexity: Scalable regulator design, with fast switching behaviour Peripherals require full scaling capability to ensure seamless switching Synchronization handling during DVFS changes 100 ma Full Run mode Low Freq Run mode Low Vdd Run mode Low Vdd, Low Freq Run mode 5V, 120MHz 5V, 60MHz 2.5V, 120MHz 1 2.5V, 60MHz Note 1: Assumption is that maximum frequency also achievable at lowest voltage, but this will not always be the case Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink

19 Low Power Modes STANDBY lowest power mode Power supply is cut off from most devices All clocks disabled Longest wakeup time and some reconfiguration required Most pins not powered (high impedance) STOP Advanced low-power mode during which the clock to the core and the PLL are disabled Optionally switch off most peripherals State of the output pins is kept HALT disable core clock Reduced-activity mode during which the clock to the core is disabled Optionally switch off analog peripherals (PLL, flash, main regulator, etc.) RUN0-3 Software execution modes where most processing activity occurs. Allows run-time customization of different clock & power configurations of the system SW request RESET Non recoverable HW failure SYSTEM MODES SAFE DRUN TEST HW triggered transition SW triggered transition Recoverable HW failure RUN 0 RUN 1 RUN 3 USER MODES LOW POWER MODES HALT STOP STANDBY Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 19

20 General theme is to switch on as little as possible: CPU is the most power hungry module on an MCU Need to switch to OFF when possible Put more intelligence into peripherals Autonomous peripherals can help achieve this. Typical Autonomous peripherals include: API Autonomous Periodic Interrupt Autonomous Operation Allows device to recover from very low power state at selectable time intervals RTC Real Time Clock Offers time keeping functionality in very low power states DMA Direct Memory Access Allows data transfer between peripherals minimizing CPU activity ADC Analog Digital Converter Continual conversion while running in low power Triggers wake-up when signal reaches certain level LINFlex Intelligent LIN management, minimizing CPU interrupts Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 20

21 Low Power System Techniques 21

22 irc_slow Low Power System Techniques Using the silicon System solutions to achieve low power are based on several key principles: Reduce average power Sleep as much as possible Minimize RUN execution Match speed against requirements SYSTEM MODES Recoverable HW failure SW request SAFE RESET DRUN Non recoverable TEST HW failure HW triggered transition SW triggered transition USER MODES LOW POWER MODES RUN 0 HALT RUN 1 STOP RUN 3 STANDBY Only power what is needed Only switch on silicon portions Completely power gate unused portions in many power modes Only clock what is required Clock gating Clock tree management Peripheral grouping O S C 4-1 6I RM CH 1z 6 M H z div 1 to 32 div 1 to 32 F M P L L irc_fast osc a_c lck osc b_c lck osca_clk_div irc_fast_div CM U Syste m Clock Selec tor (ME) RESET SAFE INT system_clk div 1 to 15 div 1 to 15 div 1 to 15 Core Platform Peripher al Set 1 Peripher al Set 2 Peripher al Set 3 Employ intelligent autonomous operation MPC5603B Intelligent Clock Tree architecture Design autonomous peripherals e.g. DMA, RTC, API, ADC, LINFlex Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink

23 Energy Saving Potential on the System Level low high Local, internal optimization of Electronic Control Units, actuators & sensors Smart algorithms (PWM, motor control, and etc.) Loss minimation (DC/DC regulators, LEDs, and etc.) Smart activation of peripherals Effort / Risks Deactivation of complete sub-busses B C Deactivation of individual ECUs C A CGW D D A B X X Y CGW Y Network topology change Traditional wake-up mechanism Slow reaction times Limited SW changes Flexible wake-up mechanism required Slow reaction times SW and HW changes Industry standardization Savings Potential high low Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 23

24 Electronic Control Unit low power modes Vbat Very low system consumption longer wake-up time Vbat No MCU osc RAM content saved Fast wake-up time MC33905 SBC Vdd MCU MC33905 SBC Vdd MCU Osc Osc Osc Osc SBC LPM VDD OFF, no osc no cyclic wake-up MCU off I SBC = 15uA SBC LPM VDDON with osc MCU powered, STDBY mode no osc. I SBC = 40uA, I MCU = 30uA Wake up time: 2-5ms + MCU S/W start Vbat Cyclic w/u allowed longer wake-up time Vbat Faster w/u time Impact on cons. MC33905 SBC Vdd MCU MC33905 SBC Vdd MCU Osc Osc Osc Osc SBC LPM VDDOFF + osc (cyclic wake-up) MCU off I SBC = 25uA SBC LPM VDDON with osc MCU powered, HALT mode with osc. I SBC = 40uA, I MCU < 350uA Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink

25 Example: Body Controller Module Typical Scenario ms 50ms 700ms MCU Mode: STANDBY - + 8K RAM - + API/RTC (128K clock) - + Wake-up lines MCU Mode: RUN + Exec. from RAM - + IRC 16MHz - + Polling of ~24 digital + 5 analog inputs Duration: ~667ms Duration: ~200µs MCU Mode: RUN + Exec. from RAM + XTAL for IRC trimming - + IRC 16MHz - + Polling of ~24 digital + 5 analog inputs - + SPI: 500Kbps - + LIN: 3 msg at 20kbps Duration: 32ms Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 25

26 Managing Communication Wake-Ups High speed CAN I[mA] SBC wake-up SBC detects a wake up signal (3 dominant signals) Triggers a wake-up procedure. I[mA] SBC wake-up HW (fixed consumption) HW (fixed consumption) t[ms] t[ms] I[mA] Osc start MCU wake MCU Wakes up from an SBC signal. I[mA] Osc start MCU wake HW (fixed consumption) HW (fixed consumption) MCU behavior to process communication wake-up t[ms] MCU behavior to process communication wake-up t[ms] Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 26

27 Monitoring Fast Analog Signals V Scenario: Measure 3 fast analog inputs and check values (e.g., fast temperature sensors) read the state of 5 port inputs and check values Only continue full power-up if values breech predefined conditions Timing and absolute accuracy of initial measurements is not critical ADC function is active for approximately 9us (3us per conversion) in every 10ms Analog input t[s] μA Run from RAM & enable sensor 20μs 31μs 1μs 23mA 18mA Standby Current (8KRAM, 32KHIRC, API) 10μs 2ms Proposed solution: Use approach: STANDBY RUN STANDBY RUN Utilize STANDBY and retain 8K of RAM Utilize an API (Application Programming Interface) to wake-up periodically every 10ms and transition into RUN Clock the API with the on-chip 128KHz IRC (very low power Internal RC ocsillator) Use a 16MHz IRC for fast execution, accurate enough for this example application Execute limited code from RAM at 16MHz bus speed Run Current range 10ms Run from RAM & read sensor 20μs 10μs 40μs 10μs Standby Current (8KRAM, 32KHIRC, API) 7929μs Run from RAM & enable sensor 20μs 1μs 31μs 10μs Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 27

28 Monitoring Slow Analog Signals Proposed solution: Scenario: Measure 3 analog inputs and check values (for example, slow temperature sensors) Sensors are not instantly available for reading Sensor settling time: 2ms Timing and absolute accuracy of initial measurements is not critical ADC function is active for approximately 9us (3us per conversion) in every 10ms This solution is identical as previous one, except the STOP state will be used instead of STANDBY during the sensor stabilization period Use approach: STANDBY RUN STOP STANDBY RUN Return to STANDBY unless pre-defined conditions are exceeded V Analog input t[s] μA 40μA Run from RAM & enable sensor 20μs 31μs 1μs 23mA 18mA Sensor stabilization 10μs STOP Current 2ms Run Current range 10ms Run from RAM & read sensor 20μs 40μs 10μs 10μs Standby Current (8KRAM, 32KHIRC, API) 7929μs Run from RAM & enable sensor 20μs 31μs 1μs 10μs Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 28

29 AUTOSAR AUTOSAR 4.0 lacks specifications for sleeping or functionally degraded ECUs. Future AUTOSAR (AUTomotive Open System ARchitecture) enhancement: Support of partial networking (some kind of system degradation) Support of ECU degradation (implying MCU degradation) Dynamic degradation by System and ECU configuration Partial networking requirements Flexible network management (Today: only synchronized fall asleep of all ECUs of one bus) Specification for configuration of wake-up of a single ECU (avoiding wake-up of all connected ECUs) Definition of configurable wake-up patterns Transceiver enhancement Configuration of partial networks and related signals ECU degradation, a standardized approach for: De-initialization, re-initialization and re-configuration of software modules Adjustment on changed clock rates (of cores and/or other MCU blocks) which influences schedules (e.g., FlexRay). Adjustment on reduced clock accuracy which affects functions like PWM or CAN communication. Support of advanced low-power modes where some MCU blocks are still operative (e.g., PWM) while the rest of the MCU sleeps. Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 29

30 Low Power Challenges Automotive market demands for low power are increasing: More body nodes are appearing in every new generation of cars Each body node has more functionality and features More functionality demands more from the silicon: Smaller geometries to meet increasing demands Smaller technology drives the power curve Microcontroller Low Power Mechanisms Are there to make it easy Software support System Low Power Techniques: Power up fast Standby as much as possible Intelligent use of available resources Attention to power is needed from the beginning of system design Accuracy low high Cicuit/Logic Technology System Algorithm Architecture Session Summary Partitioning, Power Down, Power States Complexity, Concurrency, Regularity, Locality Parallelism, Pipelining, Redundancy, Data Encoding Logic Styles & Manipulation, Transistor Sizing, Energy recovery Threshold Reduction, Double-Threshold Devices Power Savings high low Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 30

31