FPGA Intrinsic PUFs and Their Use in IP Protection
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1 FPGA Intrinsic PUFs and Their Use in IP Protection Jorge Guajardo*,Sandeep S. Kumar*, Geert-Jan Schrijen**, and Pim Tuyls** * Philips Research Europe, Eindhoven, The Netherlands ** Business Line Intrinsic-ID, Philips Research, Eindhoven, The Netherlands September 11th, 2007
2 Contents Relevance FPGAs Intrinsic PUFs Protocols for IP Protection Conclusions September 11th,
3 Intellectual Property Theft Annual value of trade in fake goods: $400 Billion Spare parts Clothing Perfumes Medicines Audio & video Software Electronic Designs 10% of all High Tech Products sold are Counterfeit! IC designs Electronic circuitry Configuration data of programmable devices September 11th,
4 Is this relevant in the real world? September 11th,
5 Contents Relevance FPGAs Intrinsic PUFs Protocols for IP Protection Conclusions September 11th,
6 SRAM based FPGA: configuration Configuration Controller FPGA 1 EEPROM IP BLOCK Configuration IP BLOCK COPY September 11th,
7 Available Solutions Option 1 Encrypted IP configuration file External battery to store Key Option 2 Use flash based FPGA Cannot be updated in the field Option 3 Use a PUF Need two components: Randomness source Fuzzy extractor September 11th,
8 Contents Relevance FPGAs Intrinsic PUFs Protocols for IP Protection Conclusions September 11th,
9 Physical Unclonable Function PUF = Physical Unclonable Function: Derive strings from a complex physical system that is inherently unclonable Easy to evaluate (by probing the physical system) Inherently tamper resistant Manufacturer not-reproducible PUFs can be used as a source of a large amount of unclonable secret key material Unclonable Hard to make a physical clone Hard to make a mathematical model that simulates the behavior of the physical structure Practicality Requirements Easy to challenge the source Cheap and easy integrable on an IC Excellent mechanical and chemical properties September 11th,
10 Modern FPGA Floorplan Digital Signal Processing (DSP) Blocks M512 Block M4K Block MRAM Blocks I/O Channels Stratix II EP2S60 60,440 Equivalent Logic Elements 2,544,192 Memory Bits Phase- Locked Loops (PLL) September 11th,
11 Examples On chip demo Coating-PUF passivation transistors M5 M4 M3 M2 M1 IC with Coating PUF Intrinsic Identifier Challenge c-bits Response n-bits Combinatorial Circuit IC with SRAM PUF IC with Delay PUF September 11th,
12 S-RAM PUF word word bit not bit 1/2 1/2 September 11th,
13 Histogram of Inter-class and Intra-class differences September 11th,
14 Properties Randomness Noise Error Fraction E rrors in M RA M s tartup values over tem perature T= -20 o C 0.12 T= 0 o C T= 20 o C T= 40 o C T= 60 o C T= 80 o C Properties: Entropy: 95% Secrecy Rate: 76% M easurem ent Nr. Fuzzy Extractor Needed: Error Correction Randomness Extraction September 11th,
15 Contents Relevance FPGAs Intrinsic PUFs Protocols for IP Protection Conclusions September 11th,
16 How do we put everything together? Notation: TTP (Trusted Third Party), SYS (System Integrator), IPP (IP Provider), HWM (Hardware Manufacturer) Assumptions: Semantically secure encryption scheme Honest but curious model In the symmetric-key setting, possible constructions for encryption+authentication: Enc K1 (M) MAC K2 (M), MAC-then-Encrypt, Encrypt-then-MAC PUF and encryption modules assumed to be on the FPGA PUF responses are only available inside the FPGA Secure and authenticated channels SYS-TTP and TTP-IPP during enrollment and online phase September 11th,
17 Protocol for IP Protection on FPGAs Enrollment Phase HWM TTP IPP {{C1,R1}, {Cn,Rn}} Online Phase SYS TTP IPP ID SW ID HW ID SW C 1 C 2 D MAC R2 (C1 C2 D) D <- Enc R1 (SW ID SW ) Offline Phase SW September 11th,
18 PUF based Solution Intrinsic PUF Helper Data dependent on the specific FPGA chip September 11th,
19 A Bit of History 2001 Pappu et al. - Physical Random Functions (Optical PUFs) MIT Ph.D. Thesis, and Science Gassend et al., Su et al. IC PUFs (Delay PUF) CCS 2002, ACSAC Kean, Encryption for IP Protection on FPGAs, FPGA Simpson and Schaumont (Protocols for IP Protection based on the usage of PUFs) CHES Tuyls et al. (Coating PUF), CHES Guajardo et al. PK-based protocols for IP Protection based on intrinsic PUFs, FPL 2007 This work September 11th,
20 Contents Relevance FPGAs Intrinsic PUFs Protocols for IP Protection Conclusions September 11th,
21 Conclusions New PUF intrinsic to the FPGA with good statistical properties and robustness to environmental conditions. New protocol(s) for IP protection on FPGAs In the future, Other Intrinsic PUFs Complexity of fuzzy extractors Limit the use of FPGA resources. Reliability: Guaranteeing a low failure rate under all kinds of circumstances. September 11th,
22
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