FPGA Implementation and Analysis of Error Correction Codes for Physical Unclonable Functions

Transcription

1 1 FPGA Implementation and Analysis of Error Correction Codes for Physical Unclonable Functions Brian Jarvis, ECE 646, George Mason University Abstract This project explores and implements an encoding and decoding algorithm suitable for use with Physical Unclonable Functions (PUFs). This topic is of particular interest because of the growing need for trust in integrated circuits (IC). This could mean an IC generating a secret key for authentication or responding in a challenge/response scheme. The area known as Physical Unclonable Functions provides a means by which such trust may be established, however an encoding and decoding algorithm is needed to provide PUF ID fault tolerance and reduce the error rate of the system. BCH codes are selected due to their attractive error correction properties. This project implements and analyzes a BCH encoder and decoder and explores alternative implementations to reduce resource utilization. Index Terms Physical Unclonable Function, Correction Code, MicroBlaze, Concatenated code T I. INTRODUCTION BCH Error HERE is a growing need for trust at the hardware level. An increasingly popular method for addressing this need is the use of Physical Unclonable Functions (PUFs). PUFs allow a hardware component to exploit manufacturing variations or any other part-specific data in order to generate a unique signature or key for that individual part. This is analogous to biometric information such as a human fingerprint. The appeal of PUFs is that the same circuit design can be implemented on any number of hardware devices, yet due to the uniqueness of each device, each will produce a unique code. In [1] a usage of PUFs is described in which a bank customer uses a PUF device to authenticate at an ATM. The advantage brought by PUFs in this application is that an adversary would be unable to duplicate the PUF ID of the customer. A problem arises with PUFs whereby on successive PUF code generation, the outputs may not be identical. In [2] it is claimed that the error rate in PUF value regeneration can be as high as 10%. Additionally, environmental and system factors such as ambient temperature and voltage fluctuations can influence the PUF ID reproducibility, increasing the native error rate. In order to use a PUF system for establishing trust each device must be able to reliably regenerate the same code. It is for this reason that an error correcting code is often used to augment the PUF ID generation. The field of coding theory is vast and has applications which reach far beyond PUFs, which was the primary application explored during this project. For that reason, the field of candidate encoders and decoders was pared down to those which use minimal resources when implemented in an FPGA. The PUF concept of operations is that the unique function generator is run primarily at the time of FPGA power-up. For this reason, speed is not a priority as it does not need to run in real-time. What is of high priority is minimal resource utilization. This is because the PUF implementation must fit in the FPGA alongside the main application, whatever that may be. The encoding and decoding portion ideally would be just a small subset of the overall PUF circuit, thus must be implemented as efficiently as possible to reduce the resources needed. Additionally, the encoding and decoding algorithm must provide an error rate which is sufficiently low to reliably produce a unique PUF ID for a given chip. For this project, the BCH code was selected due to its attractive error correcting performance. An implementation by [3] was used as a baseline for encoding and decoding performance. This implementation was then compared to the resource utilization of a software implementation by [4] running in a MicroBlaze soft processor core. Finally, concatenated error correction codes were analyzed and compared as a way to reduce area. The FPGA family selected for implementation was the Xilinx Kintex-7. Specifically, the lowest-resource part available in the family, XC7K70T-FBG676, was used. VHDL was selected as the hardware description language for FPGA implementation. C was used in the MicroBlaze application. II. PREVIOUS WORK In [5] an encoding and decoding scheme known as Index Based Syndrome (IBS) is described. The authors claim superior resource utilization with sufficient error correction for PUF applications. This encoder and decoder was explored in a previous project. What was discovered was that while the code is indeed very small in terms of area needs, several negative attributes make it less useful for cryptographic applications. Specifically, IBS requires a specific form of PUF ID format known as a Real-Valued PUF which is not realistic to assume will always be available. Additionally, by nature of how IBS code words are formed, the code rate could become low if a large bank of PUF inputs are used; its code rate is 1 / log 2(N),

2 2 where N is the number of PUF inputs used. In [2], Maes et al. selected a BCH encoder and decoder due to its superior error correcting performance and purported low resource requirements. This code is selected for further analysis and comparison to alternative implementations in this paper. III. BACKGROUND PUF IDs can be formed from many different sources. The techniques used to generate PUFs are topics of ongoing research. An example implementation is illustrated below with a brief explanation. In Fig. 2, the shift register stages are selectively XORed with the feedback line according to a generator polynomial. This allows simple encoding by feeding the message to encode into the LFSR one bit at a time. While the input message loads the LFSR, it is also passed through to the output. Once the message to encode has been input completely the multiplexer at the output is switched to pass the contents of the LFSR stages through to the output. Once the LFSR is drained, the encoded word has been completely output. Mathematically, this process is represented by the following equations. ( ) = (1) ( ) = (2) ( ) = ( ) ( ) (3) Fig. 1: Ring-Oscillator Physical Unclonable Function Network In Fig. 1, a Ring-Oscillator PUF (ROPUF) is seen. This type of PUF is a digital circuit which has been designed to produce an oscillating logic pattern on its output bit. It can be seen that by feeding a 1 into the input bit, the output bit will oscillate due to the NAND gate output inversion feedback loop. The distance between the NAND gate output and feedback loop input dictates the frequency at which the output pattern will oscillate. This feedback distance can be made even more configurable through the introduction of multiplexers which select different paths through the circuit. Each of these ROPUFs is designed to oscillate at a prescribed frequency. In reality, when implemented in hardware the actual oscillation frequency differs slightly from what was expected. These differences are accumulated in the processing logic illustrated in the right side of the above diagram and are used to produce a unique PUF ID. The BCH code is a cyclic linear block code. It is described in detail in [6]. These codes make use of Galois Field arithmetic to correct many bit errors given sufficient parity information. BCH codes can be used to correct both binary and non-binary error patterns; the Reed-Solomon code is an example of a non-binary error correction code within the BCH family. Only binary BCH codes are considered in this project. An advantage of the BCH code is that the encoder can be implemented very efficiently using a linear feedback shift register (LFSR). An example encoder implementation is illustrated below. Fig. 2: Example BCH encoder. M denotes the message bits. C denotes the code word output. In (1), a message polynomial m(x) is formed according to the message bits. For example, the binary sequence 1101 yields an m(x) value of 1 + x + x 3. In (2), the generator polynomial for the circuit depicted in Fig. 2 is given. In ( 3), the code word polynomial c(x) is formed by multiplying the message polynomial by the generator polynomial g(x). The output of the circuit in Fig. 2 is the value c(x). The downside to using the BCH code is its decoder. The decoding process involves a complex circuit which is not areaefficient. Also the decoding stage takes significantly longer than the encoding stage. The time required is not a problem for PUF applications, however the area requirements make alternative implementations more attractive. A simple class of error correction codes known as repetition codes are explored as a concatenation option. Repetition codes operate on a message size of one bit. The code word size dictates how many times the input bit gets repeated. For example, a (5,1) repetition code takes one bit of input and outputs the bit repeated five times. To decode a repetition code, simple majority logic can be used. That is, whichever value is most prevalent in the sequence of N bits becomes the decoded value. Concatenated codes are explored as an alternative to a single error correction code. The concept of a concatenated code is that the message to be encoded is first passed through an outer encoder, denoted C 1. The code word produced by C 1 is then fed as a message to an inner encoder, denoted C 2. The output of C 2 becomes the code word of the concatenated encoder. The reverse is performed in order to decode a concatenated code word. First D 2, the decoder corresponding to the inner code, decodes the code word to an intermediate value which is then further decoded by D 1, the decoder corresponding to the outer code. This simple architecture has powerful properties. A metric used in evaluating error correction codes, the minimum distance, is multiplied when concatenating two codes. A multiplicative effect on the minimum distance becomes an exponential effect on the error correcting capability. This allows two relatively small codes to correct large amounts of errors. IV. ALGORITHM PARAMETERS The BCH algorithm is described by three parameters: code

3 3 word length, message length, and correctable errors. These parameters are denoted as N, k, and t, respectively. Code word length, N, is the length of the code following the encoding process. Message length, k, is the length of the input message to the encoder. So put another way, a message of length k is BCH encoded to produce a code word of length N. Once encoded, the BCH decoder can produce the original message of length k, even in the presence of up to t errors in the code word. For this project, BCH codes with parameters N=255, k=131, t=18 are initially considered. V. SOFTWARE MODELING In [3] Jamro presents a configurable C application which constructs a BCH encoder and decoder. The application generates synthesizable VHDL for the encoder and decoder as well as a simulation circuit to test with artificially introduced errors. A combination of C algorithms and template files are used to accomplish this. The application is configured using an input file where the code parameters are specified. This C application and associated support files were used in this project as a baseline implementation of a BCH encoder and decoder. The Jamro BCH design has some negative aspects to it. The design is reliant on the C application in order to modify the code parameters. This is less desirable than a pure HDL solution. Also the output VHDL uses some coding practices which are more error prone. Lastly, the output files are not well organized and result in files containing thousands of lines of VHDL code that could be encapsulated for better readability. As part of this project, several improvements were performed on the Jamro application. For signal types throughout the C application algorithms and template files, all BIT and BIT_VECTOR signals were replaced by STD_LOGIC and STD_LOGIC_VECTOR signals, respectively. This was done because the STD_LOGIC based signals are capable of more realistically representing signals in a digital system. The BIT types can only be values 1 or 0, whereas the STD_LOGIC types can be one of nine possible values. For example the value U can represent an uninitialized signal or the value X can help diagnose improper states or multiple drivers of a signal. Additionally, clock conditions in the Jamro design used the (clk event and clk= 1 ) style condition checking for driving clock-based processes. With signals capable of more values than just 1 and 0, this style of condition checking can possibly lead to undesirable behavior. For example, a STD_LOGIC value could theoretically transition from H to 1, which would evaluate to true in that condition check. This form of clock transition checking was replaced with rising_edge(clk). This statement only evaluates to true on the rising edge of the clock signal, which is the intended behavior. In the Jamro design s process blocks there were no process sensitivity lists. By omitting sensitivity lists, all processes were running infinitely with execution only paused due to wait until statements inside the block. This practice can lead to incorrect simulation results which are very difficult to trace. To correct this, process statements were bound with sensitivity lists instead of interior wait until statements. Lastly, as mentioned previously the Jamro application uses a combination of C algorithms and template files to generate the output VHDL files. On inspection, many of the components are copied directly from the templates into the output files without any intermediary modification. These modules were pulled aside into separate VHDL files that are used from inside the encoder and decoder. This effectively reduces the design s dependence on the C application. A separate C application originally developed by [4] was also used in this project. This application provides a standalone BCH encoder and decoder in C which was used with some slight modifications. Prior to this project, for an earlier effort, this application was modified to reduce stack usage. All arrays used in the BCH algorithms were replaced by dynamically allocated memory. An initialization routine was added to allocate these memory areas based on the desired BCH parameters and a clean-up routine added to free the allocated memory. This has the advantage of being able to use the same compiled executable with variable parameters without needing to recompile the application. VI. HARDWARE ANALYSIS Three hardware implementations were considered for this project. The Jamro BCH Encoder and Decoder were analyzed for baseline performance. A MicroBlaze implementation was also compared to determine at what BCH parameters it becomes more efficient, in terms of resource utilization, to implement the encoder and decoder in software. Lastly a concatenated code example was compared to determine if area savings can be realized by combining multiple codes. A. Jamro BCH Encoder and Decoder The Jamro BCH encoder and decoder were implemented for the Kintex 7 XC7K70T-FBG676 FPGA using the Xilinx ISE tool. The parameters used to establish baseline performance were N=255, k=131, t=18. The circuit implemented, at a high level, is illustrated below. Fig. 3: Test circuit used for Jamro BCH analysis Figure Fig. 3 illustrates how the Jamro BCH simulation circuit is designed. Test vectors generated by the C application are fed into the BCH encoder. The output of this block is now an N-bit code word. An error introduction stage corrupts the data before passing it along to the decoder. At the output of the decoder, the k bit message is compared against the original input to verify all errors have been corrected.

4 4 1) Timing The timing parameters of the BCH encoder and decoder were determined algorithmically and verified empirically by inspection of waveform output during functional simulation. The encoder circuit described previously has a latency of N clock cycles. Due to the serial nature of the design, only one bit can be processed at a time. This latency is due to the need to pass the k message bits through the LFSR (and to output the message portion of the code word), followed by N-k cycles needed to drain the LFSR. This yields a total of N clock cycles. For N=255, this results in a latency of 255 clock cycles. The decoder can be implemented in either a parallel or serial architecture. The parallel architecture uses a more complex circuit to eliminate the need for wait states incurred by the serial architecture in the interior Berlekamp-Massey algorithm used by the decoder. When implemented using the serial architecture, the decoder has a latency of N k clock cycles. For N=255, k=131, this results in a latency of 568 clock cycles. When implemented using the parallel architecture, the decoder has a latency of N k clock cycles. For N=255, k=131, this results in a latency of 442 clock cycles. 2) Area To derive resource utilization metrics, the Xilinx ISE project build parameters were set to optimize for area. The project was implemented for the same Kintex 7 part mentioned previously. The implementation results are summarized in the table below. TABLE I RESOURCE UTILIZATION OF JAMRO BCH ENCODER AND DECODER ON KINTEX 7 XC7K70T-FBG676 Architecture Serial Parallel Slice Registers Slice LUTs Occupied Slices In Table I, it is seen that the serial implementation uses many more registers than the parallel implementation, however overall uses fewer slices. This is because the serial architecture requires wait states inside the Berlekamp-Massey algorithm implementation whereas the parallel architecture does not. But in exchange, the parallel architecture has a more complex design resulting in higher area usage. Using several different sets of parameters and the parallel Jamro architecture, the resource utilization of each was captured in Table II. TABLE II RESOURCE UTILIZATION OF JAMRO BCH AT DIFFERENT PARAMETERS BCH Parameters N=511, k=241, t=36 N=255, k=131, t=18 N=127, k=64, t=10 N=15, k=5, t=3 Slice Registers Slice LUTs Occupied Slices Utilization Percentage 24 % 13 % 5 % 1 % TABLE II shows that, as would be expected, the resource utilization increases as the size of the code also increases with a roughly linear relationship. Of particular interest is that on the Kintex 7 XC7K70T-FBG676 FPGA the (511, 241, 36) code occupies 24% of available slices. B. MicroBlaze BCH Encoder and Decoder The Xilinx Platform Studio was used to design a MicroBlaze-based project in which the modified C BCH implementation from [4] could be tested. Due to resource constraints, this testing was limited to an analysis of the resources utilized by the MicroBlaze soft processor. Using the Xilinx SDK the modified BCH application was compiled for the MicroBlaze architecture. Using an available MicroBlaze compilation analysis program, it was determined that the BCH application requires bytes of instruction memory and 3568 bytes of data memory. Using these metrics and a conservative padding, a MicroBlaze processor with 16 KB instruction memory and 16 KB data memory was implemented. The table below summarizes the resource utilization of this implementation. TABLE III RESOURCE UTILIZATION OF MICROBLAZE SOFT PROCESSOR ON KINTEX 7 XC7K70T-FBG676 Slice Registers 1532 Slice LUTs 2131 Occupied Slices 855 Using the area measurements in TABLE III the MicroBlaze implementation can be compared to the Jamro hardware implementation. A break-even point is determined to be between the (127,64,10) and (255, 131, 18) Jamro BCH codes. That is, above N=127, k=64, t=10, it is more area-efficient to use a MicroBlaze software implementation of BCH error correction. C. Concatenated Repetition and BCH codes In [8] several concatenated encoder and decoder schemes are described whereby a repetition code is used as an outer code with a small inner code used to augment the coding performance. This concatenation has the effect of multiplying the two individual codes minimum distances. This exponentially increases the concatenated code s error correcting performance. Since the concatenated architecture is simply passing the output of one code to the input of another,

5 5 this exponential increase in performance is achieved with only an additive cost in terms of area. As an example of this powerful concept, the (15, 5, 3) Jamro BCH implementation with a (13,1) outer repetition code was evaluated. A repetition code is a very simple circuit, requiring just 41 slices regardless of the repetition size if implemented with sequential logic [8]. From earlier comparisons of resource utilization, the (15, 5, 3) Jamro BCH code is known to occupy 81 slices. The minimum distance of the (13, 1) code is d min=13, which means it can correct up to 6 errors. The minimum distance of the (15, 5, 3) BCH code is d min=7, which means it can correct up to 3 errors. The concatenation of these two codes produces a minimum distance of d min=91, capable of correcting up to 45 errors while occupying 122 slices. A stand-alone BCH code could require upwards of 2496 occupied slices to achieve comparable performance. VII. ANALYSIS OF RESULTS In many publications about PUF applications, the BCH code is used to correct errors in the PUF ID generation. The argument is sometimes made, for example in [2], that the BCH code is efficient in terms of area required for implementation. The results of this project show, however, that the BCH code by itself is not an efficient algorithm in terms of area. For example, if a 512 bit key is desired and is to be directly computed using the (511, 241, 36) BCH code, 24% of a Kintex 7 XC7K70T-FBG676 FPGA is occupied purely by this error correction code. From the comparison of the stand-alone hardware BCH code to one which is offloaded to a MicroBlaze soft processor, these results showed that there is a clear break-even point in the design. Occupied Slices Errors corrected HW SW Figure 4: Slices required versus errors corrected for BCH implemented in hardware versus software (MicroBlaze) The chart above illustrates the break-even point of a hardware versus software decision for the BCH encoder and decoder. If more than approximately 12 errors are to be corrected, the MicroBlaze soft processor implementation will use less area. The previous results are dwarfed by the area-efficiency of a concatenated code, however. Using the numbers produced above, extremely high error correction ability is realized with relatively small codes. For example, a BCH code capable of correcting 10 errors concatenated with a repetition code capable of correcting 6 errors is able to correct 60 errors with less area than would be required by the MicroBlaze implementation. The concatenated code approach is not without risk, though. In [7], Koeberl et al. point out that previous publications have underestimated the entropy loss in their designs. This leads to PUF-based keys which are not cryptographically sound as in many cases there is no remaining entropy in the values produced. The paper summarizes several concatenated codes which do produce keys acceptable for cryptographic applications. Notably, the only concatenated schemes listed which have a BCH code as the inner code require a very large BCH code with a relatively small repetition code. For example, a (460, 289, 41) BCH code concatenated with a (7, 1) repetition code. Notably, Koeberl et al. indicate that equivalent concatenated bit-error rates can be realized with alternative inner codes for example, the Golay code or small Reed-Muller codes. Implementation of these concatenated schemes would be viable options for future work. VIII. LESSONS LEARNED In addition to time management, this project provided valuable lessons in the evaluation of designs for minimal area. The comparison to a software implementation in a MicroBlaze soft processor is a valuable tool in the field of software/hardware co-design. In addition, this project has provided a greater understanding of error correction codes and their applications. Similarly, studying methods in which PUF IDs can be used for cryptographic key generation and authentication has provided a better realization of real-world possibilities for what was previously perceived to be primarily academic. IX. CONCLUSIONS AND FUTURE WORK In this project, the goal was to select, implement, and analyze error correction codes which used minimal area while still providing acceptable error correction capability. The desired target family of FPGAs was the Xilinx Kintex 7. The smallest part in this family of FPGAs, XC7K70T-FBG676, was selected. Through hardware implementation analysis, it was found that the BCH codes often recommended in previous publications quickly grow to an area that is unsustainable, especially at high code word sizes. An alternative was presented which implements the BCH algorithms in software running on a MicroBlaze soft processor. These results showed that at a break-even point of approximately 12 errors corrected, the MicroBlaze approach becomes the more areaefficient design. Concatenated codes were analyzed and showed great promise both in terms of area required and error correction performance. Future work in this area would include research and implementation of concatenated codes which use the Reed- Muller or Golay codes in place of BCH. The inclusion of such error correcting codes would reduce the required resource utilization while maintaining cryptographic integrity of the generated keys. Also the area of Fuzzy Extractors was

6 6 explored, but was not used heavily in this project. That area combined with the performance of concatenated codes is a very promising area of further research. REFERENCES [1] K. Frikken, M. Blanton, and M. Atallah, "Robust Authentication Using Physically Unclonable Functions," Information Security Conference, September September , pp [2] R. Maes, A. Van Herrewege, and I. Verbauwhede, "PUFKY: A Fully Functional PUF-based Cryptographic Key Generator," Proc. CHES 2012, LNCS 7428, pp [3] E. Jamro. The Design of a VHDL Based Synthesis Tool for BCH Codecs, Master of Philosophy Thesis, University of Huddersfield, Huddersfield, England, Internet: [4] R. Morelos-Zaragoza. Encoder/decoder for binary BCH codes in C (Version 3.1), Internet: June 13, 1997 [Sep. 14, 2014]. [5] M. Yu, S. Devadas, "Secure and Robust Error Correction for Physical Unclonable Functions," IEEE Design & Test of Computers, vol.27, no.1, Jan. -Feb. 2010, pp [6] S. Lin and D. Costello, Error Control Coding, 2nd. ed., Prentice Hall, 2004 [7] P. Koeberl, J. Li, A. Rajan and W. Wu. "Entropy Loss in PUF-based Key Generation Schemes: The Repetition Code Pitfall," Proc IEEE International Symposium on Hardware-Oriented Security and Trust, pp Ph.D. Thesis, KU Leuven, Belgium, Aug Available: pdf [8] C. Bösch, J. Guajardo, A-R. Sadeghi, J. Shokrollahi, and P. Tuyls. Efficient Helper Data Key Extractor on FPGAs, CHES 2008, pp