MSE 5010 HARDWARE DESCRIPTION. M5010/EN FT/A11 Version A

Transcription

1 M5010/EN FT/A11 Version A

2 TECHNICAL DOCUMENTATION M5010/EN FT/A11 Chapter No (if applicable) MSE 5010 Page 2/103 MSE 5010 Original signed by Date Name Visa Established 02/12/02/2004 Monique Wils Checked 02/12/02/2004 Gwenaelle Secretan Approved 02/12/02/2004 Vianney Vannson

3 VOLUME X (Volume Title) Page 3/103 CONTENTS 1. EQUIPMENT ARCHITECTURE Board slots 8 2. BOARDS Classified Board Description Board Appearance SL SLQ4/SLD4/SL SLQ1/SL SEP1/EU04/EU08/OU08/TSB8/ TSB SPQ4/MU PD3/PL3/D34S/C34S PQ1/PQM/PD1/D75S/D12S/D12B EGS EFS4/EFS0/ETF CXL1/CXL4/CXL EOW AUX PIU Erreur! Signet non défini FAN CABLES Ω E1 Cable Ω E1/T1 Cable E3/DS3 Cable Power Cable PGND Cable Ω Clock Cable Ω Clock Cable Network Cable Boolean Input/Output Cable OAM Serial Port Cable 95

4 VOLUME X (Volume Title) Page 4/ S1 ~ S4/F&f Cable Fiber INDICATOR DESCRIPTION FOR EQUIPMENT AND BOARD Board Indicator Description POWER CONSUMPTION AND WEIGHT ACRONYMS AND ABBREVIATIONS 102

5 VOLUME X (Volume Title) Page 5/103 PAGE BLANCHE ("Blank Page")

6 VOLUME X (Volume Title) Page 6/103 MODIFICATIONS PAGE Version DATE COMMENTS A 03/02/2004 ORIGINAL ISSUE

7 VOLUME X (Volume Title) Page 7/103

8 VOLUME X (Volume Title) Page 8/ EQUIPMENT ARCHITECTURE The MSE 5010 is composed of power supply unit, fan unit, boards and cables, as shown in Fig 1-1. Fig 1-1 MSE Board slots The slot assignment of the MSE 5010 subrack is shown in Fig 1-2 slot14 slot15 slot18 (PIU) slot16 slot17 slot19 (PIU) slot1 slot11 slot6 slot20 (FAN) slot2 slot3 slot4 slot12 slot13 slot7 slot8 slot9 slot5 slot10 (AUX) Fig 1-2 Slot assignment of the MSE 5010 Boards and their corresponding slots of the MSE 5010 are shown in Table 1-1. Board Full name Slot available SL16 STM-16 optical interface board slot 11~13 SLQ4 4 STM-4 optical interface board slot 11~13 SLD4 2 STM-4 optical interface board slot 11~13 SL4 STM-4 optical interface board slot 11~13 SLQ1 4 STM-1 optical interface board slot 11~13 SL1 STM-1 optical interface board slot 11~13

9 VOLUME X (Volume Title) Page 9/103 Board Full name Slot available SEP1 STM-1 electrical processing board slot 11~13 SPQ4 E4/STM-1 electrical interface board slot 12, 13 PL3 3 E3/DS3 processing board slot 12, 13 PD3 6 E3/DS3 processing board slot 12, 13 PQ1 63 E1 processing board slot 11~13 PQM 63 E1/T1 processing board slot 11~13 PD1 32 E1 processing board slot 1, 2, 3, 11, 12, 13, 6, 7, 8 EGS2 EFS0 EFS4 CXL16 CXL4 CXL1 2-Port Gigabit Ethernet optical interface board with Lanswitch Fast Ethernet Interface Board with Lanswitch 4-Port Fast Ethernet processing board with Lanswitch STM-16 system control, cross-connect, optical interface board STM-4 system control, cross-connect, optical interface board STM-1 system control, cross-connect, optical interface board slot 11~13 slot 12~13 slot 11~13 slot 4, 5 slot 4, 5 slot 4, 5 AUX System auxiliary process board slot 10 EOW Engineering Order Wire slot 9 Table 1-1 Processing boards and their corresponding slots

10 VOLUME X (Volume Title) Page 10/ BOARDS 2.1 Classified Board Description In terms of functions, boards can be classified into the following types: SDH interface unit PDH interface unit Ethernet interface unit System control, cross-connect, optical interface board Engineering Order Wire Auxiliary interface unit Power unit Fan unit Other functional unit Table 2-1 shows the corresponding relationship between the functional units and boards. Unit name Board Full name SL16 STM-16 optical interface board SDH interface unit PDH interface unit SLQ4 SLD4 SL4 SLQ1 SL1 SEP1 EU04 EU08 OU08 SPQ4 MU04 PD3 PL3 C34S D34S PQM PQ1 PD1 4 STM-4 optical interface board 2 STM-4 optical interface board STM-4 optical interface board 4 STM-1 optical interface board STM-1 optical interface board 8 STM-1 line processing board 4 STM-1 electrical interface board 8 STM-1 electrical interface board 8 STM-1 optical interface board 4 E4/STM-1 processing board 4 x E4/STM-1 interface board 6 E3/DS3 processing board 3 E3/DS3 processing board 3 E3/DS3 PDH interface switching board 6 E3/DS3 PDH interface switching board 63 E1/T1 processing board 63 E1 processing board 32 E1 processing board

11 VOLUME X (Volume Title) Page 11/103 Unit name Board Full name D75S 32 75Ω E1/T1 PDH interface switching board Ethernet interface unit System control, cross-connect, optical interface board Engineering Order Wire System auxiliary interface unit D12S D12B TSB4 TSB8 EGS2 EFS4 EFS0 ETF8 CXL16 CXL4 CXL1 EOW AUX Ω E1/T1 PDH interface switching board 32 75Ω/120Ω E1/T1 PDH interface board 4 PDH interface switching & bridging board 8 PDH interface switching & bridging board 2-port Gigabit Ethernet optical interface board with Lanswitch 4-port Fast Ethernet processing board with Lanswitch Fast Ethernet processing board with Lanswitch 8 x 10/100M Ethernet twisted pair interface board STM-16 system control, cross-connect, optical interface board STM-4 system control, cross-connect, optical interface board STM-1 system control, cross-connect, optical interface board Engineering Order Wire System auxiliary interface board Power unit PIU Power interface unit Fan unit FAN Fan control unit Table 2-1 Corresponding relationship between functional units and boards

12 VOLUME X (Volume Title) Page 12/ Board Appearance The appearances of some MSE 5010 boards are shown in Fig Board name 2.Ejector lever 3. Indicator 4. Front panel 5. PCB Fig 2-1 The boards appearance Caution: Always wear an ESD wrist strap when holding the board, and make sure the ESD wrist strap is well grounded, thus to prevent the static electricity from damaging the board. Warning: It is strictly forbidden to stare into the optical interface board and the optical interface, lest the laser beam inside the optical fiber would hurt your eyes.

13 VOLUME X (Volume Title) Page 13/ SL16 SL16 is the STM-16 optical interface board, responsible for STM-16 optical signal processing. SL16 can be seated in Slot 11~ Functions and Principles Functions Receive/transmit one channel of STM-16 optical signal. Support VC-4-4c, VC-4-8c, and VC-4-16c concatenated services. Support I-16, S-16.1, L-16.1, L-16.2 and L-16.2Je optical modules for different transmission distances. Support fixed wavelength output, so that it can be connected with the multiplex unit of WDM equipment directly without using the wavelength conversion unit. Support various protection schemes such as two-fiber and four-fiber bidirectional MSP ring, linear MSP and SNCP. Support shared optical path protection of MSP ring and SNCP ring, and that of two MSP rings. Provide abundant alarm and performance events for convenient equipment management and maintenance. Support inloop and outloop at optical interfaces for fast fault location. Support ALS function, avoiding laser injury to human body during maintenance. Support on-line query of the board information and the optical power. Support configuration of such bytes as D1-D3, D4 -D12 (DCC), E1 and E2 (ECC) to transparent transmission or into other unused overhead bytes. Support smooth software upgrade and expansion.

14 VOLUME X (Volume Title) Page 14/ Principles Fig 2-2 shows the functional diagram of SL16. 1 x STM-16 optical signal Interface unit Data and clock recovery unit SDH signal processing unit Active crossconnect board Standby crossconnect board Timing unit Overhead processing unit Control and communication unit Clock signal Overhead bus SCC Cross-connect and timing unit Power module -48V Fig 2-2 Functional diagram of SL16 The STM-16 optical signal is accessed at the interface unit and sent to the SDH signal processing unit after data and clock signal extraction at data and clock recovery unit. The SDH signal processing unit implements frame search, SOH termination and insertion, overhead byte extraction, pointer justification and POH monitoring to the incoming signals and then sends them to overhead processing unit for further processing. After that, the signals are re-timed with the system clock, and then multiplexed into 622M data signals after cross-connect and finally sent to the cross-connect and timing unit. The timing unit extracts the clock signal at line side and receives system clock and frame header from the active and standby cross-connect boards. It also provides clock signal for other modules on the board. The control and communication unit mainly functions control, communication and service configuration of the board. The power module provides all modules of the board with DC power supply with required voltage. The overhead processing unit extracts the overhead bytes from the one channel of overhead signal it receives, and sends the extracted bytes to SCC and its paired board through the overhead bus according to related sequence and clock requirements. In transmit direction, the overhead processing unit re-arranges the received overhead signals from SCC or its paired board and then inserts them into the SOH.

15 VOLUME X (Volume Title) Page 15/ Front Panel The front panel of SL16 is shown in Fig 2-3. Fig 2-3 The front panel of SL16 The indicator of SL16 is shown in Table 2-2 Indicator Board hardware indicator-stat Color and status On, green On, red On for 100ms and off for 100ms alternatively, red Off Description The board works normally. The board hardware fails. The board hardware is mismatched. The board is not powered on, or the service is not configured. Service On, green The service is activated. activation indicator-act Off The service is not activated. Board software indicator- PROG On, green On for 100ms and off for 100ms alternatively, green Upload of board software to FLASH or the FPGA upload is normal, or the board software initialization is normal. Board software is being uploaded to FLASH or FGPA The board software is initializing, and is in BIOS boot stage. Board software indicator- PROG On, red Off The board software in FLASH or the FPGA configuration is lost, resulting in upload and initialization failure. No power supply.

16 VOLUME X (Volume Title) Page 16/103 Indicator Service alarm indicator-srv Color and status On, green On, red On, yellow Off Description Service is normal, no service alarm occurs. Critical or major alarm occurs to service. Minor or remote alarm occurs to service. No service configured or no power supply. Table 2-2 The indicator description of SL Interface The optical interface of SL16 is LC Board Configuration Before using SL16 for running service, parameters should be set for it through NM. Configuration should be provided to the following bytes for the line board: J1 J1 is the path trace byte. Successive transmission of the higher order access point identifier through J1 at the transmit end helps the receive end learn that its connection with the specified transmit end is in continuous connection status. When J1 mismatch is detected at receive end, the corresponding VC-4 path will generate HP- TIM alarm. C2 C2 is the signal label byte, indicating the multiplexing structure of VC-4 frame and the payload property. It is required that the C2 bytes transmitted matches those received. Once mismatch is detected, the corresponding VC- 4 path will generate HP-SLM alarm and insert all 1 s into the C4 in downstream stations Technical Parameters Parameter Rate Processing capability Line code pattern Connector Description SL kbit/s Process 1 STM-16 standard service or concatenated service NRZ LC Size (mm) Weight (kg) Power consumption (W) 20 Optical module type I-16 S-16.1 L-16.1 L-16.2 L- 16.2Je V- 16.2Je U- 16.2Je Wavelength (nm)

17 VOLUME X (Volume Title) Page 17/103 Parameter Description SL16 Transmission distance (km) 0~2 2~15 15~40 40~80 80~ ~ ~1 70 Launched power (dbm) -10 ~ ~ 0-2 ~ 3-2 ~ 3 5 ~ 7 NA NA Receiver sensitivity (dbm) SLQ4/SLD4/SL4 SLQ4 is the 4 STM-4 optical interface board; SLD4 is the 2 STM-4 optical interface board; SL4 is the 1 STM- 4 optical interface board. All are responsible for STM-4 optical signal processing. Table 2-3 shows the difference between these three optical interface boards. Comparison SL4 SLD4 SLQ4 Processing capability 1 STM-4 2 STM-4 4 STM-4 Slot available Slot 11 ~ 13 Slot 11 ~13 Slot 11 ~ 13 Table 2-3 Comparison between SLQ4, SLD4 and SL Functions and Principles Functions SLQ4, SLD4 and SL4 can access and process 4, 2 and 1 STM-4 optical signal respectively. Support VC-4-4c concatenated services. Support I-4, S-4.1, L-4.1, L-4.2 and Ve-4.2 optical interfaces for different transmission distances. Support various protection schemes such as two-fiber and four-fiber bidirectional MSP, linear MSP, and SNCP. Provide abundant alarm and performance events for convenient equipment management and maintenance. Support inloop and outloop at optical interfaces for fast fault location. Support ALS function, avoiding laser injury to human body during maintenance. Support on-line query of the board information. Support configuration of such bytes as D1-D3, D4-D12 (DCC), E1 and E2 (ECC) to transparent transmission or into other unused overhead bytes. Support smooth software upgrade and expansion.

18 VOLUME X (Volume Title) Page 18/ Principles Fig 2-4 shows the functional diagram of SLQ4/SLD4/SL4. 4/2/1 x STM-4 optical signal Interface unit Data and clock recovery unit SDH signal processing unit Active crossconnect board Standby crossconnect board Timing unit Overhead processing unit Control and communication unit Clock signal Overhead bus SCC Cross-connect and timing unit Power module -48V Fig 2-4 Functional diagram of SLQ4/SLD4/SL4 The 4/2/1 STM-4 optical signals are accessed at the interface unit and sent to the SDH signal processing unit after data and clock signal extraction at data and clock recovery unit. The SDH signal processing unit implements frame search, SOH termination and insertion, overhead byte extraction, pointer justification and POH monitoring to the incoming signals and then sends them to overhead processing unit for further processing. After that, the signals are re-timed with the system clock, and then multiplexed into 622M data signals after cross-connect and finally sent to the cross-connect and timing unit. The timing unit extracts the clock signal at line side and receives system clock and frame header from the active and standby cross-connect boards. It also provides clock signal for other modules on the board. The control and communication unit mainly functions control, communication and service configuration of the board. The power module provides all modules of the board with DC power supply with required voltage. The overhead processing unit extracts the overhead bytes from the two channels of overhead signals it receives, and sends the extracted bytes to SCC and its paired board through the overhead bus according to related sequence and clock requirements. In transmit direction, the overhead processing unit re-arranges the received overhead signals from SCC or its paired board and then inserts them into the SOH.

19 VOLUME X (Volume Title) Page 19/ Front Panel The front panel of SLQ4, SLD4 and SL4 is shown in Fig 2-5, and the indicator description is shown in Table 2-4 Fig 2-5 Front panel of SLQ4, SLD4 and SL4

20 VOLUME X (Volume Title) Page 20/103 Indicator Color and status Description On, green The board works normally. Board hardware indicator- STAT On, red On for 100ms and off for 100ms alternatively, red Off The board hardware fails. The board hardware is mismatched. The board is not powered on. Service activation indicator- ACT On, green Off The service is activated, and the board is in operation. The service is not activated, and the board can be swapped. Board software indicator- PROG On, green On for 100ms and off for 100ms alternatively, green On for 300ms and off for 300ms alternatively, green On, red Off Upload of board software to FLASH or the FPGA upload is normal, or the board software initialization is normal. Board software is being uploaded to FLASH or FGPA The board software is initializing, and is in BIOS boot stage. The board software in FLASH or the FPGA configuration is lost, resulting in upload and initialization failure. No power supply. Service alarm indicator- SRV On, green On, red On, yellow Off Service is normal, no service alarm occurs. Critical or major alarm occurs to service. Minor or remote alarm occurs to service. No service is configured. Table 2-4 description of SLQ4, SLD4 and SL4

21 VOLUME X (Volume Title) Page 21/ Interface SLQ4, SLD4 and SL4 provide LC optical interfaces Board Configuration Before using SLQ4, SLD4 and SL4 for running service, parameters should be set for it through NM. Configuration should be provided to the following bytes for the line board: J1 J1 is the path trace byte. Successive transmission of the higher order access point identifier through J1 at the transmit end helps the receive end learn that its connection with the specified transmit end is in continuous connection status. When J1 mismatch is detected at receive end, the corresponding VC-4 path will generate HP- TIM alarm. C2 C2 is the signal label byte, indicating the multiplexing structure of VC-4 frame and the payload property. It is required that the C2 bytes transmitted matches those received. Once mismatch is detected, the corresponding VC- 4 path will generate HP-SLM alarm and insert all 1 s into the C4 in downstream stations Technical Parameters Parameter Rate Processing capability Line code pattern Connector Description SLQ4 SLD4 SL kbit/s 4 STM-4 2 STM-4 1 STM-4 NRZ LC Size (mm) Weight (kg) Power consumption (W) Optical module type Wavelength (nm) Transmission distance (km) Launched power (dbm) Received sensitivity (dbm) I-4 S-4.1 L-4.1 L-4.2 Ve ~15 2~15 15~40 40~80 80~ ~ ~ -8-3 ~ 2-3 ~ 2-3 ~

22 VOLUME X (Volume Title) Page 22/ SLQ1/SL1 SLQ1 is the 4 STM-1 optical interface board; SL1 is the 1 STM-1 optical interface board. Both are responsible for STM-1 optical signal processing Table 2-5 shows the difference between these two optical interface boards. Comparison SL1 SLQ1 Processing capability 1 STM-1 4 STM-1 Slot available Slot 11 ~ 13 Slot 11 ~ 13 Table 2-5 Comparison between SLQ1 and SL Functions and Principles Functions SLQ1 and SL1 access and process four and one channel of STM-1 optical signal respectively. Support Ie-1, I-1, S-1.1, L-1.1, L-1.2 and V-1.2 optical interfaces for different transmission distances. Support various protection schemes such as two-fiber unidirectional MSP, linear MSP and SNCP. Provide abundant alarm and performance events for convenient equipment management and maintenance. Support inloop and outloop at optical interfaces for fast fault location. Support ALS function, avoiding laser injury to human body during maintenance. Support on-line query of the board information. Support configuration of such bytes as D1-D3, D4-D12 (DCC), E1 and E2 (ECC) to transparent transmission or into other unused overhead bytes. Support smooth software upgrade and expansion.

23 VOLUME X (Volume Title) Page 23/ Principles Fig 2-6 shows the functional diagram of SLQ1/SL1. 4/1 x STM-1 optical signal Interface unit Data and clock recovery unit SDH signal processing unit Active crossconnect board Standby crossconnect board Timing unit Overhead processing unit Control and communication unit Clock signal Overhead bus SCC Cross-connect and timing unit Power module -48V Fig 2-6 Functional diagram of SLQ1/SL1 The 4/1 STM-1 optical signals are accessed at the interface unit and sent to the SDH signal processing unit after data and clock signal extraction at data and clock recovery unit. The SDH signal processing unit implements frame search, SOH termination and insertion, overhead byte extraction, pointer justification and POH monitoring to the incoming signals and then sends them to overhead processing unit for further processing. After that, the signals are re-timed with the system clock, and then multiplexed into 622M data signals after cross-connect and finally sent to the cross-connect and timing unit. The timing unit extracts the clock signal at line side and receives system clock and frame header from the active and standby cross-connect boards. It also provides clock signal for other modules on the board. The control and communication unit mainly functions control, communication and service configuration of the board. The power module provides all modules of the board with DC power supply with required voltage. The overhead processing unit extracts the overhead bytes from the two channels of overhead signals it receives, and sends the extracted bytes to SCC and its paired board through the overhead bus according to related sequence and clock requirements. In transmit direction, the overhead processing unit re-arranges the received overhead signals from SCC or its paired board and then inserts them into the SOH.

24 VOLUME X (Volume Title) Page 24/ Front Panel The front panel of SLQ1 and SL1 is shown in Fig 2-7, and the indicator description is shown in Table 2-6 Fig 2-7 Front panel of SLQ1 and SL1

25 VOLUME X (Volume Title) Page 25/103 Indicator Color and status Description On, green The board works normally. Board hardware indicator- STAT On, red On for 100ms and off for 100ms alternatively, red Off The board hardware fails. The board hardware is mismatched. The board is not powered on. Service activation indicator- ACT On, green Off The service is activated, and the board is in operation. The service is not activated, and the board can be swapped. Board software indicator- PROG On, green On for 100ms and off for 100ms alternatively, green On for 300ms and off for 300ms alternatively, green On, red Off Upload of board software to FLASH or the FPGA upload is normal, or the board software initialization is normal. Board software is being uploaded to FLASH or FGPA The board software is initializing, and is in BIOS boot stage. The board software in FLASH or the FPGA configuration is lost, resulting in upload and initialization failure. No power supply. Service alarm indicator- SRV On, green On, red On, yellow Off Service is normal, no service alarm occurs. Critical or major alarm occurs to service. Minor or remote alarm occurs to service. No service is configured. Table 2-6 Indicator description of SLQ1 and SL1

26 VOLUME X (Volume Title) Page 26/ Interface The interface of SLQ1 and SL1 is LC Board Configuration using SLQ1 and SL1 for running service, parameters should be set for it through NM. Configuration should be provided to the following bytes for the line board: J1 J1 is the path trace byte. Successive transmission of the higher order access point identifier through J1 at the transmit end helps the receive end learn that its connection with the specified transmit end is in continuous connection status. When J1 mismatch is detected at receive end, the corresponding VC-4 path will generate HP- TIM alarm. C2 C2 is the signal label byte, indicating the multiplexing structure of VC-4 frame and the payload property. It is required that the C2 bytes transmitted matches those received. Once mismatch is detected, the corresponding VC- 4 path will generate HP-SLM alarm and insert all 1 s into the C4 in downstream stations Technical Parameters Parameter Rate SLQ kbit/s Description SL1 Processing capability Line code pattern Connector 4 STM-1 1 STM-1 NRZ LC Size (mm) Weight (kg) Power consumption (W) Optical module type Wavelength (nm) Transmission distance (km) Launched power (dbm) Received sensitivity (dbm) I-1 S-1.1 L-1.1 L-1.2 Ve ~15 2~15 15~40 40~80 80~ ~ ~ -8-5 ~ 0-5 ~ 0-3 ~

27 VOLUME X (Volume Title) Page 27/ SEP1/EU04/EU08/OU08/TSB8/ TSB4 SEP1 is the 8 STM-1 line processing board, with two STM-1 electrical interfaces on the front panel. EU08 is the 8 STM-1 electrical interface board; EU04 is the 4 STM-1 electrical interface board; OU08 is the 8 STM-1 optical interface board; TSB8 is the 8 PDH interface switching & bridging board; and TSB4 is the 4 PDH interface switching & bridging board. Table 2-7 shows the differences between SEP1, EU04, EU08, OU08, TSB8 and TSB4. Board Boards equipped Function None Accessing and processing 2 x STM-1 electrical signal SEP1 EU08 EU04 OU08 Accessing and processing 8 x STM-1 electrical signal Accessing and processing 4 x STM-1 electrical signal Accessing and processing 8 x STM-1 optical signal EU08 and TSB8 Accessing and processing 8 x STM-1 electrical signal, realizing the 1:1 EPS to SEP1 board. EU04 and TSB4 Accessing and processing 4 x STM-1 electrical signal, realizing the 1:1 EPS to SEP1 board. Table 2-7 Comparison between SEP1, EU04, EU08, OU08, TSB8 and TSB Functions and Principles Functions SEP1 can process 8 STM-1 services. Support various protection schemes such as linear MSP, MSP and SNCP. Provide abundant alarm and performance events for convenient equipment management and maintenance. Support inloop and outloop at optical interfaces for fast fault location. Support ALS function, avoiding laser injury to human body during maintenance. Support on-line query of the board information. Support configuration of such bytes as D1-D3, D4 D12, (DCC),, E1 and E2 (ECC) to transparent transmission or into other unused overhead bytes. Support smooth software upgrade and expansion Principles The functional diagram of SEP1 and TSB8 is shown in Fig 2-8 and Fig 2-9 respectively.

28 VOLUME X (Volume Title) Page 28/103 2/4/8 x STM-1 optical/electrical signals Interface unit Data and clock recovery unit SDH signal processing unit Active crossconnect board Standby crossconnect board Timing unit Overhead processing unit Control and communication unit Overhead bus SCC Clock signal Cross-connect and timing unit Power module -48V Fig 2-8 Functional diagram of SEP1 TSB8 Signal selector Working SEP1 Protection SEP1 Allocation drive 8 ÁSTM-1 Electrical signal Fig 2-9 Functional diagram of TSB8 The interface unit of SEP1 is EU04, EU08 and OU08, which accesses STM-1 signals and sends them to SDH signal processing unit after data and clock signal extracting at data and clock recovery unit. The SDH signal processing unit implements frame search, SOH termination and insertion, overhead byte extraction, pointer justification and POH monitoring to the incoming signals and then sends them to overhead processing unit for further processing. After that, the signals are re-timed with the system clock, and then multiplexed into 622M data signals after cross-connect and finally sent to the cross-connect and timing unit. The timing unit extracts the clock signal at line side and receives system clock and frame header from the active and standby cross-connect boards. It also provides clock signal for other modules on the board. The control and communication unit mainly functions control, communication and service configuration of the board. The power module provides all modules of the board with DC power supply with required voltage. The overhead processing unit extracts the overhead bytes from the two channels of overhead signals it receives, and sends the extracted bytes to SCC and its paired board through the overhead bus according to related sequence and clock requirements. In transmit direction, the overhead processing unit re-arranges the received overhead signals from SCC or its paired board and then inserts them into the SOH. TSB8 enables EPS of SEP1. The signal selector of the TSB8 selects one out of the three groups of received signals from the working SEP1 and sends them to the protection SEP1. The allocation drive allocates the signals from the protection SEP1 to the working SEP1.

29 VOLUME X (Volume Title) Page 29/ Front Panel The front panel of SEP1, EU04, EU08, OU08, TSB8 and TSB4 is shown in Fig 2-10, and the indicator description is shown in tabe 2-8. Fig 2-10 The front panel of SEP1, EU04, EU08, OU08, TSB8 and TSB4 Indicator Color and status Description On, green The board works normally. Board hardware indicator-stat On, red On for 100ms and off for 100ms alternatively, red Off The board hardware fails. The board hardware is mismatched. The board is not powered on, or the service is not configured. Service activation indicator-act On, green Off The service is activated. (In EPS protection mode, the board is in working status.) The service is not activated. (In EPS protection mode, the board is in protection status.) Board software indicator-prog On, green On for 100ms and off for 100ms alternatively, green On for 300ms and off for 300ms alternatively, green On, red Off Upload of board software to FLASH or the FPGA upload is normal, or the board software initialization is normal. Board software is being uploaded to FLASH or FGPA The board software is initializing, and is in BIOS boot stage. The board software in FLASH or the FPGA configuration is lost, resulting in upload and initialization failure. No power supply. Service alarm On, green Service is normal, no service alarm occurs.

30 VOLUME X (Volume Title) Page 30/103 indicator-srv On, red On, yellow Off Critical or major alarm occurs to service. Minor or remote alarm occurs to service. No service configured or no power supply. Table 2-9 Indicator description of SEP Interface There are two pairs of 75Ω SMB interface on the panel of SEP1. The board can access 2 x STM electrical signals when it is used independently. SEP1 board can also cooperate with EU08, EU04 or OU08 to realize different functions. Table 2-10 shows the comparison between EU08, EU04 and OU08. Board EU08 EU04 OU08 Item Interface Number Access Capability 8 STM-1 electrical signal 4 STM-1 electrical signal 8 STM-1 optical signal Interface Type 8 pairs of SMB electrical interface 4 pairs of SMB electrical interface 8 pairs of SC or LC optical interface Table 2-10 Comparison between EU08, EU04 and OU08

31 VOLUME X (Volume Title) Page 31/103 TSB8 and TSB4 enable EPS of SEP1. The specific protection principle is shown in Fig SLOT 14 TSB8 SLOT16 EU04 Signal of Switch Control System Control Unit Protection SEP1 SLOT12 Working SEP1 Failure SLOT13 SLOT 4/5 8 STM-1(E4) Service Fig 2-11 EPS of SEP1 When a working SEP1 failure is detected, the cross-connect and timing unit will ask EU04 to transfer the signal to TSB8, and thus to bridging the signals of EU04 and protection SEP1. Note: EPS is a scheme at device level. When the working board fails, the accessed signal will be protected by being bridged to the protection board. By this way, triggering of more complex protection at network level such as MSP and SNCP can be avoided, improving the equipment reliability.

32 VOLUME X (Volume Title) Page 32/ Board Configuration Before using SEP1 for running service, parameters should be set for it through NM. Configuration should be provided to the following bytes for the line board: J1 J1 is the path trace byte. Successive transmission of the higher order access point identifier through J1 at the transmit end helps the receive end learn that its connection with the specified transmit end is in continuous connection status. When J1 mismatch is detected at receive end, the corresponding VC-4 path will generate HP- TIM alarm. C2 C2 is the signal label byte, indicating the multiplexing structure of VC-4 frame and the payload property. It is required that the C2 bytes transmitted matches those received. Once mismatch is detected, the corresponding VC- 4 path will generate HP-SLM alarm and insert all 1 s into the C4 in downstream stations Technical Parameters Parameter Rate Description SEP1 EU08 EU04 OU08 TSB8 TSB kbit/s Access capability 2 STM-1 electrica l signals 8 STM-1 electrica l signals 4 STM-1 electrica l signals 8 STM- 1 optical signals None None Processing capability 8 STM-1 None None None EPS EPS Line code pattern CMI or NRZ Connector SMB SMB SMB LC, SC None None Size (mm) Weight (kg) Power consumption (W) Optical module type Wavelength (nm) Transmission distance (km) Launched power (dbm) Receiver sensitivity (dbm) None 1-1 S-1.1 None None 1310 None None 0~15 None None -15 ~ -8 None None -38 None

33 VOLUME X (Volume Title) Page 33/ SPQ4/MU04 SPQ4 is the 4 E4/STM-1 processing board; and MU04 is the 4 x E4/STM-1 interface board. SPQ4 can work with MU04 to access and process 4 E4/STM-1 electrical signals; and SPQ4 and MU04 can work with TSB4 to provide 1:1 EPS to SPQ4. SPQ4 can be seated in Slot 12 ~ 13, MU04 in Slot 14, 16, and TSB4 in Slot 14, Functions and Principles Functions Access and process 4 E4/STM-1 electrical signals. All paths can be set for either E4 or STM-1 service as desired. MU04 provides 75Ω SMB unbalanced interface. The STM-1 service supports such protection schemes as MSP and SNCP, while the E4 service supports path protection (PP). Support SOH byte processing, including B1, B2, K1, K2, M1, F1 and D1-D3, D4-D12 (DCC). Support POH byte processing, including J1, B3, C2, G1 and H4. Provide abundant alarm and performance events for convenient equipment management and maintenance. Support inloop and outloop at electrical interfaces for fast fault location. Support on-line query of the board information. Support configuration of such bytes as D1-D3, D4-D123 (DCC), E1 and E2 (ECC) to transparent transmission or into other unused overhead bytes. Support smooth software upgrade and expansion Principles Fig 2-12 shows the functional diagram of SPQ4. 4 x E4/STM-1 electrical signals... Interface unit Data and clock recovery unit Mapping/ demapping unit Overhead processing unit Bus conversion unit Active crossconnect board Standby crossconnect board Control and communication unit Other boards Power module -48V Fig 2-12 Functional diagram of SPQ4

34 VOLUME X (Volume Title) Page 34/103 The interface unit for SPQ4 is MU04, at which the 4 E4/STM-1 electrical signals are accessed. Then the data signals extracted by the data and clock recovery unit are sent to the mapping/demapping unit and overhead processing unit for signal processing, SOH byte termination and insertion, and overhead data extraction. The control and communication unit communicates with the SCC and others boards through the Ethernet port to collect and report alarm and performance events, and interpret and process the configuration command sent by NM. The power module provides all modules on the board with required DC power supply and monitors the power supply status. TSB4 enables EPS of SPQ4. The signal selector of the TSB4 selects one out of received signals from working SPQ4 and sends them to the protection SEP1. The allocation drive allocates the signals from the protection SPQ4 to working SPQ4.

35 VOLUME X (Volume Title) Page 35/ Front Panel The front panel of SPQ4 and MU04 is shown in 0, and the indicator description of SPQ4 is shown in Fig 2-13 Fig 2-13 The front panel of SPQ4 and MU04 Table 2-10 Indicator description of SPQ4 Indicator Color and status Description On, green The board works normally. Board hardware indicator-stat On, red On for 100ms and off for 100ms alternatively, red Off The board hardware fails. The board hardware is mismatched. The board is not powered on, or the service is not configured. Service activation On, green The service is activated. (In EPS protection mode, the board is in working status.) indicator-act Off The service is not activated. (In EPS protection mode, the board is in protection status.) Board software indicator- PROG Service alarm indicator-srv On, green On for 100ms and off for 100ms alternatively, green On for 300ms and off for 300ms alternatively, green On, red Off On, green Upload of board software to FLASH or the FPGA upload is normal, or the board software initialization is normal. Board software is being uploaded to FLASH or FGPA The board software is initializing, and is in BIOS boot stage. The board software in FLASH or the FPGA configuration is lost, resulting in upload and initialization failure. No power supply. Service is normal, no service alarm occurs.

36 VOLUME X (Volume Title) Page 36/103 On, red On, yellow Off Critical or major alarm occurs to service. Minor or remote alarm occurs to service. No service configured or no power supply.

37 VOLUME X (Volume Title) Page 37/ Interface MU04 provides 75Ω SMB unbalanced interface, with the maximum transmission distance reaching 70m. MU04 and TSB4 enable EPS for SPQ4. The specific protection principle is shown in Fig SLOT 14 TSB4 SLOT16 MU04 signal of switching control System Control Unit protecting SPQ4 working SPQ4 failure SLOT 4/5 4 x E 4 service SLOT12 SLOT13 Fig 2-14 EPS of SPQ4 When a working SPQ4 failure is detected, the cross-connect and timing unit will ask MU04 to transfer the signals to TSB4, thus to bridging the signals of MU04 and protection SPQ4. The slot assignment of SPQ4, MU04 and TSB4 is shown in Table 2-11 Board Protection group 1 Protection SPQ4 Slot 12 TSB4 Slot 14 Working SPQ4 Slot 13 MU04 Slot 16 Table 2-11 Slot assignment of SPQ4, MU04 and TSB4

38 VOLUME X (Volume Title) Page 38/103 Note: EPS is a scheme at device level. When the working board fails, the accessed signal will be protected by being bridged to the protection board. By this way, triggering of more complex protection at network level such as MSP and SNCP can be avoided, improving the equipment reliability Board Configuration Before using SPQ4 for running service, parameters should be set for it through NM. Configuration should be provided to the following bytes: J1 J1 is the path trace byte. Successive transmission of the higher order access point identifier through J1 at the transmit end helps the receive end learn that its connection with the specified transmit end is in continuous connection status. When J1 mismatch is detected at receive end, the corresponding VC-4 path will generate HP- TIM alarm. C2 C2 is the signal label byte, indicating the multiplexing structure of VC-4 frame and the payload property. It is required that the C2 bytes transmitted matches those received. Once mismatch is detected, the corresponding VC- 4 path will generate HP-SLM alarm and insert all 1 s into the C4 in downstream stations Technical Parameters Parameter Rate Description SPQ4 MU kbit/s or kbit/s Processing capability Line code pattern Process 4 E4/STM-1 electrical signals CMI Access 4 E4/STM-1 electrical signals Connector None SMB Size (mm) Weight (kg) Power consumption (W) 24 2

39 VOLUME X (Volume Title) Page 39/ PD3/PL3/D34S/C34S PD3 is the 6 E3/DS3 processing board; PL3 is the 3 E3/DS3 processing board. D34S is the 6 E3/DS3 PDH interface switching board, C34S is the 3 E3/DS3 PDH interface switching board. Table 2-12 shows the difference between PD3 and PL3. Board Comparison PD3 PL3 Processing capability 6 E3/DS3 3 E3/DS3 Available slots Slot 12, 13 Slot 12, 13 Interface board D34S C34S Table 2-12 Comparison between PD3 and PL Functions and Principles Functions PD3 can process 6 E3/DS3 signals, and PL3 can process 3 E3/DS3 signals. D34S provides 6 75Ω unbalanced E3/DS3 interfaces. C34S provides 3 75Ω unbalanced E3/DS3 interfaces. PD3/PL3 supports 1:1 EPS and SNCP, with the switching time less than 50ms. Support setting and query of all POH bytes at VC-3 level. Provide abundant alarm and performance events for convenient equipment management and maintenance. Support inloop and outloop at electrical interfaces for fast fault location. Support on-line query of the board information. Support smooth software upgrade and expansion Principles Fig 2-15 shows the functional diagram of PD3/PL3.

40 VOLUME X (Volume Title) Page 40/103 3/6 x E3/DS3 electrical signals Interface unit Mapping/ demapping unit Bus conversion unit Active crossconnect board Standby crossconnect board Timing unit Control and communication unit Clock signal Cross-connect and timing unit Power module -48V Fig 2-15 Functional diagram of PD3/PL3 The interface unit accesses E3/DS3 electrical signals through D34S/C34S and recovers the data and clock signals. Also, the interface unit performs decoding/encoding and jitter suppressing to the signals, generates and detects pseudo-random binary sequence (PRBS), and detects and inserts part of the alarms. The mapping/demapping unit maps/demaps the E3/DS3 signal, processes the lower order overhead, suppresses the jitter, and generates and detects the PRBS. The bus conversion unit converts the low speed bus at board side into the high speed bus at protection board side. The timing unit receives the 38M clock signal and 2K frame header from the active and standby cross-connect and timing units at the same time and performs the clock frequency conversion and drive of the board. Additionally, the 8K line reference clock signal is for board status checking. It is sent to the active and standby cross-connect boards and indicates whether the board works normal and whether the board is in position. The control and communication unit mainly functions control, communication and service configuration of the board. The power module provides all modules of the board with DC power supply with required voltage.

41 VOLUME X (Volume Title) Page 41/ Front Panel The front panel of PD3, PL3, D34S and C34S is shown in Fig 2-16, and the indicator description of PD3 and PL3 is shown in Table 2-13 Fig 2-16 The front panel of PD3, PL3, D34S and C34S

42 VOLUME X (Volume Title) Page 42/103 Indicator Board hardware indicator-stat Color and status On, green On, red On for 100ms and off for 100ms alternatively, red Off Description The board works normally. The board hardware fails. The board hardware is mismatched. The board is not powered on, or the service is not configured. Service On, green The service is activated. activation indicator-act Off The service is not activated. Board software indicator- PROG Service alarm indicator-srv On, green On for 100ms and off for 100ms alternatively, green On for 300ms and off for 300ms alternatively, green On, red Off On, green On, red On, yellow Off Upload of board software to FLASH or the FPGA upload is normal, or the board software initialization is normal. Board software is being uploaded to FLASH or FGPA The board software is initializing, and is in BIOS boot stage. The board software in FLASH or the FPGA configuration is lost, resulting in upload and initialization failure. No power supply. Service is normal, no service alarm occurs. Critical or major alarm occurs to service. Minor or remote alarm occurs to service. No service configured or no power supply. Table 2-13 Indicator description of PD3/PL3

43 VOLUME X (Volume Title) Page 43/ Interface Interface description of D34S and C34S is shown in Table 2-14 Board name D34S C34S Access capacity 6 E3/DS3 3 E3/DS3 Interface Interface Type Processing Board Equipped 75Ω unbalanced interface SMB angle female PD3 PL3 Slot available Slot 14, 16 Table 2-14 Interface description of D34S and C34S PD3/PL3, D34S/C34S and TSB8/TSB4 can work together to provide 1:1 EPS. Fig 2-17 shows the 1:1 EPS of PD3.The protection PD3 can be seated in Slot 12, and the working PD3 in Slot 13. D34S is in Slot 16, and TSB8 is in Slot 14. When a working PD3 failure is detected, the cross-connect and timing unit will ask the interface board to switch the service from service bus to protection bus for protection. SLOT 14 TSB8 SLOT16 D34S Signal of Switching control System Control unit protecting PD3 SLOT12 working PD3 failure SLOT13 SLOT 4/5 6?&E3 service Fig :1 EPS of PD3

44 VOLUME X (Volume Title) Page 44/ Board Configuration Before using PL3/PD3 for running service, parameters should be set for it through NM. Configuration should be provided to the following bytes: J2 It is the VC-3 path trace byte. Successive transmission of the lower order access point identifier through J1 helps the receive end learn that its connection with the transmit end in this path is in continuous connection status Technical Specifications Parameter Rate Processing capability Access Capability Line code pattern Description PL3 PD3 D34S C34S 34368kbit/s or 44736kbit/s 3 E3/DS3 6 E3/DS E3/DS3 3 E3/DS3 E3:HDB3, DS3:B3ZS Connector None None SMB SMB Size (mm) Weight (kg) Power consumption (W)

45 VOLUME X (Volume Title) Page 45/ PQ1/PQM/PD1/D75S/D12S/D12B PQ1 is the 63 E1 processing board; PQM is the 63 E1/T1 processing board; PD1 is the 32 E1 processing board; D75S is the 32 75Ω E1/T1 PDH interface switching board; D12S is the Ω E1/T1 PDH interface switching board; D12B is the 32 75Ω/120Ω E1/T1 PDH interface board. D75S, D12S and D12B can work as interfaces boards to receive/transmit E1/T1 service for PQ1/PQM/PD1. D75S and D12S can also work as switching boards to implement EPS for PQ1/PQM/PD1. Table 2-15 shows the difference between PQ1, PD1 and PQM. Board name Comparison PQ1 PQM PD1 Processing capability 63 E1 63 E1/T1 32 E1 Interface board (Providing EPS) 2 D75S or 2 D12S 2 D12S D75S or D12S Interface board (NOT providing EPS) 2 D12B 2 D12B D12B Table 2-15 Comparison between PQ1, PD1 and PQM Functions and Principles Functions D75S provides 32 75Ω unbalanced E1 interfaces; D12S provides Ω balanced E1/T1 interfaces; and D12B provides 32 75Ω/120Ω E1/T1 interfaces. PQM processes 63 E1/T1 signals, each of which can be configured as either E1 or T1 independently through software. PQ1 processes 63 E1 signals. PD1 processes 32 E1 signals. PQ1/PQM/PD1 supports 1:N (N 2) EPS, PP and SNCP, with the switching time less than 50ms. Provide abundant alarm and performance events for convenient equipment management and maintenance. Support inloop and outloop at electrical interfaces for fast fault location. Support on-line query of the board information. Support smooth software upgrade and expansion Principles 0ig 2-18 shows the functional diagram of PQ1/PQM/PD1.

46 VOLUME X (Volume Title) Page 46/103 E1/T1 electrical.. signals. Interface unit Frame header extraction & insertion unit Mapping/ demapping unit Bus conversion unit Active crossconnect board Standby crossconnect board Timing unit Control and communication unit Clock signal Cross-connect and timing unit Power module -48V Fig 2-18 Functional diagram of PQ1/PQM/PD1 The interface unit accesses 63 E1/T1 electrical signals through the interface board and recovers the data and clock signals. Also, the interface unit performs decoding/encoding and jitter suppressing to the signals, generates and detects PRBS, and detects and inserts part of the alarms. The frame header extraction & insertion unit extracts and inserts the frame header of T1 signal, and pass through the E1 service in both the transmit and receive directions. The mapping/demapping unit maps/demaps the E1/T1 signal, processes the lower order overhead, suppresses the jitter, and generates and detects the PRBS. The bus conversion unit converts the low speed bus at board side into the high speed bus at protection board side. The timing unit receives the 38M clock signal and 2K frame header from the active and standby cross-connect and timing units at the same time and performs the clock conversion and drive of the board. Additionally, the 8K line reference clock signal is for board status checking. It is sent to the active and standby cross-connect boards and indicates whether the board works normal and whether the board is in position. The control and communication unit mainly functions control, communication and service configuration of the board. The power module provides all modules of the board with DC power supply with required voltage.

47 VOLUME X (Volume Title) Page 47/ Front Panel The front panel of PQ1, PQM, PD1, D75S, D12S and D12B is shown in Fig 2-19, and the indicator description of PQ1, PD1 and PQM is shown in Table Fig 2-19 Front panel of PQ1, PQM, PD1, D75S, D12S and D12B

48 VOLUME X (Volume Title) Page 48/103 Indicator Board hardware indicator-stat Color and status On, green On, red On for 100ms and off for 100ms alternatively, red Off Description The board works normally. The board hardware fails. The board hardware is mismatched. The board is not powered on, or the service is not configured. Service On, green The service is activated. activation indicator-act Off The service is not activated. Board software indicator- PROG Service alarm indicator-srv On, green On for 100ms and off for 100ms alternatively, green On for 300ms and off for 300ms alternatively, green On, red Off On, green On, red On, yellow Off Upload of board software to FLASH or the FPGA upload is normal, or the board software initialization is normal. Board software is being uploaded to FLASH or FGPA The board software is initializing, and is in BIOS boot stage. The board software in FLASH or the FPGA configuration is lost, resulting in upload and initialization failure. No power supply. Service is normal, no service alarm occurs. Critical or major alarm occurs to service. Minor or remote alarm occurs to service. No service configured or no power supply. Table 2-16 Indicator description of PQ1, PD1 and PQM

49 VOLUME X (Volume Title) Page 49/ Interface Table 2-17 shows the difference between D75S, D12S and D12B. Comparison Board name D75S D12S D12B Service accessed 32 E1 32 E1/T1 32 E1/T1 Interface 75Ω unbalanced interface 120Ω balanced interface 75Ω unbalanced interface and 120Ω balanced interface Interface type DB44 DB44 DB44 Slot Slot 14 ~ 16 Slot14 ~ 17 Slot14 ~ 17 Table 2-17 Comparison between D75S, D12S and D12B PQ1/PQM/PD1 and D75S/D12S can be provided with 1:2 EPS. Fig 2-20 shows the EPS of PQ1.Slot 11 is for protection PQ1, while Slot is for working PQ1/PQM/PD1. Slot 14 ~ 15 and 15 ~ 17 is for interface board D75S/D12S. When a working PQ1 fails, the cross-connect unit will ask the interface board to switch the service to protection PQ1 for protection. SLOT 14 SLOT16 D75S D75S Signal of Switch Control System Control Unit Protecting PQ1 Working PQ1 Working PQ1 SLOT 4/5 Failure E1 Service Fig :2 EPS of PQ1 SLOT11 SLOT12 SLOT13

50 VOLUME X (Volume Title) Page 50/ Board Configuration Before using PQ1/PQM/PD1 for running service, parameters should be set for it through NM. Configuration should be provided to the following byte for PQ1/PQM/PD1: J2 It is the VC-12 path trace byte. Successive transmission of the lower order access point identifier through J1 helps the receive end learn that its connection with the transmit end in this path is in continuous connection status Technical Parameters Rate Parameter Description PQ1 PQM PD1 D75S D12S D12B 1544kbit/s or 2048kbit/s Processing capability Process 63 E1 Process 63 E1/T1 Process 32 E1 Access 32 E1 Access 32 E1/T1 Access 32 E1/T1 Line code pattern E1: HDB3, T1: B8ZS, AMI Connector None None None DB44 DB44 DB44 Size (mm) Weight (kg) Power consumption (W)

51 VOLUME X (Volume Title) Page 51/ EGS2 EGS2 is the 2-port Gigabit Ethernet (GE) optical interface board with Lanswitch. EGS2 can transparently transmit and converge the GE service. When working together with EFS0 and EFS4, the FE service can be converged into GE service and the Layer 2 switching can be performed. EGS2 can be seated in Slot Functions and Principles Functions Provides 2 LC 1000BASE-SX/LX Ethernet optical interfaces with auto-negotiation function, that is, they can be set to enabled or disabled. The transmission distance of the interfaces is 500m (multimode) or 10km (single-mode), or you can select the 40km or 70km optical module as required in practice. Support bandwidth adjustment at granularity of 64kbit/s and service mapping into VC-12 or VC-3 level. The service supports global functional plane (GFP), link access procedure-sdh (LAPS) and highlevel data link control (HDLC) encapsulation. Support Link Capacity Adjustment Scheme (LCAS), achieving higher transmission bandwidth utility. Support the Ethernet Layer 2 switching, rapid spanning tree protocol (RSTP), and point-to-point and point-to-multipoint multiprotocol label switching (MPLS) Layer 2 virtual private network (VPN). Support IEEE 802.1q-compliant and IEEE 802.1p-compliant virtual local area network (VLAN) and VLAN convergence. Support Layer 2-based convergence and point-to-multipoint convergence. EGS2 can work with EFS0 and EFS4 to converge the FE service into GE service. Support the port-based and port + VLAN-based flow classification, and the priority setting and queue adjusting of flow. Support IEEE802.3X-compliant flow control. Support inloop and outloop of all kinds for fast fault location. Provide abundant alarm and performance events for convenient equipment management and maintenance Principles Fig 2-21 shows the functional diagram of EGS2.

52 VOLUME X (Volume Title) Page 52/103 Front panel Backplane Interface processing module Service processing module Encapsulation module Mapping module Control and communication module Power module -48V Fig 2-21 Functional diagram of EGS2 In receive direction: The interface processing module accesses the 1000BASE-SX/LX signals from external Ethernet equipments such as Ethernet switch and router and performs decoding and serial/parallel conversion to the signals. Then, the signals are sent to the service processing module for frame delimitation, preamble field code stripping, cyclic redundancy code (CRC) termination and Ethernet performance statistics. And flow classification is performed according to the service type and configuration requirement (message formats MPLS, L2 MPLS VPN and Ethernet/VLAN are supported), and Tunnel and VC double labels are added according to the service for mapping and transfer. At the encapsulation module, the HDLC, LAPS or GFP encapsulation is performed to the Ethernet frame. After that, the services are mapped into VC-3 or VC-12 at the mapping module and then sent to the crossconnect unit. In transmit direction: The VC-3 or VC-12 signals from the cross-connect unit are demapped and sent to the encapsulation module for decapsulation. The service processing module determines the route according to the level of the equipment, and performs flow classification according to the service type and configuration requirement. Also, frame delimitation, adding preamble field code, CRC calculation and performance statistics are performed by the service processing module. Finally, the signals are sent out from the Ethernet interface after serial/parallel conversion and encoding at interface processing module. Control and communication module The control and communication unit mainly functions control, communication and service configuration of the board. Power module The power module provides all modules of the board with DC power supply with required voltage Front Panel The front panel of EGS2 is shown in Fig The indicator description is shown in Table Fig 2-22 The front panel of EGS2 Indicator Color and status Description Board On, green The board works normally.

53 VOLUME X (Volume Title) Page 53/103 Indicator Color and status Description hardware indicator- On, red The board hardware fails. STAT On for 100ms and off for 100ms alternatively, red The board hardware is mismatched. Service activation indicator- ACT Board software indicator- PROG Service alarm indicator- SRV LINK* ACT* Off On, green Off On, green On for 100ms and off for 100ms alternatively, green On for 300ms and off for 300ms alternatively, green On, red Off On, green On, red On, yellow Off On, green Off On for 100ms and off for 100ms alternatively, orange Off The board is not powered on, or the service is not configured. The service is activated. The service is not activated. Upload of board software to FLASH or the FPGA upload is normal, or the board software initialization is normal. Board software is being uploaded to FLASH or FGPA The board software is initializing, and is in BIOS boot stage. The board software in FLASH or the FPGA configuration is lost, resulting in upload and initialization failure. No power supply. Service is normal, no service alarm occurs. Critical or major alarm occurs to service. Minor or remote alarm occurs to service. No service configured or no power supply. The GE port is connected with the opposite equipment, and the link is established. The GE port is not connected with the opposite equipment, and the link is not available. There is data exchanged between the GE port and opposite equipment. There is no data exchanged between the GE port and opposite equipment. Table 2-17 Front panel and indicator description of EGS2

54 VOLUME X (Volume Title) Page 54/ Interface EGS2 supports the small-form pluggable (SEP) LC optical interface, and 1000Base-SX and 1000Base-LX interfaces. The interface transmission distance reaches 500m (multimode) or 10km (single-mode). Table 2-18 shows the interface characteristics of EGS2. Connector Optical interface type Specifications Line code LC 1000Base-SX or 1000Base-LX IEEE 802.3z-compliant Manchester coding (10M), MLT-3 or NRZI Table 2-18 Interface characteristics of EGS Board Configuration Before using EGS2 for running service, parameters should be set for it through NM. Configuration should be provided to the following bytes: J1 J1 is the path trace byte. Successive transmission of the higher order access point identifier through J1 at the transmit end helps the receive end learn that its connection with the specified transmit end is in continuous connection status. When J1 mismatch is detected at receive end, the corresponding VC-4 path will generate HP- TIM alarm. C2 C2 is the signal label byte, indicating the multiplexing structure of VC-4 frame and the payload property. It is required that the C2 bytes transmitted matches those received. Once mismatch is detected, the corresponding VC- 4 path will generate HP-SLM alarm and insert all 1 s into the C4 in downstream stations. Ethernet port working mode The Ethernet ports of the interconnected equipments are generally required to work in the same fixed mode. If not, packet loss or rate decrease will happen, and even complete service interruption will be resulted when the traffic is heavy Technical Parameters Parameter Board Rate Processing capability Line code pattern Connector Description EGS2 1000Mbit/s Mbit/s Ethernet signals Manchester coding (10M), MLT-3 or NRZI LC (SFP) Size (mm) Weight (kg) Power consumption (W) 39 Optical module type 1000Base-SX 1000Base-LX Transmission distance (km) 0~0.5 0~10

55 VOLUME X (Volume Title) Page 55/103 Mean launched power (dbm) -9.5 ~ 0-9 ~ -3 Receiver sensitivity (dbm) Central wavelength (nm)

56 VOLUME X (Volume Title) Page 56/ EFS4/EFS0/ETF8 EFS4 is the 4-ports fast Ethernet processing board with Lanswitch, EFS0 is the fast Ethernet processing board with Lanswitch. They are responsible for transparent transmission, convergence and Layer 2 switching of the Ethernet signal. Table 2-19 shows the difference between EFS4 and EFS0. Board name Comparison EFS4 EFS0 Processing capability 4 10M/100M 8 10M/100M Interface board None ETF8 Ports at panel 4 0 Slot available Slot 11 ~ 13 Slot 12 ~ 13 Table 2-19 Comparison between EFS4 and EFS Functions and Principles Functions EFS4 provides 4 10Base-T/100Base-TX ports (RJ-45) with autonegotiation function, that is, they can be set to enabled or disabled. The transmission distance is up to 100m. ETF8 provides 8 10Base-T/100Base-TX ports (RJ-45) with autonegotiation function, that is, they can be set to enabled or disabled. The transmission distance is up to 100m. EFS4 can process 4 10M/100M Ethernet services. EFS0 can process 8 10M/100M Ethernet services, support 64kbit/s bandwidth adjustment and service mapping into VC-12 or VC-3 level. The service supports GFP, LAPS and HDLC encapsulation. Support LCAS, achieving higher transmission bandwidth utility. Support the Ethernet Layer 2 switching, RSTP, and point-to-point and point-to-multipoint MPLS Layer 2 VPN. Support IEEE 802.1q-compliant and IEEE 802.1p-compliant virtual local area network (VLAN) and VLAN convergence. Support Layer 2-based convergence and point-to-multipoint convergence. EFS4 and EFS0 can work with EGS2 to converge the FE service into GE service. Support the port-based and port + VLAN-based flow classification, and the priority setting and queue adjusting of flow. Support IEEE802.3X-compliant flow control. Support inloop and outloop of all kinds for fast fault location. Provide abundant alarm and performance events for convenient equipment management and maintenance.

57 VOLUME X (Volume Title) Page 57/ Principles Fig 2-23 shows the functional diagram of EFS0. Front panel Backplane Interface processing module (ETF8) Service processing module Encapsulation module Mapping module Control and communication module Power module -48V Fig 2-23 Functional diagram of the EFS0 In receive direction: The interface processing module accesses the 10/100BASE-TX signals from external Ethernet equipments such as Ethernet switch and router and performs decoding and serial/parallel conversion to the signals. Then, the signals are sent to the service processing module for frame delimitation, preamble field code stripping, cyclic redundancy code (CRC) termination and Ethernet performance statistics. And flow classification is performed according to the service type and configuration requirement (message formats MPLS, L2 MPLS VPN and Ethernet/VLAN are supported), and Tunnel and VC double labels are added according to the service for mapping and transfer. At the encapsulation module, the HDLC, LAPS or GFP encapsulation is performed to the Ethernet frame. After that, the services are mapped into VC-3 or VC-12 at the mapping module and then sent to the cross-connect unit. In transmit direction: The VC-3 or VC-12 signals from the cross-connect and timing unit are demapped and sent to the encapsulation module for decapsulation. The service processing module determines the route according to the level of the equipment, and performs flow classification according to the service type and configuration requirement. Also, frame delimitation, adding preamble field code, CRC calculation and performance statistics are performed by the service processing module. Finally, the signals are sent out from the Ethernet interface after serial/parallel conversion and encoding at interface processing module. Control and communication module The control and communication unit mainly functions control, communication and service configuration of the board. Power module The power module provides all modules of the board with DC power supply with required voltage Front Panel The front panel of EFS0, EFS4 and ETF8 is shown in Fig 2-24 and the indicator description is shown in Table 2-20

58 VOLUME X (Volume Title) Page 58/103 Fig 2-24 The front panel of EFS0, EFS4 and ETF8

59 VOLUME X (Volume Title) Page 59/103 Indicator Color and status Description On, green The board works normally. Board hardware indicator- STAT Service activation indicator- ACT Board software indicator- PROG Service alarm indicator- SRV On, red On for 100ms and off for 100ms alternatively, red Off On, green Off On, green On for 100ms and off for 100ms alternatively, green On for 300ms and off for 300ms alternatively, green On, red Off On, green On, red On, yellow Off The board hardware fails. The board hardware is mismatched. The board is not powered on, or the service is not configured. The service is activated. The service is not activated. Upload of board software to FLASH or the FPGA upload is normal, or the board software initialization is normal. Board software is being uploaded to FLASH or FGPA The board software is initializing, and is in BIOS boot stage. The board software in FLASH or the FPGA configuration is lost, resulting in upload and initialization failure. No power supply. Service is normal, no service alarm occurs. Critical or major alarm occurs to service. Minor or remote alarm occurs to service. No service configured or no power supply. T Table 2-20 Indicator description of EFS0, EFS4

60 VOLUME X (Volume Title) Page 60/ Interface EFS4 provides 4 Ethernet ports, and ETF8 provides the EFS0 with 8 ports. Table 2-21 shows the ports characteristics. Type Impedance Specifications Line code RJ Ω IEEE compliant Manchester coding (10M), MLT-3 or NRZI Table 2-21 Ethernet ports characteristics Two indicators for each interface, their meanings shown in Table 2-22 Color Meaning Silkscreen Description Green link LINK* On: link is established; Off: no link is established. Orange activity ACT* Flash: There is data transmitted/received; Off: there is no data transmitted/received. Table 2-22 Meanings of LED indicators on RJ-45 connector Board Configuration Before using EFS4 or EFS0 for running service, parameters should be set for it through NM. Configuration should be provided to the following bytes: J1 J1 is the path trace byte. Successive transmission of the higher order access point identifier through J1 at the transmit end helps the receive end learn that its connection with the specified transmit end is in continuous connection status. When J1 mismatch is detected at receive end, the corresponding VC-4 path will generate HP- TIM alarm. C2 C2 is the signal label byte, indicating the multiplexing structure of VC-4 frame and the payload property. It is required that the C2 bytes transmitted matches those received. Once mismatch is detected, the corresponding VC- 4 path will generate HP-SLM alarm and insert all 1 s into the C4 in downstream stations. Ethernet port working mode The Ethernet ports of the interconnected equipments are generally required to work in the same fixed mode. If not, packet loss or rate decrease will happen, and even complete service interruption will be resulted when the traffic is heavy.

61 VOLUME X (Volume Title) Page 61/ Technical Parameters Parameter Rate Description EFS4 EFS0 EFT8 10Mbit/s, 100Mbit/s Processing capability 4 10M/100M 8 10M/100M None Accessing capability 4 10M/100M M/100M Line code pattern Manchester coding (10M), MLT-3 or NRZI Connector RJ-45 None RJ-45 Size (mm) Weight (kg) Power consumption (W)

62 VOLUME X (Volume Title) Page 62/ CXL1/CXL4/CXL16 CXL1, CXL4 and CXL16 are boards integrating the functions of the SDH processing unit, system control & communication unit, cross-connect unit and timing unit at levels of STM-1, STM-4 and STM-16 respectively. Table 2-23 shows a comparison between CXL1, CXL4 and CXL16. Board name CXL1 CXL4 CXL16 Ling processing capacity Cross-connect capacity (higher order / lower order) Clock function System control function 1 STM-1 1 STM-4 1 STM-16 40G/5G 40G/5G 40G/5G Same Same Table 2-23 Comparison between CXL1, CXL4 and CXL Functions and Principles SDH processing unit The CXL1, CXL4 and CXL16 boards are responsible for receiving and transmitting one channel of optical signal at STM-1, STM-4 and STM- 16 level respectively. Their optical interfaces are compliant with ITU-T Recommendation G.957. Frame structures are compliant with ITU-T Recommendation G.707, and the jitter specifications compliant with ITU-T Recommendation G.825 and G.958. The CXL1 supports S-1.1, L-1.1, L-1.2, and Le-1.2 optical modules for different transmission distances. The CXL4 supports S-4.1, L-4.1, L-4.2, and Le-4.2 optical modules for different transmission distances. The CXL16 supports 1-16, S-16.1, L-16.1, and L-16.2 optical modules for different transmission distances. The CXL16 supports VC-4-4c, VC-4-8c and VC-4-16c concatenated services. The CXL16 can connect with the optical multiplex board of wavelength division equipment without wavelength converter. Support various protection schemes, such as 2-fiber or 4-fiber bidirectional MSP ring, linear MSP and SNCP. Provide abundant alarm and performance events for convenient equipment management and maintenance. Provide inloop and outloop at optical interfaces and VC-4 level for fast fault locating. Support ALS function, avoiding laser injury to human body during maintenance. Support the on-line query of board information and optical power.

63 VOLUME X (Volume Title) Page 63/103 Support smooth upgrade and capacity expansion of software System control & communication unit Configure and groom services, monitor service performance, and collect performance event and alarm information. Provide 10M and 100M compatible Ethernet NM interface. Provide F&f interface through AUX board for TDA, COA and DCU management. Provide two 4M HDLC emergency paths for realizing MSP and SNCP. Provide the OAM interface through AUX board, support remote maintenance of the Modem of RS-232 DEC. Provide 30 DCC to realize the transmit link for network management. Support fan alarm and management function. Provide PIU with lightening protection and in-position detection functions Functions of cross-connect unit Implement 40G VC-4 full cross-connect, and 5G VC-12/VC-3 full crossconnect. Realize flexible service grooming, including loopback, crossconnection, group-broadcasting and broadcasting. Ensure the normal running of other services after provisioning or removing a certain service. Support SNCP at VC-3 and VC-12 levels. Support AU4-4C, AU4-8C and AU4-16C concatenated services. Support 1+1 hot backup, revertively and non-revertively. The default is non-revertive Timing unit Provide standard system synchronization clock. Input two channels of 2048kHz or 2048kbit/s timing signals, and support the function of selecting external timing source. Output two channels of 2048kHz or 2048kbit/s timing signals. Provide SSM and the function of extracting, inserting and processing clock ID Principle Take CXL16 as an example. Fig 2-27 shows the system diagram of CXL16.The CXL16 integrates SDH processing unit, cross-connect unit SCC and timing unit at STM-16 level.

64 VOLUME X (Volume Title) Page 64/103 Front P anel S T M -16 S D H processing unit Back plane cross-connect unit S C C tim ing unit Fig 2-27 CXL16 system diagram Front Panel Fig 2-26 shows the front panels of CXL1, CXL4 and CXL16. 0 shows the relevant description. Fig 2-26 Front panels of CXL1, CXL4 and CXL16

65 VOLUME X (Volume Title) Page 65/103 Indicator status: Indicator Color and status On, green Description The board works normally. Board hardware indicator - STAT On, red On for 100ms and off for 100 ms, red Off The board hardware fails. The board hardware is mismatched. The board is not powered on, or service is not configured. Service activation indicator of cross-connect unit - ACTX On, green Off The cross-connect unit is in active status. The cross-connect unit is in standby status. Service activation indicator of SCC - ACTC On, green Off The SCC is in active status. The SCC is in standby status. Board software indicator - PROG On, green On for 100ms and off for 100 ms, green On for 300 ms and off for 300 ms, green On, red Off Upload of board software or the FPGA in FLASH is normal, or the board software initialization is normal. Broad software is being uploaded to FLASH or FGPA. The board software is initializing, and is in BIOS boot stage. The board software in FLASH or FPGA is lost, resulting in upload and initialization failure. No power supply. Service alarm indicator of cross-connect unit - SRVX Service alarm indicator of line On, green On, red On, green Service operates normally on the crossconnect unit. Switching (for example, EPS) occurs to the service on the cross-connect unit. Service operates normally on the line unit. No alarm occurs.

66 VOLUME X (Volume Title) Page 66/103 Indicator status: Indicator unit - SRVL Color and status On, red On, yellow Off Description Critical or major alarm occurs to the service on the line unit. Minor or remote alarm occurs to the service on the line unit. The line service is not configured or there is no power supply. ALMC On, yellow Off Alarm is cut off permanently. Alarm is provided normally. Table 2-24 Front panel and its description of CXL Interfaces The CXL1, CXL4 and CXL16 use LC connectors Board Configuration Before using CXL for running services, set parameters through the NM. Line board needs the following setting: J1 byte J1 is the path trace byte. It is used to transmit continuously the higher order access point identifier. The receive end verifies the continuous connecting of the intended transmit end by this byte. When J1 is detected to be mismatch at the receive end, the corresponding VC-4 path generates an HP-TIM alarm. C2 byte C2 is the signal label byte, indicating the multiplexing structure of VC frame and the payload property. C2 from the transmit end should match that at the received end. If mismatch is detected, the corresponding VC-4 path generates an HP-SLM alarm. Also C4 will be set to all 1 in downstream stations.

67 VOLUME X (Volume Title) Page 67/ Technical Parameters Description Parameter CXL1 CXL4 CXL16 Rate kbit/s kbit/s kbit/s Processing capability Connector Line, SCC, cross-connect and timing LC Size (mm) x 220 x 25.4 Weight (kg) Power consumption CXL1 Optical module type Wavelength (nm) Transmission distance (km) Launched Optical Power (dbm) Receiver Sensitivity (dbm) S-1.1 L-1.1 L-1.2 Le CXL4 Optical module type Wavelength (nm) Transmission distance (km) Launched Optical Power (dbm) Receiver Sensitivity (dbm) S-4.1 L-4.1 L-4.2 Le CXL16 Optical module type Wavelength (nm) I-16 S-16.1 L-16.1 L

68 VOLUME X (Volume Title) Page 68/103 Parameter Transmission distance (km) Launched Optical Power (dbm) Receiver sensitivity (dbm) Description CXL1 CXL4 CXL

69 VOLUME X (Volume Title) Page 69/ EOW EOW offers order wire phone and data interfaces. EOW is seated in Slot Functions and Principles Functions It provides: One orderwire phone Four broadcast data interfaces S1~S Principles Fig 2-27 shows the functional diagram of EOW. System control & communication unit Ring generaating&reset, clock unit Overhead processing unit Broadcast data and orderwire phone unit ~ Orderwire phone S1 S4 Backplane Fig 2-27 The functional diagram of EOW Front Panel The appearance of EOW is shown in Fig Its interface description is listed in Table The indicator STAT on the front panel is described in Table Fig 2-28 The front panel of EOW

70 VOLUME X (Volume Title) Page 70/103 Interface PHONE Description Orderwire Phone Interface S1 Serial 1 S2 Serial 2 S3 Serial 3 S4 Serial 4 Table 2-24 Description of the EOW interface on the front panel Indicator Color and status Description On, green The board works normally. Board hardware status indicator- STAT Board software status indicator- PROG On, red On for 100ms and off for 100ms alternatively, red Off Off On, green On for 100ms and off for 100ms alternatively, green On for 300ms and off for 300ms alternatively, green On, red Off The board hardware fails. The board hardware is mismatched. The board is not powered on or service is not configured. The cross-connect unit is in protection status. Upload of board software to FLASH or the FPGA upload is normal, or the board software initialization is normal. Board software is being uploaded to FLASH or FGPA The board software is initializing, and is in BIOS boot stage. The board software in FLASH or the FPGA configuration is lost, resulting in upload and initialization failure. No power supply. Table 2-25 Description of the indicators of EOW

71 VOLUME X (Volume Title) Page 71/ Interface The orderwire phone interface of EOW is RJ-11, the interface of S1 S4 is the type of RJ Technical Parameters Parameter Board name Processing capability Description EOW Orderwire phone & data access Size (mm) Weight (kg) 0.4 Power consumption (W) 10

72 VOLUME X (Volume Title) Page 72/ AUX AUX is the system auxiliary interface board, seated in slot Functions and Principles Functions Provides one ETH interface for NM. Provides one COM interface for debugging. Monitors two independent -48V power and reports the result of overvoltage when the voltage exceeds -72V or under-voltage when the voltage is under -38.4V. Provides the function of three inputs & one output Boolean value. Provides the backup power of 3.3V, 80W for all the boards and monitors the 3.3V backup power. Provides the function of sound alarm. Provides the operation administration and maintenance (OAM) interface which can be used as serial interface of NM, supporting remote maintenance of the Modem of RS-232 data connected equipment (DCE) and the X.25 protocol. Manages the serial interface of F&f which is the same as OAM interface for managing external devices such as TDA, COA and DCU. Provides two BITS clock input interfaces and two BITS clock output interfaces Principles Fig 2-29 shows the functional diagram of AUX.

73 VOLUME X (Volume Title) Page 73/103 OAM F&f Interface module CLK External clock input/output modul Clock bus ETH COM Communications module 2 interfa ces of NM ALM Power monitoring module Boolean value of 3 inputs and 1 output Two -48V power monitoring 3.3V backup power monitoring Front panel Backplane Fig 2-29 The functional diagram of AUX Interface module The interface module provides access of OAM and F&f. OAM and F&f use the same serial port, and are led out on the front panel through RJ-45 interface. External clock input/output module The external clock input/output module performs access and processing of two building integrated timing supply systems (BITS), and outputs two clock signals. The input and output share one RJ-45 interface with the impedance of 120Ω. Communication module The module provides on the front panel one NT interface (ETH) and one debugging interface (COM), which pass through RJ-45 interface. Power monitoring module The power monitoring module monitors two -48V power and 3.3V backup power, accomplishes the Boolean value of three inputs and one output, and is led out on the front panel through RJ-45 interface.

74 VOLUME X (Volume Title) Page 74/ Front Panel The front panel of AUX is shown in Fig Fig 2-30 The front panel of AUX Interface The interface provided by AUX is shown in Table 2.26 Interface COM ETH CLK Description Debugging interface, RJ-45 NM interface, RJ-45 External clock input/output interface, RJ-45 ALM OAM/F&f Boolean value input/output, RJ-45 Serial interface for NM or OAM, RJ-45 Table 2-26 Description of AUX interfaces Technical Parameters Parameter Board name Processing capability Description AUX System control, inter-board communication, orderwire, and power detection Size (mm) Weight (kg) 0.4 Power consumption (W) 15