Low Power Programmable Timing Control Hub for P4 processor

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Low Power Programmable Timing Control Hub for P4 processor Recommended Application: Low Power CK55 Compliant Main Clock Output Features: 2.8V pushpull differential CPU pairs 7.

1 Low Power Programmable Timing Control Hub for P4 processor Recommended Application: Low Power CK55 Compliant Main Clock Output Features: 2.8V pushpull differential CPU pairs 7.8V pushpull differential PCIEX pairs.8v pushpull differential SATA pair.8v pushpull differential CPU/PCIEX selectable pair.8v pushpull differential 27MHz/LCDCLK/PCIEX selectable pair 4 PCI (33MHz) 2 PCICLK_F, (33MHz) freerunning USB, 48MHz DOT96/PCIEX selectable pair 2 REF, 4.38MHz Key Specifications: CPU outputs cyclecycle jitter < 85ps PCIEX outputs cyclecycle jitter < 25ps SATA outputs cyclecycle jitter < 25ps PCI outputs cyclecycle jitter < 5ps +/ ppm frequency accuracy on CPU, PCIEX and SATA clocks +/ ppm frequency accuracy on USB clocks Features/Benefits: Supports tight ppm accuracy clocks for SerialATA and PCIEX Supports programmable spread percentage and frequency Uses external 4.38MHz crystal, external crystal load caps are required for frequency tuning PEREQ# pins to support PCIEX power management. Low power differential clock outputs (No 5Ω resistor to GND needed) iamt support Pin Configuration VDDPCI GND 2 PCICLK 3 PCICLK2 4 *SELPCIEX_LCD#/PCICLK3 5 GND 6 VDDPCI 7 ITP_EN/PCICLK_F4 8 *SELLCD_27#/PCICLK_F5 9 VttPWR_GD/PD# VDD48 FS L A/USB_48MHz 2 GND 3 PCIeT_L9/DOTT_96MHzL 4 PCIeC_L9/DOTC_96MHzL 5 FS L B/TEST_MODE 6 27FIX/LCD_SSCGT/PCIeT_L 7 27SS/LCD_SSCGC/PCIeC_L 8 PCIeT_L 9 PCIeC_L 2 VDDPCIEX 2 PCIeT_L2 22 PCIeC_L2 23 PCIeT_L3 24 PCIeC_L3 25 SATACLKT_L 26 SATACLKC_L 27 VDDPCIEX 28 GND 29 PCIeT_L4 3 PCIeC_L4 3 *PEREQ3# 32 ICS9LPR PCICLK/REQ_SEL** 63 PCI/PCIEX_STOP# 62 CPU_STOP# 6 REF/FSLC/TEST_SEL 6 REF 59 GND 58 X 57 X2 56 VDDREF 55 SDATA 54 SCLK 53 GND 52 CPUT_L 5 CPUC_L 5 VDDCPU 49 CPUT_LF 48 CPUC_LF 47 VREF 46 GNDA 45 VDDA 44 CPUITPT_L2/PCIeT_L8 43 CPUITPC_L2/PCIeC_L8 42 VDDPCIEX 4 PEREQ#/PCIeT_L7 4 PEREQ2#/PCIeC_L7 39 PCIeT_L6 38 PCIeC_L6 37 GND 36 PCIeT_L5 35 PCIeC_L5 34 PWRSAVE#* 33 PEREQ4#* Latch Select Table Pin5 Pin9 Pin4/5 Pin7/8 SELPCIEX_LCD#/ SELLCD_27#= PCIEX9 27FIX/SS PCI3 = (low) SELLCD_27#= DOT96 LCD SELPCIEX_LCD#/ SELLCD_27#= PCIEX9 PCIEX PCI3 = (high) SELLCD_27#= DOT96 PCIEX Functionality Table FS LC FS LB FS LA CPU PCI MHz PCIEX MHz MHz Spread % % Down % Down % Down % Down % Down % Down % Down % Down 64TSSOP * Internal PullUp Resistor ** Internal PullDown Resistor Note: Please add an external resistor for pull up or down, never rely on an internal resistor when the pin is connected to a device 99 8/2/8

2 Pin Description PIN # PIN NAME TYPE DESCRIPTION VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GND PWR Ground pin. 3 PCICLK OUT PCI clock output. 4 PCICLK2 OUT PCI clock output. 5 *SELPCIEX_LCD#/PCICLK3 #N/A #N/A 6 GND PWR Ground pin. 7 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 8 ITP_EN/PCICLK_F4 I/O Free running PCI clock not affected by PCI_STOP#. ITP_EN: latched input to select CPU_ITP/SRC output functionality = CPU_ITP pair = SRC pair 9 *SELLCD_27#/PCICLK_F5 I/O Free running PCI clock not affected by PCI_STOP#. SELLCD_27#: latched input to select pin functionality. See Latch Select Table VttPWR_GD/PD# IN This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the device into a low power state. VDD48 PWR Power pin for the 48MHz output.3.3v 2 FSLA/USB_48MHz I/O 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V. 3 GND PWR Ground pin. 4 PCIeT_L9/DOTT_96MHzL OUT True clock of.8v differential pushpull PCI_Express pair / True clock of differential DOT96 output pair. (no 5ohm resistor to GND needed) 5 PCIeC_L9/DOTC_96MHzL OUT Complement clock of.8v differential pushpull PCI_Express pair. / Complement clock of differential DOT96 pushpull output. (no 5ohm resistor to GND needed) 6 FSLB/TEST_MODE IN 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between HiZ and REF/N divider mode while in test mode. Refer to Test Clarification Table. 7 27FIX/LCD_SSCGT/PCIeT_L OUT 27MHz NonSpread PushPull output / True clock of low power LCDCLK output / True clock of low power PCIEXCLK differential pair/ selected by SELPCIEX_LCD# and SELLCD_27#. No 5ohm resistor to GND needed for differential outputs. 8 27SS/LCD_SSCGC/PCIeC_L OUT 27MHz Spreading PushPull output / Complementary clock of LCDCLK_SS output / Complementary clock of PCIEXCLK differential pair/ selected by SELPCIEX_LCD# and SELLCD_27#. No 5ohm resistor to GND needed for differential outputs. 9 PCIeT_L OUT True clock of.8v differential pushpull PCI_Express pair (no 5ohm resistor to GND needed) 2 PCIeC_L OUT Complement clock of.8v differential pushpull PCI_Express pair. (no 5ohm resistor to GND needed) 2 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 22 PCIeT_L2 OUT True clock of.8v differential pushpull PCI_Express pair (no 5ohm resistor to GND needed) 23 PCIeC_L2 OUT Complement clock of.8v differential pushpull PCI_Express pair. (no 5ohm resistor to GND needed) 24 PCIeT_L3 OUT True clock of.8v differential pushpull PCI_Express pair (no 5ohm resistor to GND needed) 25 PCIeC_L3 OUT Complement clock of.8v differential pushpull PCI_Express pair. (no 5ohm resistor to GND needed) 26 SATACLKT_L OUT True clock of.8v pushpull differential SATA pair. (no 5ohm resistor to GND needed) 27 SATACLKC_L OUT Complement clock of.8v pushpull differential SATA pair. (no 5ohm resistor to GND needed) 28 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 29 GND PWR Ground pin. 3 PCIeT_L4 OUT True clock of.8v differential pushpull PCI_Express pair (no 5ohm resistor to GND needed) 3 PCIeC_L4 OUT 32 *PEREQ3# IN Complement clock of.8v differential pushpull PCI_Express pair. (no 5ohm resistor to GND needed) Realtime input pin that controls PCIEXCLK outputs that are selected through the I2c. = disabled, = enabled. 99 8/2/8 2

3 Pin Description (Continued) PIN # PIN NAME TYPE DESCRIPTION 33 PEREQ4#* IN Realtime input pin that controls PCIEXCLK outputs that are selected through the I2c. = disabled, = enabled. 34 PWRSAVE#* IN Activelow input pin used to change frequency to underclocked entries in the ROM table that can be preprogrammed through Byte 6 of the I2c. 35 PCIeC_L5 OUT Complement clock of.8v differential pushpull PCI_Express pair. (no 5ohm resistor to GND needed) 36 PCIeT_L5 OUT True clock of.8v differential pushpull PCI_Express pair (no 5ohm resistor to GND needed) 37 GND PWR Ground pin. 38 PCIeC_L6 OUT Complement clock of.8v differential pushpull PCI_Express pair. (no 5ohm resistor to GND needed) 39 PCIeT_L6 OUT True clock of.8v differential pushpull PCI_Express pair (no 5ohm resistor to GND needed) 4 PEREQ2#/PCIeC_L7 I/O Realtime input pin that controls PCIEXCLK outputs that are selected through the I2c. = disabled, = enabled. / Complement clock of differential low power PCI Express output. No 5ohm resistor to GND needed. 4 PEREQ#/PCIeT_L7 I/O Realtime input pin that controls PCIEXCLK outputs that are selected through the I2c. = disabled, = enabled. / True clock of differential low power PCI Express output. No 5ohm resistor to GND needed. 42 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 43 CPUITPC_L2/PCIeC_L8 OUT Complement clock of differential pair CPU output. / Complement clock of differential PCIEX pair. These are.8v push pull outputs. No 5ohm resistor to GND needed. 44 CPUITPT_L2/PCIeT_L8 OUT True clock of differential pair CPU output. / True clock of differential PCIEX pair. These are.8v push pull outputs. No 5ohm resistor to GND needed. 45 VDDA PWR 3.3V power for the PLL core. 46 GNDA PWR Ground pin for the PLL core. 47 VREF PWR Voltage reference for low power outputs. 48 CPUC_LF OUT Complementary clock of differential pair of low power CPU outputs. Free running during iamt. No 5ohm resistor to GND needed. 49 CPUT_LF OUT True clock of differential pair of low power CPU outputs. Free running during iamt. No 5ohm resistor to GND needed. 5 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 5 CPUC_L OUT Complementary clock of differential pair.8v pushpull CPU outputs. No 5ohm resistor to GND needed. 52 CPUT_L OUT True clock of differential pair.8v pushpull CPU outputs. No 5ohm resistor to GND needed. 53 GND PWR Ground pin. 54 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 55 SDATA I/O Data pin for SMBus circuitry, 5V tolerant. 56 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 57 X2 OUT Crystal output, Nominally 4.38MHz 58 X IN Crystal input, Nominally 4.38MHz. 59 GND PWR Ground pin. 6 REF OUT 4.38 MHz reference clock. 6 REF/FSLC/TEST_SEL I/O 4.38 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. /TEST_Sel: 3level latched input to enable test mode. Refer to Test Clarification Table 62 CPU_STOP# IN Stops all CPUCLK, except those set to be free running clocks 63 PCI/PCIEX_STOP# IN Stops all PCICLKs and PCIEXCLKs besides the freerunning clocks at logic level, when input low 64 PCICLK/REQ_SEL** I/O 3.3V PCI clock output / Latch select input pin. = PCIEXCLK, = PEREQ# 99 8/2/8 3

4 General Description ICS9LPR363 is a low power CK55compliant clock specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9LPR363 is driven with a 4.38MHz crystal. Block Diagram USB_48MHz X X2 XTAL Fixed PLL Frequency Dividers PCIeT_L9/DOTT_96MHzL PCIeC_L9/DOTC_96MHzL REF(:) SCLK SDATA FSLA FSLB FSLC PEREQ#(4:) CPU_STOP# PCI/PCIEX_STOP# ITP_EN REQ_SEL TEST_SEL TEST_MODE SELPCIEX_LCD# SELLCD_27# PWRSAVE# Vtt_Pwr_GD/PD# Control Logic PLL Array Programmable Frequency Divider Array STOP Logic CPUCLKT (:) CPUCLKC (:) CPUCLKT2_ITP/PCIEXT8 CPUCLKC2_ITP/PCIEXC8 PCICLK_F(5:4) PCICLK (3:) PCIEXT (7:) PCIEXC (7:) 27FIX/LCD_SSCGT/PCIEXT 27SS/LCD_SSCGT/PCIEXC SATACLKT SATACLKC Note:. VREF is not connected unless differential amplitude needs to be tuned Power Supply PIN NUMBER Description VDD,7 GND 2,6 3 PCICLK outputs 48MHz,96Mhz, LCDCLK, Fix Digital, Fix Analog 45 28, Master clock, CPU Analog 2, 29, 37 PCIEXT/C outputs 53 CPUT/C output 59 Xtal, REF 99 8/2/8 4

5 Differential Amplitude control using VREF. Rpullup: Connected between Vref and Vdd=3.3V; Rpulldown: Connected between Vref and GND Keep Rpullup=K ohm and variable Rpulldown to measure CPU and PCIEX Vtop Rpullup (ohm) Rpulldown (ohm) CPUT Vtop (mv) PCIEXT Vtop (mv) SATAT Vtop (mv) K K K K K K K K K K *Measurement based on Vtopavg **Test board trace impedance is 5ohms Vdd=3.3V Rpullup=K ohm DUT Vref Rpulldown is variable GND 99 8/2/8 5

6 Table : CPU/PCIEX Frequency Selection Table FS4 FS3 FSLC FSLB FSLA CPU PCI MHz PCIEX MHz MHz Spread % % Down % Down % Down % Down % Down % Down % Down % Down /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center /.25 Center 99 8/2/8 6

7 Table2: LCDCLK Spread and Frequency Selection Table SELDOT_27# Byte 9b7 SS3 Byte9b6 SS2 Byte 9b5 SS Byte 9b4 SS Pin 7/8 MHz Spread % 27. +/.25 Center 27. +/.5 Center 27. +/.75 Center 27. +/. Center 27. +/.25 Center 27. +/.5 Center 27. +/.75 Center 27. +/2 Center Down 27. Down Down Down Down Down Down Down 96. +/.5 Center 96. +/.25 Center 96. +/. Center 96. +/.8 Center 96. +/.6 Center 96. +/.5 Center 96. +/.4 Center 96. +/.3 Center Down Down Down Down Down Down 96. Down Down Table3: SATA Spread and Frequency Selection Table SEL_SATA Byte 6b3 Byte6b2 Pin 27/26 Spread SS3 SS2 MHz %..2 Down..3 Down..4 Down..5 Down 99 8/2/8 7

8 CPU Power Management Table PWRDWN# CPU_STOP# PCI_STOP# PEREQ# SMBus Register OE CPU CPU# CPU CPU# X Running Running Running Running X X X Low/2K Low Low/2K Low X X High Low High Low X X X Disable Low/2K Low Low/2K Low M Running Running Low/2K Low PCIe, LCD, DOT Power Management Table PWRDWN# CPU_STOP# PCI_STOP# PEREQ# PCIe/LCD PCIe#/LCD# PCIe/LCD PCIe#/LCD# DOT DOT# PCI / FreeRun PEREQ Selected X Running Running Running Running Running Running X X X Low/2K Low Low/2K Low Low/2K Low X X Running Running High Low Running Running X X Running Running Low/2K Low Running Running X X X Disable Low/2K Low Low/2K Low Low/2K Low M Low/2K Low Low/2K Low Low/2K Low Singledended Power Management Table SMBus PWRDWN# CPU_STOP# PCI_STOP# PEREQ# Register OE PCIF/PCI PCIF/PCI USB REF Freerun X X Running Running Running Running X X X Low Low Low Low X X Running Low Running Running X X X Disable Low Low Low Low M Low Low Low Low 99 8/2/8 8

9 General I 2 C serial interface information for the ICS9LPR363 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X ICS clock sends Byte through byte X (if X (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N Byte N + X P stop bit X Byte ICS (Slave/Receiver) ACK ACK ACK ACK ACK Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite ACK Beginning Byte = N ACK RT Repeat start Slave Address D3 (H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte N P Not acknowledge stop bit Byte N + X 99 8/2/8 9

10 I2C Table: Output Control Register Byte Name Control Function Type Bit 7 CPUCLK2_ITP/PCIEX8 Output RW Disable (HiZ) Bit 6 PCIEX7 Output RW Disable (HiZ) Bit 5 PCIEX5 Output RW Disable (HiZ) Bit 4 PCIEX4 Output RW Disable (HiZ) Bit 3 PCIEX3 Output RW Disable (HiZ) Bit 2 PCIEX2 Output RW Disable (HiZ) Bit PCIEX Output RW Disable (HiZ) Bit LCD/PCIEX Output RW Disable (HiZ) I2C Table: Output Control Register Byte Name Control Function Type Bit 7 PCICLK_2 Output RW Disable Bit 6 PCIEX9/DOT_96MHz Output RW Disable (HiZ) Bit 5 USB_48MHz Output RW Disable Bit 4 REF Output RW Disable Bit 3 PCIEX6 Output RW Disable (HiZ) Bit 2 CPUCLK_ Output RW Disable (HiZ) Bit CPUCLK_ Output RW Disable (HiZ) Bit Spread Spectrum Mode (CPU, PCIEX, PCIF, PCI) Spread Control for PLL RW SPREAD OFF SPREAD ON I2C Table: Output Control Register Byte 2 Name Control Function Type Bit 7 PCICLK Output RW Disable Bit 6 PCICLK Output RW Disable Bit 5 PCICLK_F5 Output RW Disable Bit 4 PCICLK_F4 Output RW Disable Bit 3 PCICLK3 Output RW Disable Bit 2 27MHz (Fixed) Output RW Disable Bit 27MHz (SS) Output RW Disable Bit SATACLK Output RW Disable (HiZ) I2C Table: Output Control Register Byte 3 Name Control Function Type Bit 7 PCIEX6 RW FreeRunning Bit 6 PCIEX5 RW FreeRunning Bit 5 PCIEX4 RW FreeRunning Bit 4 SATACLK Allow assertion of PCI_STOP# or setting of RW FreeRunning PCI_STOP control bit in I2C register to stop Bit 3 PCIEX3 RW FreeRunning PCIEX clocks. Bit 2 PCIEX2 RW FreeRunning Bit PCIEX RW FreeRunning Bit PCIEX RW FreeRunning I2C Table: Output Control Register Byte 4 Name Control Function Bit 7 PCIEX7 FreeRunning Control RW FreeRunning Bit 6 PCIEX9 FreeRunning Control RW FreeRunning Bit 5 PCIEX8 FreeRunning Control RW FreeRunning Bit 4 PCICLK_F5 Allow assertion of PCI_STOP# or setting of RW FreeRunning PCI_STOP control bit in SMBus register to stop Bit 3 PCICLK_F4 PCI clocks. RW FreeRunning Bit 2 CPUCLK_2/ITP RW FreeRunning Allow assertion of CPU_STOP# to stop CPU Bit CPUCLK_ RW FreeRunning clocks. Bit CPUCLK_ RW FreeRunning I2C Table: Output Control Register Byte 5 Name Control Function Bit 7 Reserved Reserved RW Bit 6 PCICLK Strength Control RW x 2x Bit 5 Reserved Reserved RW Bit 4 Reserved Reserved RW Bit 3 Reserved Reserved RW Bit 2 PCICLK Strength Control RW x 2x Bit Reserved Reserved RW Bit Reserved Reserved RW 99 8/2/8

11 I2C Table: Frequency Select Register Byte 6 Name Control Function Type Bit 7 PWRSAVE PWR_SAVE programming RW IIC PWR_SAVE programming Bit 6 FS4 Frequency Select bit RW See Table : Frequency Selection Table Bit 5 FS3 Frequency Select bit RW Bit 4 REF STRENGTH Strength Prog RW X 2X Bit 3 PCI/SRC_STOP# Stop all PCI and SRC clocks RW Outputs Stopped Outputs Active Bit 2 FSL_C Frequency Select bit RW latch Bit FSL_B Frequency Select bit RW See Table : Frequency Selection Table latch Bit FSL_A Frequency Select bit RW latch I2C Table: Revision and Vendor ID Register Byte 7 Name Control Function Type Bit 7 RID3 R Bit 6 RID2 R Revision ID Bit 5 RID R Bit 4 RID R Bit 3 VID3 R Bit 2 VID2 R VENDOR ID Bit VID R = ICS Bit VID R I2C Table: PEREQ Control Register Byte 8 Name Control Function Type Bit 7 PEREQ2# Control PCIEX8 is controlled RW Not Controlled Controlled Bit 6 PEREQ2# Control PCIEX is controlled RW Not Controlled Controlled Bit 5 iamt_en Set via SMBus or dynamically by CK55 if detects dynamic M RW Legacy Mode iamt d Bit 4 PD_Restore If config saved, on deassert return to last known state else clear all config as if cold power on and RW Configuration Not Saved Configuration Saved go to latches open state Bit 3 Reserved Reserved RW Bit 2 PEREQ# Control SATACLK is controlled RW Not Controlled Controlled Bit PEREQ# Control PCIEX6 is controlled RW Not Controlled Controlled Bit PEREQ# Control PCIEX is controlled RW Not Controlled Controlled I2C Table: LCDCLK and M/N Control Register Byte 9 Name Control Function Type Bit 7 LCDCLK_SS3 Bit S3 RW Bit 6 LCDCLK_SS2 Bit S2 RW See LCDCLK_SS and 27Mhz Spread Select Table 2 Bit 5 LCDCLK_SS Bit S RW Bit 4 LCDCLK_SS Bit S RW Bit 3 *SEL SRC_LCDCLK# Selects SRC or LCD/27MHz on pins 7 and 8 R LCDCLK PCIEX latch Bit 2 REF Output RW Disable Bit LCDCLK_SS Spread SS RW OFF ON Bit M/N PLL M/N Programming RW Disable I2C Table: Byte Count Register Byte Name Control Function Type Bit 7 Reserved Reserved RW X Bit 6 Reserved Reserved RW X Bit 5 Reserved Reserved RW X Bit 4 BC4 RW Bit 3 BC3 RW Writing to this register will configure how many bytes will be Bit 2 BC2 Byte Count Programming b(7:) RW read back, default is 5 = 2 Bytes. Bit BC RW Bit BC RW I 2 C Table: PLL Frequency Control Register Byte Name Control Function Type Bit 7 N Div8 N Divider Prog bit 8 RW X Bit 6 N Div 9 N Divider Prog bit 9 RW X Bit 5 M Div5 RW The decimal representation of M and N Divier in Byte and X Bit 4 M Div4 RW 2 will configure the VCO frequency. Default at power up = X Bit 3 M Div3 RW latchin or Byte Rom table. VCO Frequency = 4.38 x X M Divider Programming bits Bit 2 M Div2 RW [NDiv(9:)+8] / [MDiv(5:)+2] X Bit M Div RW X Bit M Div RW X 99 8/2/8

12 I 2 C Table: PLL Frequency Control Register Byte 2 Name Control Function Type Bit 7 N Div7 RW X Bit 6 N Div6 RW X Bit 5 N Div5 RW The decimal representation of M and N Divier in Byte and X Bit 4 N Div4 RW 2 will configure the VCO frequency. Default at power up = X N Divider Programming b(8:) Bit 3 N Div3 RW latchin or Byte Rom table. VCO Frequency = 4.38 x X Bit 2 N Div2 RW [NDiv(9:)+8] / [MDiv(5:)+2] X Bit N Div RW X Bit N Div RW X I 2 C Table: PLL Spread Spectrum Control Register Byte 3 Name Control Function Type Bit 7 SSP7 RW X Bit 6 SSP6 RW X Bit 5 SSP5 RW X Bit 4 SSP4 RW These Spread Spectrum bits in Byte 3 and 4 will program X Spread Spectrum Programming bit(7:) Bit 3 SSP3 RW the spread percentage of PLL X Bit 2 SSP2 RW X Bit SSP RW X Bit SSP RW X I 2 C Table: PLL Spread Spectrum Control Register Byte 4 Name Control Function Type Bit 7 Reserved Reserved R Bit 6 SSP4 RW X Bit 5 SSP3 RW X Bit 4 SSP2 RW X These Spread Spectrum bits in Byte 3 and 4 will program Bit 3 SSP Spread Spectrum Programming bit(4:8) RW X the spread percentage of PLL Bit 2 SSP RW X Bit SSP9 RW X Bit SSP8 RW X I2C Table: PEREQ Control Register Byte 5 Name Control Function Type Bit 7 PEREQ4# Control PCIEX7 is controlled RW Not Controlled Controlled Bit 6 PEREQ4# Control PCIEX5 is controlled RW Not Controlled Controlled Bit 5 PEREQ4# Control PCIEX3 is controlled RW Not Controlled Controlled Bit 4 Reserved Reserved RW Bit 3 Reserved Reserved RW Bit 2 Reserved Reserved RW Bit PEREQ3# Control PCIEX4 is controlled RW Not Controlled Controlled Bit PEREQ3# Control PCIEX2 is controlled RW Not Controlled Controlled I2C Table: SATACLK Control Register Byte 6 Name Control Function Type Bit 7 SEL_SATA SATACLK Spread Control RW PCIEX PLL SATA PLL Bit 6 SEL_LCD(27#) Select LCD or 27MHz for pins 7 and 8 RW 27MHz/PCIEX9 LCDCLK/DOT96 latch Bit 5 PCIEX source PCIEX comes from RW PCIEX PLL SATA PLL Bit 4 SATA SS ENABLE SPREAD ENABLE SATA PLL RW OFF ON Bit 3 SATA_SS Bit S RW See SATA_SS Frequency Select Table 3 Bit 2 SATA_SS Bit S RW Bit PCI source PCI comes from RW PCIEX PLL SATA PLL Bit PCICLK2 Strength Control RW x 2x I 2 C Table: PLL2 Frequency Control Register Byte 7 Name Control Function Type Bit 7 N Div8 N Divider Prog bit 8 RW X Bit 6 N Div9 N Divider Prog bit 9 RW X Bit 5 M Div5 RW The decimal representation of M and N Divider in Byte 7 X Bit 4 M Div4 RW and 8 will configure the VCO frequency. Default at power X Bit 3 M Div3 RW up = Byte Rom table. VCO Frequency = 4.38 x X M Divider Programming bits Bit 2 M Div2 RW [NDiv(9:)+8] / [MDiv(5:)+2] X Bit M Div RW X Bit M Div RW X 99 8/2/8 2

13 I 2 C Table: PLL2 Frequency Control Register Byte 8 Name Control Function Type Bit 7 N Div7 R X Bit 6 N Div6 RW X Bit 5 N Div5 RW The decimal representation of M and N Divider in Byte 7 X Bit 4 N Div4 RW and 8 will configure the VCO frequency. Default at power X N Divider Programming b(8:) Bit 3 N Div3 RW up = Byte Rom table. VCO Frequency = 4.38 x X Bit 2 N Div2 RW [NDiv(9:)+8] / [MDiv(5:)+2] X Bit N Div RW X Bit N Div RW X I2C Table: PLL 2 Spread Spectrum Control Register Byte 9 Name Control Function Type Bit 7 SSP7 RW X Bit 6 SSP6 RW X Bit 5 SSP5 RW X These Spread Spectrum bits in Byte 9 and 2 will program Bit 4 SSP4 RW X Spread Spectrum Programming b(7:) the spread pecentage. It is recommended to use ICS Bit 3 SSP3 RW X Spread % table for spread programming. Bit 2 SSP2 RW X Bit SSP RW X Bit SSP RW X I2C Table: PLL 2 Spread Spectrum Control Register Byte 2 Name Control Function Type Bit 7 Reserved Reserved RW Bit 6 SSP4 RW X Bit 5 SSP3 RW X These Spread Spectrum bits in Byte 9 and 2 will program Bit 4 SSP2 RW X the spread pecentage. It is recommended to use ICS Bit 3 SSP Spread Spectrum Programming b(4:8) RW X Spread % table for spread programming. Bit 2 SSP RW X Bit SSP9 RW X Bit SSP8 RW X 99 8/2/8 3

14 Test Clarification Table Comments Powerup w/ TEST_SEL = to enter test mode Cycle power to disable test mode FSLC./TEST_SEL >3level latched input If powerup w/ V>.4V then use TEST_SEL If powerup w/ V<.4V then use FSLC FSLB/TEST_MODE >low Vth input TEST_MODE is a real time input HW FSLC/ TEST_SEL HW PIN FSLB/ TEST_MODE HW PIN OUTPUT <.4V X NORMAL >.4V HIZ >.4V REF/N 99 8/2/8 4

15 Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Maximum Supply Voltage VDDxxx Supply Voltage 4.6 V,3 Maximum Input Voltage V IH 3.3V LVCMOS Inputs 4.6 V,3,4 Minimum Input Voltage V IL Any Input GND.5 V,3 Storage Temperature Ts 65 5 C,3 Case Temperature Tcase 5 C,3 Input ESD protection ESD prot Human Body Model 2 V,3 Guaranteed by design and characterization, not % tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 4.388MHz to meet ppm frequency accuracy on PLL outputs. 3 Operation under these conditions is neither implied, nor guaranteed. 4 Maximum input voltage is not to exceed VDD Electrical Characteristics Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Ambient Operating Temp Tambient 7 C Supply Voltage VDDxxx Supply Voltage V Input High Voltage V IHSE Singleended inputs 2 V DD +.3 V Input Low Voltage V ILSE Singleended inputs V SS.3.8 V Input Leakage Current I IN V IN = V DD, V IN = GND 5 5 ua Inputs with pull or pull down resistors Input Leakage Current I INRES V IN = V DD, V IN = GND 2 2 ua Output High Voltage V OHSE Singleended outputs, I OH = ma 2.4 V Output Low Voltage V OLSE Singleended outputs, I OL = ma.4 V Output High Voltage V OHDIF Differential Outputs, I OH = TBD ma V Output Low Voltage V OLDIF Differential Outputs, I OL = TBD ma.4 V Low Threshold Input High Voltage V IH_FS 3.3 V +/5%.7 V DD +.3 V Low Threshold Input Low Voltage V IL_FS 3.3 V +/5% V SS.3.35 V Operating Supply Current I DD3.3OP Full Active, C L = Full load; TBD ma iamt Mode Current I DDiAMT TBD ma Powerdown Current I DDPD TBD ma Input Frequency F i V DD = 3.3 V TBD MHz 2 Pin Inductance L pin 7 nh C IN Logic Inputs.5 5 pf Input Capacitance C OUT Output pin capacitance 6 pf C INX X & X2 pins TBD pf From VDD PowerUp or deassertion of PD to Clk Stabilization T STAB st clock.8 ms SRC output enable after Tdrive_SRC T DRSRC PCI_STOP# deassertion 5 ns Differential output enable after Tdrive_PD T DRPD PD deassertion 3 us CPU output enable after Tdrive_CPU T DRSRC PCI_STOP# deassertion ns Tfall_PD T FALL Fall/rise time of PD, PCI_STOP# and 5 ns Trise_PD T RISE CPU_STOP# inputs 5 ns SMBus Voltage V DD V Lowlevel Output Voltage V I PULLUP.4 V Current sinking at V OLSMB =.4 V I PULLUP SMB Data Pin 4 ma SCLK/SDATA (Max VIL.5) to T Clock/Data Rise Time RI2C (Min VIH +.5) ns SCLK/SDATA (Min VIH +.5) to T Clock/Data Fall Time FI2C (Max VIL.5) 3 ns Maximum SMBus Operating Frequency F SMBUS khz Spread Spectrum Modulation Frequency f SSMOD Triangular Modulation 3 33 khz Guaranteed by design and characterization, not % tested in production. 99 8/2/8 5

16 AC Electrical Characteristics Low Power Differential (CPUCLK, SATACLK, PCIEX, DOT96Mhz) Outputs PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Rising Edge Slew Rate t SLR Differential Measurement V/ns,2 Falling Edge Slew Rate t FLR Differential Measurement V/ns,2 Slew Rate Variation t SLVAR Singleended Measurement 2 % Maximum Output Voltage V HIGH Includes overshoot 5 mv Minimum Output Voltage V LOW Includes undershoot 3 mv Differential Voltage Swing V SWING Differential Measurement 3 mv Crossing Point Voltage V XABS Singleended Measurement 3 55 mv,3,4 Crossing Point Variation V XABSVAR Singleended Measurement 4 mv,3,5 Duty Cycle D CYC Differential Measurement % CPU Jitter Cycle to Cycle CPUJ C2C Differential Measurement 85 ps SRC Jitter Cycle to Cycle SRCJ C2C Differential Measurement 25 ps DOT Jitter Cycle to Cycle DOTJ C2C Differential Measurement 25 ps CPU[:] Skew CPU SKEW Differential Measurement ps CPU[2_ITP:] Skew CPU SKEW2 Differential Measurement 5 ps SRC[:] Skew SRC SKEW Differential Measurement TBD ps Guaranteed by design and characterization, not % tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. Electrical Characteristics PCICLK/PCICLK_F PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Long Accuracy ppm see Tperiod minmax values ppm,2 Clock period T period 33.33MHz output nominal 3.9 ns MHz output spread ns 2 Absolute min/max period T abs 33.33MHz output nominal/spread ns 2 Output High Voltage V OH I OH = ma 2.4 V Output Low Voltage V OL I OL = ma.4 V Output High Current I OH V =. V 33 ma V = 3.35 V 33 ma Output Low Current I OL V MIN =.95 V 3 ma V MAX =.4 V 38 ma Rising Edge Slew Rate t SLR Measured from.8 to 2. V 4 V/ns Falling Edge Slew Rate t FLR Measured from 2. to.8 V 4 V/ns Duty Cycle d t V T =.5 V % Skew t skew V T =.5 V TBD ps Jitter, Cycle to cycle t jcyccyc V T =.5 V 5 ps Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 99 8/2/8 6

17 Electrical Characteristics USB48MHz PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Long Accuracy ppm see Tperiod minmax values ppm,2 Clock period T period 48.MHz output nominal ns 2 Absolute min/max period T abs 48.MHz output nominal ns 2 Output High Voltage V OH I OH = ma 2.4 V Output Low Voltage V OL I OL = ma.4 V Output High Current I OH V =. V 29 ma V = 3.35 V 23 ma Output Low Current I OL V MIN =.95 V 29 ma V MAX =.4 V 27 ma Rising Edge Slew Rate t SLR Measured from.8 to 2. V 2 V/ns Falling Edge Slew Rate t FLR Measured from 2. to.8 V 2 V/ns Duty Cycle d t V T =.5 V % Jitter, Cycle to cycle t jcyccyc V T =.5 V 35 ps Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz Intentional PCI Clock to Clock Delay 2 ps nominal steps PCI_ PCI_ PCI_2 PCI_3 PCI_F4 PCI_F5.ns Electrical Characteristics 27MHz PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod minmax values 5 5,2 ppm 5 5,2,3 Clock period T period 27.MHz output nominal ns 2 Output High Voltage V OH I OH = ma V Output Low Voltage V OL I OL = ma.5.55 V Output High Current Output Low Current I OH I OL V =. V ma V = 3.35 V 23 ma V MIN =.95 V ma V MAX =.4 V ma Edge Rate t slewr/f Rising/Falling edge rate V/ns Rise Time t r V OL =.4 V, V OH = 2.4 V ns Fall Time t f V OH = 2.4 V, V OL =.4 V ns Duty Cycle d t V T =.5 V % t ltj Long Term (us) 5 8 ps Jitter t jpkpk ps t jcyccyc V T =.5 V 7 5 ps *TA = 7 C; Supply Voltage VDD = 3.3 V +/5%, CL = 2 pf with Rs = 7Ω Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 3 At nominal voltage and temperature 99 8/2/8 7

18 Electrical Characteristics REF4.38MHz PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Long Accuracy ppm see Tperiod minmax values ppm,2 Clock period T period 4.38MHz output nominal ns 2 Absolute min/max period T abs 4.38MHz output nominal ns 2 Output High Voltage V OH I OH = ma 2.4 V Output Low Voltage V OL I OL = ma.4 V V =. V, Output High Current I OH V = 3.35 V ma V Output Low Current I =.95 V, OL V =.4 V 3 38 ma Rising Edge Slew Rate t SLR Measured from.8 to 2. V 4 V/ns Falling Edge Slew Rate t FLR Measured from 2. to.8 V 4 V/ns Duty Cycle d t V T =.5 V % Jitter t jcyccyc V T =.5 V ps Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 99 8/2/8 8

19 INDEX AREA N 2 D E E c α L 6. mm. Body,.5 mm. Pitch TSSOP (24 mil) (2 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A.2.47 A A b c D E SEE VARIATIONS 8. BASIC SEE VARIATIONS.39 BASIC E e.5 BASIC.2 BASIC L N SEE VARIATIONS SEE VARIATIONS α 8 8 aaa..4 A2 A A C VARIATIONS D mm. D (inch) N MIN MAX MIN MAX e b SEATING PLANE Reference Doc.: JEDEC Publication 95, MO53 aaa C 39 Ordering Information Example: 9LPR363yGLFT XXXX y G LF T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type 99 8/2/8 9

20 99 8/2/8 2

Not recommended for new designs

Not recommended for new designs Eight Output Differential Buffer for PCI-Express Recommended Application: DB800 Intel Yellow Cover part with PCI-Express support. Output Features: 8-0.7V current-mode differential output pairs Supports