November 11, 2009 Chang Kim ( 김창식 )

Transcription

1 Test Cost Challenges November 11, 2009 Chang Kim ( 김창식 ) 1

2 2 Where we are!!!

3 Number of Die per wafer exponentially increasing!! Bigger Wafer Diameter 150mm 200mm 300mm 450mm Moore s Law 32nm process Technology Ready 3

4 History of DRAM Price per Megabit (Source: DQ) DRAM has maintained a 32% average reduction per year in Price per Megabit, over 34 years! Over four years, this is approximately a 5x reduction in price per Megabit 4

5 New Trend has been increasing complexity TSV Module MCP SOC + Memory + Analog POP SIP 5

6 Higher Speed, Higher Density, More Core Higher Density Core #1 Core #2 RF GDDR5 Higher Speed Core #3 Multi Core 6

7 Known Good Die TSV Module MCP KGD required Speed, Functionality, Reliability POP SIP It s a dream!? 7

8 Known Good Die TSV Module MCP but still MGD.. Maybe Good Die? POP SIP IDEA!!! 8

9 Overall ATE Market ATE TAM History - Worldwide Revenue ($M) 7,000 6,574 6,000 5,000 5,232 Memory ATE TAM 5,136 SOC ATE TAM 4,000 4,233 4, ,831 ATE TAM 3,430 3,000 3,074 2,603 2,348 2,000 Economic Crisis i 1,000 IT Bubble

10 Solution for Test COST Higher Parallelism Concurrent Protocol Aware Per-Pin Pi PMU Single Platform 10

11 History of Multi Parallel Testing DRAM SOC 64-site 256-site 512-site 128-site 2 or 4-site 16-site 32-site 64-site 8-site Multi-site capability is the key strategy to achieve low cost of test Test technology has been aligned to high site count parallel test strategy 11

12 How to achieve Higher Parallelism IBC Internal Bit Compress SPC Small Pin Count BOST Build off self-test Today Memory >512 site DFT Design for Testability BIST Built-in self-test Channel Sharing TIU Test Interface Unit SOC >32 site ATE 12

13 ATE Requirement for Higher Parallelism New Higher Density Options for higher-site parallel Higher Performance for new technology Track Serial Data Rates -PCIe, SATA Increase Port Density Digital Channels Track HS DRAM Data Rates DDR2 DDR3/4 GDDR5 Increase Digital Pin Density. Track Mobile DDR Rates. Protocol Aware features Analog Channels Track converter resolution and SNR Combine Audio, Baseband, Video capabilities Increase source and digitizer density Higher Density Power Supplies for Parallel Memory and SOC Test DPS Channels Higher Density DC (Per Pin PMU) for Integrated Power Management Functions 13

14 Solution for Test COST Higher Parallelism Concurrent Protocol Aware Per-Pin Pi PMU Single Platform 14

15 Concurrent Testing- Device-Centric Test Time Reduction Parallel test execution of independent functional cores in the device DUT Core #1 Core #2 Core #3 *Device must be designed with independent cores ow Test Fl Serialized Flow Core #1 Tests Core #2 Tests s Core #3 Tests 2 Levels Concurrency Core #1 Tests Core #2 Tests re 3 sts Co #3 Tes 3 Levels Concurrency Core #1 Tests Core #2 Tests Cor re #3 Tes sts Etc Benefits: Reduce COT via parallel test of cores within a SOC or dies within a SIP Characterize the operation of cores running simultaneously Reduce Time to Market via re-use of modular test programs 15

16 Concurrent Testing - Independent Resources Per-Core Tester Slice per-core Environment DC Instruments 1900MHz 1.536MHz DC Instruments Digital Instruments AC Instruments Microwave Transceiver PLL Audio Converters AC Instruments Digital Instruments DSP DC Instruments 9.5MHz PMIC DSP MCU Memory I/F DDR Interface 266MHz DSP Digital Instruments Digital Instruments Advantages Independent d test t development of each core Independent timing, signals, resources, processing Computer Synchronous phase start of clocks and patterns Advantages Able to synchronize across tests Able to support concurrency with shared device resources 16 *

17 Solution for Test COST Higher Parallelism Concurrent Protocol Aware Per-Pin Pi PMU Single Platform 17

18 Chip Design Evolution Time Design T CPU Complex SOC Mobile and Baseaband Increasing Chip complexity 18

19 Async Chip Creates Non-Deterministic Test G DDR 1.6 6Gbps DDR Interface PCI Express 16 Lanes 2.5Gbps rface PCIE Inte Graphics Processor TDMS Inte erface TMDS/HMDI 3 Pairs 1.6Gbps PCI Express Graphics Data Idle Graphics Data Idle Graphics Data DDR Interface RD Idle WR RD WR Idle WR Idle TDMS Interface Disp Data Disp Data Disp Data Disp Data Idle Disp Data 19

20 Async Chip Creates Non-Deterministic Test Protoco ol Synchroniz zation & Com mmunication Protocol Aware ATE PCI Express 16 Lanes 2.5Gbps Protocol Synchronization & Communication PCIE Interf face GDD DR 1.6Gb bps DDR Interface Graphics Processor TDMS Inter rface TMDS/HMDI 3 Pairs 1.6Gbps Protoco l Synchroniza ation & Comm munication Stored Response ATE Execute fixed pass/fail vectors Slave DUT to tester Convert Design Information to Tester Language Protocol Level ATE Interact with DUT using standard protocols (PCI-E, I2C, USB, etc) Adapt tester to DUT Use RTL level commands directly on tester 20

21 Protocol Aware attributes of a new solution Accommodate Functional Test: less 200DPM Low test cost Fits the normal 5-10sec test model No massive infrastructure changes Accommodate Non-Determinism i Minimum: Idle deletion Preferred: Non-Deterministic Sequence Allow the device to operate in mission i mode Reduce Time to Market User operates at transaction level Operates more like bench fixture Test time reduced: Several Months Weeks Memory solution Design verification through variable frequency for Mobile solution Reusable application testing instead of SLT Just Do It 21

22 Solution for Test COST Higher Parallelism Concurrent Protocol Aware Per-Pin Pi PMU Single Platform 22

23 DC Test Time is Becoming More Critical Problem: As DRAM makers drive test costs down by reducing test time, DC test becomes es a larger percentage of test time 60.0% 50.0% Big Cost of Test Issue! % DC Test Tim me 40.0% 30.0% 20.0% TT Down Historically not a big problem Major trends are parallel-up and test time-down. 10.0% 0.0% Test Time (sec) 23

24 DC Test Cost Solution DC Test Time is reduced drastically with Today s solution fast with no loss of test coverage or reduced quality. 60.0% 50.0% 0% % DC Test Time 40.0% 30.0% 20.0% 0% Cost of Test Shared PMU Cost of Test Advantage: + DC Test time is very short + No loss in DC test coverage + Short test time at 10.0% Per-Pin PMU higher parallelism 0.0% Test Time (sec) 24

25 Solution for Test COST Higher Parallelism Concurrent Protocol Aware Per-Pin Pi PMU Single Platform 25

26 Single platform Trend FLASH LPDDR GDDR DDR3 Power FLASH DRAM Power SOC RF SOC RF IMAGE IMAGE Multi Platform Optimizing current market requirement Easy concept Short life cycle time Single Platform Think next generation Less Investment Long life cycle time (Reuse) 26

27 Conclusion - What is the cost saving way! Time to Market Test Coverage Pi Price Upgrade Cost Engineering tools Accuracy Test Time Utilization # of Parallel Life cycle BOST SLT ( 실장 ) ATE ATE still provides cost effective way and huge benefit!!! 27

28 Conclusion What is test? Cost! Cost down 요구는계속증가 ATE has created new technology and solution. o Higher Parallelism o Concurrent o Protocol Aware o Per-Pin PMU o Single Platform ATE keeps trying to find out a breakthrough! 28

29 29 Thank you!