C8051F360/1/2/3/4/5/6/7/8/9

Transcription

1 Mixed Signal ISP Flash MCU Family Analog Peripherals - 10-Bit ADC ( F360/1/2/6/7/8/9 only) Up to 200 ksps Up to 21 external single-ended or differential inputs VREF from internal VREF, external pin or V DD Internal or external start of conversion source Built-in temperature sensor - 10-Bit Current Output DAC ( F360/1/2/6/7/8/9 only) - Two Comparators Programmable hysteresis and response time Configurable as interrupt or reset source Low current (TBD µa) - Brown-out detector and POR Circuitry On-Chip Debug - On-chip debug circuitry facilitates full speed, nonintrusive in-system debug (no emulator required) - Provides breakpoints, single stepping, inspect/modify memory and registers - Superior performance to emulation systems using ICE-chips, target pods, and sockets - Low cost, complete development kit Supply Voltage - Range: V (50 MIPS) V (100 MIPS) (See Table 3.1) - Power saving suspend and shutdown modes High Speed 8051 µc Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks MIPS or 50 MIPS throughput with on-chip PLL - Expanded interrupt handler - 2-cycle 16 x 16 MAC engine Memory bytes internal data RAM ( ) - 32 kb ( F360/1/2/3/4/5/6/7) or 16 kb ( F368/9) Flash; In-system programmable in 1024-byte Sectors 1024 bytes are reserved in the 32 kb devices Digital Peripherals - up to 39 Port I/O; All 5 V tolerant with high sink current - Hardware enhanced UART, SMBus, and enhanced SPI serial ports - Four general purpose 16-bit counter/timers - 16-Bit programmable counter array (PCA) with six capture/compare modules - Real time clock mode using PCA or timer and external clock source - External Memory Interface (EMIF) Clock Sources - Two internal oscillators: 24.5 MHz with ±2% accuracy supports crystal-less UART operation 80/40/20/10 khz low frequency, low power - Flexible PLL technology - External oscillator: Crystal, RC, C, or clock (1 or 2 pin modes) - Can switch between clock sources on-the-fly; useful in power saving modes Packages - 48-pin TQFP (C8051F360/3) - 32-pin LQFP (C8051F361/4/6/8) - 28-pin QFN (C8051F362/5/7/9) Temperature Range: 40 to +85 C (See Table 3.1) A M U X ANALOG PERIPHERALS VOLTAGE COMPARATORS 10-bit 200 ksps ADC F360/1/2/6/7/8/9 only TEMP SENSOR 10-bit Current DAC UART SMBus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 DIGITAL I/O CROSSBAR 48-pin only External Memory Interface Port 0 Port 1 Port 2 Port 3 Port 3 Port 4 HIGH-SPEED CONTROLLER CORE WDT 16 x 16 MAC 8051 CPU (100 or 50 MIPS) 1024 B SRAM POR FLEXIBLE INTERRUPTS DEBUG CIRCUITRY Internal Oscillator / LFO / PLL 32/16 KB ISP FLASH Rev /07 Copyright 2007 by Silicon Laboratories C8051F36x This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

2 2 Rev. 0.2

3 Table of Contents C8051F360/1/2/3/4/5/6/7/8/9 1. System Overview CIP-51 Microcontroller Core Fully 8051 Compatible Improved Throughput Additional Features On-Chip Memory On-Chip Debug Circuitry Programmable Digital I/O and Crossbar Serial Ports Programmable Counter Array Bit Analog to Digital Converter Comparators bit Current Output DAC Absolute Maximum Ratings Global Electrical Characteristics Pinout and Package Definitions Bit ADC (ADC0, C8051F360/1/2/6/7/8/9) Analog Multiplexer Temperature Sensor Modes of Operation Starting a Conversion Tracking Modes Settling Time Requirements Programmable Window Detector Window Detector In Single-Ended Mode Window Detector In Differential Mode Bit Current Mode DAC (IDA0, C8051F360/1/2/6/7/8/9) IDA0 Output Scheduling Update Output On-Demand Update Output Based on Timer Overflow Update Output Based on CNVSTR Edge IDAC Output Mapping Voltage Reference (C8051F360/1/2/6/7/8/9) Comparators CIP-51 Microcontroller Performance Programming and Debugging Support Instruction Set Instruction and CPU Timing MOVX Instruction and Program Memory Memory Organization Program Memory Data Memory Rev

4 General Purpose Registers Bit Addressable Locations Stack Special Function Registers Register Descriptions Power Management Modes Idle Mode Stop Mode Suspend Mode Interrupt Handler MCU Interrupt Sources and Vectors Interrupt Priorities Interrupt Latency Interrupt Register Descriptions External Interrupts Multiply And Accumulate (MAC0) Special Function Registers Integer and Fractional Math Operating in Multiply and Accumulate Mode Operating in Multiply Only Mode Accumulator Shift Operations Rounding and Saturation Usage Examples Multiply and Accumulate Example Multiply Only Example MAC0 Accumulator Shift Example Reset Sources Power-On Reset Power-Fail Reset/VDD Monitor External Reset Missing Clock Detector Reset Comparator0 Reset PCA Watchdog Timer Reset Flash Error Reset Software Reset Flash Memory Programming the Flash Memory Flash Lock and Key Functions Erasing Flash Pages From Software Writing Flash Memory From Software Non-volatile Data Storage Security Options Summary of Flash Security Options Flash Write and Erase Guidelines VDD Maintenance and the VDD Monitor Rev. 0.2

5 PSWE Maintenance System Clock Flash Read Timing Branch Target Cache Cache and Prefetch Operation Cache and Prefetch Optimization External Data Memory Interface and On-Chip XRAM Accessing XRAM Bit MOVX Example Bit MOVX Example Configuring the External Memory Interface Port Configuration Multiplexed and Non-multiplexed Selection Multiplexed Configuration Non-multiplexed Configuration Memory Mode Selection Internal XRAM Only Split Mode without Bank Select Split Mode with Bank Select External Only Timing Non-multiplexed Mode Multiplexed Mode Oscillators Programmable Internal High-Frequency (H-F) Oscillator Internal Oscillator Suspend Mode Programmable Internal Low-Frequency (L-F) Oscillator Calibrating the Internal L-F Oscillator External Oscillator Drive Circuit System Clock Selection External Crystal Example External RC Example External Capacitor Example Phase-Locked Loop (PLL) PLL Input Clock and Pre-divider PLL Multiplication and Output Clock Powering on and Initializing the PLL Port Input/Output Priority Crossbar Decoder Port I/O Initialization General Purpose Port I/O SMBus Supporting Documents SMBus Configuration Rev

6 18.3.SMBus Operation Arbitration Clock Low Extension SCL Low Timeout SCL High (SMBus Free) Timeout Using the SMBus SMBus Configuration Register SMB0CN Control Register Data Register SMBus Transfer Modes Master Transmitter Mode Master Receiver Mode Slave Receiver Mode Slave Transmitter Mode SMBus Status Decoding UART Enhanced Baud Rate Generation Operational Modes Bit UART Bit UART Multiprocessor Communications Enhanced Serial Peripheral Interface (SPI0) Signal Descriptions Master Out, Slave In (MOSI) Master In, Slave Out (MISO) Serial Clock (SCK) Slave Select (NSS) SPI0 Master Mode Operation SPI0 Slave Mode Operation SPI0 Interrupt Sources Serial Clock Timing SPI Special Function Registers Timers Timer 0 and Timer Mode 0: 13-bit Counter/Timer Mode 1: 16-bit Counter/Timer Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) Timer bit Timer with Auto-Reload bit Timers with Auto-Reload Timer bit Timer with Auto-Reload bit Timers with Auto-Reload Rev. 0.2

7 22.Programmable Counter Array PCA Counter/Timer Capture/Compare Modules Edge-triggered Capture Mode Software Timer (Compare) Mode High Speed Output Mode Frequency Output Mode Bit Pulse Width Modulator Mode Bit Pulse Width Modulator Mode Watchdog Timer Mode Watchdog Timer Operation Watchdog Timer Usage Register Descriptions for PCA Revision Specific Behavior Revision Identification C2D Port Pin Requirements C2 Interface C2 Interface Registers C2 Pin Sharing Document Change List Contact Information Rev

8 NOTES: 8 Rev. 0.2

9 List of Figures C8051F360/1/2/3/4/5/6/7/8/9 1. System Overview Figure 1.1. C8051F360/3 Block Diagram...21 Figure 1.2. C8051F361/4/6/8 Block Diagram...22 Figure 1.3. C8051F362/5/7/9 Block Diagram...22 Figure 1.4. Comparison of Peak MCU Execution Speeds...23 Figure 1.5. On-Chip Clock and Reset...24 Figure 1.6. On-Board Memory Map...25 Figure 1.7. Development/In-System Debug Diagram...26 Figure 1.8. Digital Crossbar Diagram (Port 0 to Port 3)...27 Figure 1.9. PCA Block Diagram...28 Figure PCA Block Diagram...28 Figure Bit ADC Block Diagram...29 Figure Comparator0 Block Diagram...30 Figure Comparator1 Block Diagram...31 Figure IDA0 Functional Block Diagram Absolute Maximum Ratings 3. Global Electrical Characteristics 4. Pinout and Package Definitions Figure 4.1. TQFP-48 Pinout Diagram (Top View)...40 Figure 4.2. TQFP-48 Package Diagram...41 Figure 4.3. LQFP-32 Pinout Diagram (Top View)...42 Figure 4.4. LQFP-32 Package Diagram...43 Figure 4.5. QFN-28 Pinout Diagram (Top View)...44 Figure 4.6. QFN-28 Package Drawing...45 Figure 4.7. QFN-28 Solder Paste Recommendation...46 Figure 4.8. Typical QFN-28 Landing Diagram Bit ADC (ADC0, C8051F360/1/2/6/7/8/9) Figure 5.1. ADC0 Functional Block Diagram...49 Figure 5.2. Typical Temperature Sensor Transfer Function...51 Figure 5.3. Temperature Sensor Error with 1-Point Calibration...52 Figure Bit ADC Track and Conversion Example Timing...54 Figure 5.5. ADC0 Equivalent Input Circuits...55 Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data...62 Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data...62 Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data...63 Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data Bit Current Mode DAC (IDA0, C8051F360/1/2/6/7/8/9) Figure 6.1. IDA0 Functional Block Diagram...65 Figure 6.2. IDA0 Data Word Mapping Voltage Reference (C8051F360/1/2/6/7/8/9) Figure 7.1. Voltage Reference Functional Block Diagram Comparators Figure 8.1. Comparator0 Functional Block Diagram...73 Rev

10 Figure 8.2. Comparator1 Functional Block Diagram Figure 8.3. Comparator Hysteresis Plot CIP-51 Microcontroller Figure 9.1. CIP-51 Block Diagram Figure 9.2. Memory Map Figure 9.3. SFR Page Stack Figure 9.4. SFR Page Stack While Using SFR Page 0x0F To Access OSCICN Figure 9.5. SFR Page Stack After ADC0 Window Comparator Interrupt Occurs Figure 9.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC0 ISR. 94 Figure 9.7. SFR Page Stack Upon Return From PCA Interrupt Figure 9.8. SFR Page Stack Upon Return From ADC2 Window Interrupt Interrupt Handler 11. Multiply And Accumulate (MAC0) Figure MAC0 Block Diagram Figure Integer Mode Data Representation Figure Fractional Mode Data Representation Figure MAC0 Pipeline Reset Sources Figure Reset Sources Figure Power-On and VDD Monitor Reset Timing Flash Memory Figure Flash Program Memory Map Branch Target Cache Figure Branch Target Cache Data Flow Figure Branch Target Cache Organiztion Figure Cache Lock Operation External Data Memory Interface and On-Chip XRAM Figure Multiplexed Configuration Example Figure Non-multiplexed Configuration Example Figure EMIF Operating Modes Figure Non-multiplexed 16-bit MOVX Timing Figure Non-multiplexed 8-bit MOVX without Bank Select Timing Figure Non-multiplexed 8-bit MOVX with Bank Select Timing Figure Multiplexed 16-bit MOVX Timing Figure Multiplexed 8-bit MOVX without Bank Select Timing Figure Multiplexed 8-bit MOVX with Bank Select Timing Oscillators Figure Oscillator Diagram Figure khz External Crystal Example Figure PLL Block Diagram Port Input/Output Figure Port I/O Functional Block Diagram (Port 0 through Port 3) Figure Port I/O Cell Block Diagram Figure Crossbar Priority Decoder with No Pins Skipped Figure Crossbar Priority Decoder with Port Pins Skipped Rev. 0.2

11 18. SMBus Figure SMBus Block Diagram Figure Typical SMBus Configuration Figure SMBus Transaction Figure Typical SMBus SCL Generation Figure Typical Master Transmitter Sequence Figure Typical Master Receiver Sequence Figure Typical Slave Receiver Sequence Figure Typical Slave Transmitter Sequence UART0 Figure UART0 Block Diagram Figure UART0 Baud Rate Logic Figure UART Interconnect Diagram Figure Bit UART Timing Diagram Figure Bit UART Timing Diagram Figure UART Multi-Processor Mode Interconnect Diagram Enhanced Serial Peripheral Interface (SPI0) Figure SPI Block Diagram Figure Multiple-Master Mode Connection Diagram Figure Wire Single Master and 3-Wire Single Slave Mode Connection Diagram Figure Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram Figure Master Mode Data/Clock Timing Figure Slave Mode Data/Clock Timing (CKPHA = 0) Figure Slave Mode Data/Clock Timing (CKPHA = 1) Figure SPI Master Timing (CKPHA = 0) Figure SPI Master Timing (CKPHA = 1) Figure SPI Slave Timing (CKPHA = 0) Figure SPI Slave Timing (CKPHA = 1) Timers Figure T0 Mode 0 Block Diagram Figure T0 Mode 2 Block Diagram Figure T0 Mode 3 Block Diagram Figure Timer 2 16-Bit Mode Block Diagram Figure Timer 2 8-Bit Mode Block Diagram Figure Timer 3 16-Bit Mode Block Diagram Figure Timer 3 8-Bit Mode Block Diagram Programmable Counter Array Figure PCA Block Diagram Figure PCA Counter/Timer Block Diagram Figure PCA Interrupt Block Diagram Figure PCA Capture Mode Diagram Figure PCA Software Timer Mode Diagram Figure PCA High Speed Output Mode Diagram Rev

12 Figure PCA Frequency Output Mode Figure PCA 8-Bit PWM Mode Diagram Figure PCA 16-Bit PWM Mode Figure PCA Module 5 with Watchdog Timer Enabled Revision Specific Behavior Figure Device Package - TQFP Figure Device Package - LQFP Figure Device Package - QFN C2 Interface Figure Typical C2 Pin Sharing Rev. 0.2

13 List of Tables C8051F360/1/2/3/4/5/6/7/8/9 1. System Overview Table 1.1. Product Selection Guide Absolute Maximum Ratings 3. Global Electrical Characteristics Table 3.1. Index to Electrical Characteristics Tables Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F36x Table 4.2. TQFP-48 Package Dimensions Table 4.3. LQFP-32 Package Dimensions Table 4.4. QFN-28 Package Dimensions Bit ADC (ADC0, C8051F360/1/2/6/7/8/9) Bit Current Mode DAC (IDA0, C8051F360/1/2/6/7/8/9) 7. Voltage Reference (C8051F360/1/2/6/7/8/9) 8. Comparators 9. CIP-51 Microcontroller Table 9.1. CIP-51 Instruction Set Summary Table 9.2. Special Function Register (SFR) Memory Map Table 9.3. Special Function Registers Interrupt Handler Table Interrupt Summary Multiply And Accumulate (MAC0) Table MAC0 Rounding (MAC0SAT = 0) Reset Sources 13. Flash Memory Table Flash Security Summary Branch Target Cache 15. External Data Memory Interface and On-Chip XRAM Table EMIF Pinout (C8051F360/3) Table AC Parameters for External Memory Interface Oscillators Table PLL Lock Timing Characteristics Port Input/Output 18. SMBus Table SMBus Clock Source Selection Table Minimum SDA Setup and Hold Times Table Sources for Hardware Changes to SMB0CN Table SMBus Status Decoding UART0 Table Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Table Timer Settings for Standard Baud Rates Using an External 25.0 MHz Oscillator Table Timer Settings for Standard Baud Rates Rev

14 Using an External MHz Oscillator Table Timer Settings for Standard Baud Rates Using an External MHz Oscillator Table Timer Settings for Standard Baud Rates Using an External MHz Oscillator Table Timer Settings for Standard Baud Rates Using an External MHz Oscillator Enhanced Serial Peripheral Interface (SPI0) Table SPI Slave Timing Parameters Timers 22. Programmable Counter Array Table PCA Timebase Input Options Table PCA0CPM Register Settings for PCA Capture/Compare Modules Table Watchdog Timer Timeout Intervals Revision Specific Behavior 24. C2 Interface 14 Rev. 0.2

15 List of Registers C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select SFR Definition 5.3. ADC0CF: ADC0 Configuration SFR Definition 5.4. ADC0H: ADC0 Data Word MSB SFR Definition 5.5. ADC0L: ADC0 Data Word LSB SFR Definition 5.6. ADC0CN: ADC0 Control SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte SFR Definition ADC0LTL: ADC0 Less-Than Data Low Byte SFR Definition 6.1. IDA0CN: IDA0 Control SFR Definition 6.2. IDA0H: IDA0 Data Word MSB SFR Definition 6.3. IDA0L: IDA0 Data Word LSB SFR Definition 7.1. REF0CN: Reference Control SFR Definition 8.1. CPT0CN: Comparator0 Control SFR Definition 8.2. CPT0MX: Comparator0 MUX Selection SFR Definition 8.3. CPT0MD: Comparator0 Mode Selection SFR Definition 8.4. CPT1CN: Comparator1 Control SFR Definition 8.5. CPT1MX: Comparator1 MUX Selection SFR Definition 8.6. CPT1MD: Comparator1 Mode Selection SFR Definition 9.1. SFR0CN: SFR Page Control SFR Definition 9.2. SFRPAGE: SFR Page SFR Definition 9.3. SFRNEXT: SFR Next Register SFR Definition 9.4. SFRLAST: SFR Last Register SFR Definition 9.5. SP: Stack Pointer SFR Definition 9.6. DPL: Data Pointer Low Byte SFR Definition 9.7. DPH: Data Pointer High Byte SFR Definition 9.8. PSW: Program Status Word SFR Definition 9.9. ACC: Accumulator SFR Definition B: B Register SFR Definition PCON: Power Control SFR Definition IE: Interrupt Enable SFR Definition IP: Interrupt Priority SFR Definition EIE1: Extended Interrupt Enable SFR Definition EIP1: Extended Interrupt Priority SFR Definition EIE2: Extended Interrupt Enable SFR Definition EIP2: Extended Interrupt Priority SFR Definition IT01CF: INT0/INT1 Configuration SFR Definition MAC0CF: MAC0 Configuration SFR Definition MAC0STA: MAC0 Status SFR Definition MAC0AH: MAC0 A High Byte SFR Definition MAC0AL: MAC0 A Low Byte SFR Definition MAC0BH: MAC0 B High Byte Rev

16 SFR Definition MAC0BL: MAC0 B Low Byte SFR Definition MAC0ACC3: MAC0 Accumulator Byte SFR Definition MAC0ACC2: MAC0 Accumulator Byte SFR Definition MAC0ACC1: MAC0 Accumulator Byte SFR Definition MAC0ACC0: MAC0 Accumulator Byte SFR Definition MAC0OVR: MAC0 Accumulator Overflow SFR Definition MAC0RNDH: MAC0 Rounding Register High Byte SFR Definition MAC0RNDL: MAC0 Rounding Register Low Byte SFR Definition VDM0CN: VDD Monitor Control SFR Definition RSTSRC: Reset Source SFR Definition PSCTL: Program Store Read/Write Control SFR Definition FLKEY: Flash Lock and Key SFR Definition FLSCL: Flash Memory Control SFR Definition CCH0CN: Cache Control SFR Definition CCH0TN: Cache Tuning SFR Definition CCH0LC: Cache Lock Control SFR Definition CCH0MA: Cache Miss Accumulator SFR Definition FLSTAT: Flash Status SFR Definition EMI0CN: External Memory Interface Control SFR Definition EMI0CF: External Memory Configuration SFR Definition EMI0TC: External Memory Timing Control SFR Definition OSCICL: Internal Oscillator Calibration SFR Definition OSCICN: Internal Oscillator Control SFR Definition OSCLCN: Internal L-F Oscillator Control SFR Definition CLKSEL: System Clock Selection SFR Definition OSCXCN: External Oscillator Control SFR Definition PLL0CN: PLL Control SFR Definition PLL0DIV: PLL Pre-divider SFR Definition PLL0MUL: PLL Clock Scaler SFR Definition PLL0FLT: PLL Filter SFR Definition XBR0: Port I/O Crossbar Register SFR Definition XBR1: Port I/O Crossbar Register SFR Definition P0: Port SFR Definition P0MDIN: Port0 Input Mode SFR Definition P0MDOUT: Port0 Output Mode SFR Definition P0SKIP: Port0 Skip SFR Definition P0MAT: Port0 Match SFR Definition P0MASK: Port0 Mask SFR Definition P1: Port SFR Definition P1MDIN: Port1 Input Mode SFR Definition P1MDOUT: Port1 Output Mode SFR Definition P1SKIP: Port1 Skip SFR Definition P1MAT: Port1 Match SFR Definition P1MASK: Port1 Mask SFR Definition P2: Port Rev. 0.2

17 SFR Definition P2MDIN: Port2 Input Mode SFR Definition P2MDOUT: Port2 Output Mode SFR Definition P2SKIP: Port2 Skip SFR Definition P2MAT: Port2 Match SFR Definition P2MASK: Port2 Mask SFR Definition P3: Port SFR Definition P3MDIN: Port3 Input Mode SFR Definition P3MDOUT: Port3 Output Mode SFR Definition P3SKIP: Port3 Skip SFR Definition P4: Port SFR Definition P4MDOUT: Port4 Output Mode SFR Definition SMB0CF: SMBus Clock/Configuration SFR Definition SMB0CN: SMBus Control SFR Definition SMB0DAT: SMBus Data SFR Definition SCON0: Serial Port 0 Control SFR Definition SBUF0: Serial (UART0) Port Data Buffer SFR Definition SPI0CFG: SPI0 Configuration SFR Definition SPI0CN: SPI0 Control SFR Definition SPI0CKR: SPI0 Clock Rate SFR Definition SPI0DAT: SPI0 Data SFR Definition TCON: Timer Control SFR Definition TMOD: Timer Mode SFR Definition CKCON: Clock Control SFR Definition TL0: Timer 0 Low Byte SFR Definition TL1: Timer 1 Low Byte SFR Definition TH0: Timer 0 High Byte SFR Definition TH1: Timer 1 High Byte SFR Definition TMR2CN: Timer 2 Control SFR Definition TMR2RLL: Timer 2 Reload Register Low Byte SFR Definition TMR2RLH: Timer 2 Reload Register High Byte SFR Definition TMR2L: Timer 2 Low Byte SFR Definition TMR2H Timer 2 High Byte SFR Definition TMR3CN: Timer 3 Control SFR Definition TMR3RLL: Timer 3 Reload Register Low Byte SFR Definition TMR3RLH: Timer 3 Reload Register High Byte SFR Definition TMR3L: Timer 3 Low Byte SFR Definition TMR3H Timer 3 High Byte SFR Definition PCA0CN: PCA Control SFR Definition PCA0MD: PCA0 Mode SFR Definition PCA0CPMn: PCA0 Capture/Compare Mode SFR Definition PCA0L: PCA0 Counter/Timer Low Byte SFR Definition PCA0H: PCA0 Counter/Timer High Byte SFR Definition PCA0CPLn: PCA0 Capture Module Low Byte SFR Definition PCA0CPHn: PCA0 Capture Module High Byte C2 Register Definition C2ADD: C2 Address Rev

18 C2 Register Definition DEVICEID: C2 Device ID C2 Register Definition REVID: C2 Revision ID C2 Register Definition FPCTL: C2 Flash Programming Control C2 Register Definition FPDAT: C2 Flash Programming Data Rev. 0.2

19 1. System Overview C8051F360/1/2/3/4/5/6/7/8/9 C8051F36x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. High-speed pipelined 8051-compatible microcontroller core (up to 100 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) True 10-bit 200 ksps 16-channel single-ended/differential ADC with analog multiplexer 10-bit Current Output DAC 2-cycle 16 by 16 Multiply and Accumulate Engine Precision programmable 25 MHz internal oscillator Up to 32 kb of on-chip Flash memory 1024 bytes are reserved 1024 bytes of on-chip RAM External Data Memory Interface with 64 kb address space SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer function On-chip Power-On Reset, V DD Monitor, and Temperature Sensor Two on-chip Voltage Comparators up to 39 Port I/O (5 V tolerant) With on-chip Power-On Reset, V DD Monitor, Watchdog Timer, and clock oscillator, the C8051F36x devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 3.0 to 3.6 V (100 MIPS) operation or 2.7 to 3.6 V (50 MIPS) operation over the industrial temperature range ( 40 to +85 C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F36x devices are available in 48-pin TQFP packages, and C8051F36x devices are available in 32-pin LQFP and 28-pin QFN packages (also referred to as MLP or MLF packages). All package types are lead-free (RoHS compliant). See Table 1.1 for ordering part numbers. Block diagrams are included in Figure 1.1, Figure 1.2, and Figure 1.3. Rev

20 Table 1.1. Product Selection Guide Ordering Part Number MIPS (Peak) Flash Memory (kb) RAM (bytes) 2-cycle 16 by 16 MAC Calibrated Internal 24.5 MHz Oscillator Internal 80 khz Oscillator External Memory Interface SMBus/I 2 C Enhanced SPI UART Timers (16-bit) Programmable Counter Array Digital Port I/Os 10-bit 200ksps ADC 10-bit Current Output DAC Internal Voltage Reference Temperature Sensor Analog Comparators Lead-free (RoHS Compliant) Package C8051F360-GQ TQFP-48 C8051F361-GQ 1 90/ LQFP-32 C8051F362-GM 3 90/ QFN-28 C8051F363-GQ TQFP-48 C8051F364-GQ 1 90/ LQFP-32 C8051F365-GM 3 90/ QFN-28 C8051F366-GQ LQFP-32 C8051F367-GM QFN-28 C8051F368-GQ LQFP-32 C8051F369-GM QFN-28 Notes: 1. Pin compatible with the C8051F310-GQ. 2. Maximum speed is 90 MHz at V and 40 to 80 ºC or 100 MHz at V and 40 to 70 ºC. 3. Pin compatible with the C8051F311-GM. 20 Rev. 0.2

21 C2CK/RST VDD GND C2D Power-On Reset Supply Monitor Reset Power Net XTAL1 XTAL2 Debug / Programming Hardware CIP Controller Core 32/16 kb ISP FLASH Program Memory System Clock Setup External Oscillator Internal Oscillator 256 Byte RAM 1 kb XRAM 2-cycle 16 by 16 Multiply and Accumulate Clock Multiplier SFR Bus Port I/O Configuration Digital Peripherals UART0 Timers 0, 1, 2, 3 PCA/WDT SMBus SPI Crossbar Control External Memory Interface Control Address Data Priority Crossbar Decoder P0 / P4 P2 / P3 / P4 P1 Port 0 Drivers Port 1 Drivers Port 2 Drivers Port 3 Drivers Port 4 Drivers P0.0 P0.1/TX P0.2/RX P0.3/VREF P0.4/IDA0 P0.5/XTAL1 P0.6/XTAL2 P0.7/CNVSTR P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6/C2D Low Frequency Oscillator VREF VDD Analog Peripherals VREF 10-bit IDAC P4.4 CP0 CP1 2 Comparators bit 200 ksps ADC C8051F360 only A M U X AIN0 AIN16 VDD Temp Sensor Figure 1.1. C8051F360/3 Block Diagram Rev

22 C2CK/RST VDD GND C2D Power-On Reset Supply Monitor Reset XTAL1 XTAL2 Debug / Programming Hardware CIP Controller Core 32/16 kb ISP FLASH Program Memory System Clock Setup External Oscillator Internal Oscillator 256 Byte RAM 1 kb XRAM 2-cycle 16 by 16 Multiply and Accumulate Clock Multiplier SFR Bus VREF VDD Port I/O Configuration Digital Peripherals UART0 Timers 0, 1, 2, 3 PCA/WDT SMBus SPI Crossbar Control Analog Peripherals VREF Priority Crossbar Decoder 10-bit IDAC P0.1 CP0 CP1 Port 0 Drivers Port 1 Drivers Port 2 Drivers Port 3 Drivers 2 Comparators P0.0/VREF P0.1/IDA0 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/C2D P3.1 P3.2 P3.3 P3.4 Low Frequency Oscillator 10-bit 200 ksps ADC C8051F361/6/8 only A M U X AIN0 AIN20 VDD Temp Sensor Figure 1.2. C8051F361/4/6/8 Block Diagram C2CK/RST VDD GND C2D Power-On Reset Supply Monitor Reset Debug / Programming Hardware CIP Controller Core 32/16 kb ISP FLASH Program Memory 256 Byte RAM 1 kb XRAM 2-cycle 16 by 16 Multiply and Accumulate SFR Bus Port I/O Configuration Digital Peripherals UART0 Timers 0, 1, 2, 3 PCA/WDT SMBus SPI Crossbar Control Priority Crossbar Decoder Port 0 Drivers Port 1 Drivers Port 2 Drivers Port 3 Drivers P0.0/VREF P0.1/IDA0 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/C2D XTAL1 XTAL2 System Clock Setup External Oscillator Internal Oscillator Clock Multiplier Low Frequency Oscillator VREF VDD 10-bit 200 ksps ADC C8051F362/7/9 only Analog Peripherals VREF 10-bit IDAC A M U X P0.1 CP0 CP1 2 Comparators AIN0 AIN20 VDD Temp Sensor Figure 1.3. C8051F362/5/7/9 Block Diagram 22 Rev. 0.2

23 1.1. CIP-51 Microcontroller Core Fully 8051 Compatible The C8051F36x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51 instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, including four 16-bit counter/timers, a full-duplex UART with extended baud rate configuration, an enhanced SPI port, 1024 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and up to 39 I/O pins Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8 Number of Instructions With the CIP-51's maximum system clock at 100 MHz, it has a peak throughput of 100 MIPS. Figure 1.4 shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks MIPS Silicon Labs CIP-51 (25 MHz clk) Microchip PIC17C75x (33 MHz clk) Philips 80C51 (33 MHz clk) ADuC (16 MHz clk) Figure 1.4. Comparison of Peak MCU Execution Speeds Rev

24 Additional Features The C8051F36x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip V DD Monitor (forces reset when power supply voltage drops below V RST as given in Table 12.1 on page 139), a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization. The internal oscillator factory calibrated to 24.5 MHz ±2%. This internal oscillator period may be user programmed in ~0.5% increments. An additional low-frequency oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. If desired, the system clock source may be switched on-the-fly between both internal and external oscillator circuits. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed. Additionally, an on-chip PLL is provided to achieve higher system clock speeds for increased throughput. VDD Px.x Px.x Comparator C0RSEF Supply Monitor + - Enable Power On Reset '0' (wired-or) /RST Low Frequency Oscillator Internal Oscillator Missing Clock Detector (oneshot) EN MCD Enable PCA WDT EN WDT Enable (Software Reset) SWRSF Errant FLASH Operation Reset Funnel XTAL1 XTAL2 PLL Circuitry External Oscillator Drive System Clock Clock Select CIP-51 Microcontroller Core Extended Interrupt Handler System Reset Figure 1.5. On-Chip Clock and Reset 24 Rev. 0.2

25 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. Program memory consists of 32/16 kb of Flash. This memory may be reprogrammed in-system in 1024 byte sectors, and requires no special off-chip programming voltage. See Figure 1.6 for the MCU system memory map. PROGRAM MEMORY DATA MEMORY 0x7C00 0x7BFF C8051F360/1/2/3/4/5/6/7 RESERVED FLASH (In-System Programmable in 1024 Byte Sectors) 0xFF 0x80 0x7F 0x30 0x2F 0x20 0x1F 0x00 INTERNAL DATA ADDRESS SPACE Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) Bit Addressable General Purpose Registers Special Function Register's (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) 0x0000 C8051F368/9 EXTERNAL DATA ADDRESS SPACE 0x4000 0x3FFF RESERVED FLASH 0xFFFF Same 1024 bytes as from 0x0000 to 0x03FF, wrapped on 1024-byte boundaries 0x0000 (In-System Programmable in 1024 Byte Sectors) 0x0400 0x03FF 0x0000 XRAM Bytes (accessable using MOVX instruction) Figure 1.6. On-Board Memory Map 1.3. On-Chip Debug Circuitry The C8051F36x devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications chan- Rev

26 nels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized. The C8051F360DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F36x MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and a debug adapter. It also has a target application board with the associated MCU installed and prototyping area, plus the required cables, and wall-mount power supply. The Development Kit requires a PC running Windows98SE or later. The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. WINDOWS 2000 or later Silicon Labs Integrated Development Environment Debug Adapter C2 (x2), VDD, GND VDD GND TARGET PCB C8051F360 Figure 1.7. Development/In-System Debug Diagram 1.4. Programmable Digital I/O and Crossbar C8051F36x devices include up to 39 I/O pins (four byte-wide Ports and one 7-bit-wide Port). The C8051F36x Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The weak pullups that are fixed on typical 8051 devices may be globally disabled, providing power savings capabilities. 26 Rev. 0.2

27 The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins. (See Figure 1.8.) On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular application. XBR0, XBR1, PnSKIP Registers P0MASK, P0MATCH P1MASK, P1MATCH, P2MASK, P2MATCH Registers Priority Decoder PnMDOUT, PnMDIN Registers Highest Priority UART SPI P0 I/O Cells P0.0 P0.7 (Internal Digital Signals) SMBus CP0 CP1 Outputs SYSCLK 2 4 Digital Crossbar 8 8 P1 I/O Cells P2 I/O Cell P1.0 P1.7 P2.0 P2.7 Lowest Priority PCA T0, T P3 I/O Cells P3.0 P available on C8051F360/1/3/4/6/8 P0 8 (P0.0-P0.7) available on C8051F360/3 P1 8 (P1.0-P1.7) (Port Latches) P2 P3 8 (P2.0-P2.7) 8 (P3.0-P3.7) Figure 1.8. Digital Crossbar Diagram (Port 0 to Port 3) 1.5. Serial Ports The C8051F36x Family includes an SMBus/I 2 C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for Rev

28 real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator drives the system clock. Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture, Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally, Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system reset, Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 PCA CLOCK MUX 16-Bit Counter/Timer Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 Capture/Compare Module 3 Capture/Compare Module 4 Capture/Compare Module 5 CEX5 CEX4 CEX3 CEX2 CEX1 CEX0 ECI Crossbar Port I/O Bit Analog to Digital Converter Figure PCA Block Diagram The C8051F360/1/2/6/7/8/9 devices include an on-chip 10-bit SAR ADC with up to 21 channels for the differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL and DNL of ±1 LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Ports1-3 are available as an ADC inputs; additionally, the on-chip Temperature Sensor output and the power supply voltage (V DD ) are available as ADC inputs. User firmware may shut down the ADC to save power. Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an external convert start signal (CNVSTR). This flexibility allows the start of conversion to be triggered by software events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indi- 28 Rev. 0.2

29 cated by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data SFRs upon completion of a conversion. Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is either within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within/outside the specified range. P available on C8051F361/2/6/7/8/9 P1.0 AMX0P ADC0CN P1.7 P2.0 AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 P available on C8051F360/1/6/8 Temp Sensor P available on C8051F361/2/6/7/8/9 P2.7 P3.0 P3.4 VDD P to-1 AMUX (+) (-) VDD 10-Bit SAR ADC Start Conversion ADC0L ADC0H 000 AD0BUSY (W) 001 Timer 0 Overflow 010 Timer 2 Overflow 011 Timer 1 Overflow 100 CNVSTR Input 101 Timer 3 Overflow P1.7 P2.0 SYSCLK REF AD0WINT P available on C8051F360/1/6/8 P2.7 P3.0 P3.4 VREF GND 23-to-1 AMUX AMX0N AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJST ADC0CF ADC0LTH ADC0GTH ADC0LTL ADC0GTL 32 Window Compare Logic Figure Bit ADC Block Diagram 1.8. Comparators C8051F36x devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time is programmable, allowing the user to select between high-speed and lowpower modes. Positive and negative hysteresis are also configurable. Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a wake-up source. Comparator0 may also be configured as a reset source. Figure 1.12 shows the Comparator0 block diagram, and Figure 1.13 shows the Comparator1 block diagram. Note: The first Port I/O pins shown in Figure 1.12 and Figure 1.13 are for the 48-pin (C8051F360/3) devices. The second set of Port I/O pins are for the 32-pin and 28-pin (C8051F361/2/4/5/6/7/8/9) devices. Please refer to the CPTnMX registers (SFR Definition 8.2 and SFR Definition 8.5) for more information. Rev