DEV BHOOMI INSTITUTE OF TECHNOLOGY DEHRADUN

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1 DEV BHOOMI INSTITUTE OF TECHNOLOGY DEHRADUN Department of Computer Science and Engg. HAND BOOK Session Class : 2 nd yr / 4 th sem

2 Syllabus Course Name: Computer Organization Course Code:TCS -401 Faculty :Ms. Preeti Raturi Semester:4 th Unit-I Register Transfer Language, Bus and Memory Transfers, Bus Architecture, Bus Arbitration, Arithmetic Logic, Shift Micro operation, Arithmetic Logic Shift Unit, Design of Fast address, Arithmetic Algorithms (addition, subtraction, Booth Multiplication), IEEE standard for Floating point numbers. Unit-II Control Design: Hardwired & Micro Programmed (Control Unit): Fundamental Concepts (Register Transfers, performing of arithmetic or logical operations, fetching a word from memory, Storing a word in memory), Execution of a complete instruction, Multiple-Bus organization, Hardwired Control, Micro programmed control(microinstruction, Micro program sequencing, Wide-Branch addressing, Microinstruction with Next-address field, Pre-fetching Microinstruction). Unit-III Processor Design: Processor Organization: General register organization, Stack organization, Addressing mode, Instruction format, Data transfer & manipulations, Program Control, Reduced Instruction Set Computer Input-Output Organization: I/O Interface, Modes of transfer, Interrupts & Interrupt handling, Direct Memory access, Input-Output processor, Serial Communication. Unit-IV Memory Organization: Memory Hierarchy, Main Memory (RAM and ROM Chips), organization of Cache Memory, Auxiliary memory, Cache memory, Virtual Memory, Memory management hardware. Unit V Parallel Processing & Pipelining: Arithmetic Pipelining, Instruction Pipelining, RISC Pipelining, Vector Processing, Array Processor. Multiprocessor: Characteristic of Multiprocessor, Interconnection Structure, Inter-processor Arbitration, Cache Coherence

3 DBIT/BTech/CSE/06 DBIT DEHRADUN LESSON PLAN SEMESTER/YEAR: 4 th /2 nd COURSE: COMPUTER ORGANIZATION S. No. Topic Name DEPARTMENT : CSE COURSE CODE : TCS-401 Reference/ Text Book/ Web (R/T/W) No. Of Lectures Delivery Method T1 1. Register Transfer Language 1 Chalk &Talk 2. Bus and Memory Transfers T1 1 Chalk &Talk 3. Bus Architecture,Bus Arbitration T1 & R1 1 Chalk &Talk 4. Arithmetic Logic, Shift Microoperation T1 & R1 Chalk 2 &Talk 7. Arithmetic Logic Shift Unit, Design of Fast address T1 & R1 1 Chalk &Talk 8. Arithmetic Algorithms (addition, subtraction, Booth Multiplication T1 & R1 2 Chalk &Talk 9. IEEE standard for Floating point numbers. T1 & R1 1 Chalk &Talk 10. Hardwired Control Unit T1 2 Chalk 11. Micro Programmed Control Unit &Talk T1&R1 1 Chalk &Talk T1 Chalk 2 &Talk Fundamental Concepts (Register Transfers performing of arithmetic 12. or logical operations fetching a word from memory, Storing a word in memory) 13. Execution of a complete instruction T1 1 Chalk &Talk 14. Multiple-Bus organization T1 2 Chalk &Talk 15. Hardwired Control Micro programmed control(microinstruction T1 2 Chalk &Talk 16. Microprogram sequencing T1 1 Chalk 17. Wide-Branch addressing, Microinstruction with Next-address field 18. Processor Organization: General register organization &Talk T1 2 Chalk &Talk T1 2 Chalk &Talk 19. Stack organization T1 2 Chalk &Talk 20. Addressing mode T1 2 Chalk &Talk 21 Instruction format, Data transfer & manipulations 22. Program Control, Reduced Instruction Set Computer. 23. I/O Interface, Modes of transfer T1 1 Chalk &Talk R2 1 Chalk &Talk R2 1 Chalk &Talk T1 2 Chalk &Talk Interrupts & Interrupt handling, Direct Memory access, Input- 24. Output processor 25. Serial Communication T1 2 Chalk &Talk Remarks

4 DBIT/BTech/CSE/ Memory Hierarchy, Main Memory (RAM and ROM Chips T1 1 Chalk &Talk 27. Organization of Cache Memory T1 1 Chalk &Talk T1 1 Chalk 28. Auxiliary memory, Cache memory &Talk T1 1 Chalk 29. Virtual Memory, Memory management hardware. 30. Parallel Processing, Pipelining- Arithmetic Pipelining &Talk T1 2 Chalk &Talk 31. Instruction Pipelining T1 2 Chalk &Talk 32. RISC Pipelining T1 1 Chalk &Talk 33 Vector Processing, Array Processor T1 1 Chalk &Talk T1 34. Multiprocessor: Characteristic of Multiprocessor, 2 Chalk &Talk 35. Interconnection Structure T1 1 Chalk 36. Interprocessor Arbitration, Cache Coherence Total Lectures: 50 REMARKS/RECOMMENDATIONS FOR FUTURE: &Talk T1 2 Chalk &Talk EXTRA CLASS TAKEN (IF ANY): TEXT BOOKS: [T1] Computer Organization, John P.Hayes, McGraw Hill, 3rd Edition. [T2] Computer System Architecture, M. Mano, Pearson, 3rd Edition. REFERENCE BOOK: [R1] Computer Organization, Vravice, Zaky & Hamacher (TMH Publication) [R2] Structured Computer Organization, Tannenbaum(PHI) [R3] Computer Organization, Stallings(PHI) [R4] R.S.Gaonkar - Microprocessor architecture Programming and Application with 8085/8080A - Wiley Eastern Limited. Signature of HOD: Date:

5 ASSIGNMENT SHEET Course Name: Computer Organization Assignment No. 1 Course Code: TCS-401 Faculty :Ms. Preeti Raturi Semester: IV Unit 1: Introduction to Computer Organization Date of Issue: Date of Submission: 1. What is register transfer logic? 2. Explain the basic symbols sued in register transfer language. 3. Represent the following conditional control statement by two register transfer statements with control functions: If (P=1) then (R1<- R2) else if (Q=1) then (R1<- R3) 4. What is wrong with the following register transfer statements? a. xt: AR<- AR, AR<-0 b. yt: R1<- R2, R1<-R3 c. zt: PC<- Ar, PC<- PC+1 5. Multiply the numbers using booth multiplication: (11)*(-5)

6 ASSIGNMENT SHEET Course Name: Computer Organization Assignment No. 2 Course Code: TCS-401 Faculty :Ms. Preeti Raturi Semester: IV Unit 2 : Addressing, Register Transfer Language Date of Issue: Date of Submission: 1. What is a control unit? What are the functions of a control unit? 2. Explain with the block diagram for fetching a word from memory in hardwired control unit. 3. Explain with the block diagram for storing a word in memory in hardwired control unit 4. What is micro programmed control unit? Explain with block diagram. 5. Differentiate between hardwired and micro programmed control unit. 6. Define the following: a) Control memory b) control word c) sequencer d) pipeline register e) control address registers

7 ASSIGNMENT SHEET Course Name: Computer Organization Assignment No. 3 Course Code: TCS-401 Faculty :Ms. Preeti Raturi Semester: IV Unit 3 : Processor Organization Date of Issue: Date of Submission: 1. What is processor organization? What are the major components of a computer system? 2. A stack is organized such that SP always points at the next empty location on the stack. This means that SP can be initiated to 4000 and the first item in the stack is stored in location List the micro operations for the push and pop operations. 3. Convert the following numerical arithmetic expression into reverse polish notation an show the stack operations for calculating the numerical result. a. (3+4)[10(2+6) +8] 4. How many times does the control unit refers to memory when it fetches and executes an indirect addressing mode instruction if the instruction is (A) a computational type requiring an operand from memory (B) a branch type. 5. What must the address field of an indexed addressing mode instruction be to make it the same as a register indirect mode instruction?

8 ASSIGNMENT SHEET Course Name: Computer Organization Assignment No. 4 Course Code: TCS-401 Faculty :Ms. Preeti Raturi Semester: IV Unit/Title: IV/ Memory Organization Date of Issue: Date of Submission: 1. Explain the memory hierarchy of computer system. 2. Explain the chip set selection in RAM chip. 3. Explain the concept of virtual memory. 4. Explain the memory mapping methods in cache memory. 5. Explain instruction set Architecture? Give examples. 6. a. How many RAM chips are needed to provide a memory capacity of 2048 bytes? b. How many lines of the address bus must be used to access 2048 bytes of memory? How many of these lines will be common to all chips? c. How many lines must be decoded for chip select? Specify the size of the decoders.

9 ASSIGNMENT SHEET Course Name: Computer Organization Assignment No. 5 Course Code: TCS-401 Faculty :Ms. Preeti Raturi Semester: IV Unit/Title: V/ Instruction Pipelining Date of Issue: Date of Submission: 1. What are the various stages in a Pipeline execution? 2. What are the types of pipeline hazards? 3. Define structural, data, and control hazard. 4. List two conditions when processor can stall. 5. List the types of data hazards. 6. Explain the function of six segment pipeline and draw a space diagram for six segment pipeline solving the time it takes to process eight tables.

10 TUTORIAL SHEET Course Name:Computer Organization Tutorial Sheet No. 1 Unit/Title: UNIT 1 Course Code: TCS 401 Faculty : Ms. Preeti Raturi Date of Discussion: Semester:4 th 1. Explain the concept of normalization in floating point representation. 2. What is register transfer? Give examples. 3. Give the block diagram for bus system for four registers. 4. For a given bus system, what is the method of bus selection? 5. What is memory transfer? Explain the terms with reference to memory transfer: i. Memory read ii. Memory write iii. DR M[AR] 6. What are logic micro operations? Give few examples of micro operations with syntax. 7. What are shift micro operations? Give few examples of shift micro operations with syntax.

11 TUTORIAL SHEET Course Name:Computer Organization Tutorial Sheet No. 2 Course Code: TCS 401 Faculty : Ms. Preeti Raturi Semester:4 th Unit/Title: Unit-2 Date of Discussion: 1. What are instruction codes and operation codes? Give examples. 2. Give block diagrams for the working of direct and indirect address. Also example the calculation of effective address. 3. What are the different types of registers used in computer system? Give their functions and sizes. 4. Explain the basic computer instruction formats. Also give their instruction formats. 5. What is a control unit? Differentiate between hardwired and micro programmed control unit. 6. Explain with a block diagram for fetching a word from memory in a hardwired control unit. 7. Give the control timing signal for hardwired control unit.

12 TUTORIAL SHEET Course Name:Computer Organization Tutorial Sheet No. 3 Course Code: TCS 401 Faculty : Ms. Preeti Raturi Semester:4 th Unit/Title: Unit-3 Date of Discussion: 1. What is processer organization? Give a block diagram of the basic components of computer organization. 2. Explain the creation of a control word in general register organization of 7 registers. 3. What is control word? Give the encoding of register selection fields. 4. Explain the block diagram of 64 word stack. Also give the algorithm for following stack operations: i. PUSH ii. POP 5. Write a program to evaluate the expression: X = A B + A (B D + C E) a. Using an accumulator type computer with one address register.

13 TUTORIAL SHEET Course Name:Computer Organization Tutorial Sheet No. 4 Course Code: TCS 401 Faculty : Ms. Preeti Raturi Semester:4 th Unit/Title: Unit-4 Date of Discussion: 1. Draw a space-time diagram for a six segment pipeline showing takes to process eight tasks. 2. Give an example that uses delayed load with the three-segment pipeline. 3. Give an example of a program that will cause a branch penalty in the three-segment pipeline.. 4. Formulate a six-segment instruction pipeline for a computer operation to be performed in each segment. 5. What are vector processors and array processors? Give examples and applications.

14 TUTORIAL SHEET Course Name:Computer Organization Tutorial Sheet No. 5 Course Code: TCS 401 Faculty : Ms. Preeti Raturi Semester:4 th Unit/Title: Unit 5 Date of Discussion: 1. What are the differences between electromechanical and electromagnetic peripheral devices? 2. Why does DMA have priority over the CPU when both request transfer? 3. What is the minimum number of bits that a frame must have in the bit-oriented protocol? 4. A data communication links employs the character-controlled protocol with data transparency using the DLE character. The text message that the transmits sends between STX and ETX is as follows: DLE STX DLE DLE ETX DLE DLE ETX DLE ETX What is the binary value of the transparent text data?

15 TUTORIAL SHEET Course Name:Computer Organization Tutorial Sheet No. 6 Unit/Title: Unit- 3 and 4 Course Code: TCS 401 Faculty : Ms. Preeti Raturi Date of Discussion: Semester:4 th 1. Explain memory hierarchy in a computer system 2. A computer s memory is composed of 8K words of 32 bits each. How many bits are required for memory address if the smallest addressable memory unit is a word? processes are currently running. If the OS permitted each process to use the maximum possible address space, how many page table entries are required. (i) Conventional page tables (ii) Inverted page tables 4. Draw a diagram showing how the bits of a virtual address are used to generate a 32- bit physical address.

16 TUTORIAL SHEET Course Name:Computer Organization Tutorial Sheet No. 7 Course Code: TCS 401 Faculty : Ms. Preeti Raturi Unit/Title: Unit 4 and 5(Collection) Date of Discussion: Semester: 4 th 1. Determine the number of clock cycles that it takes to process 200 tasks in a six segment pipeline. 2. Explain the organization of virtual memory 3. A no pipeline system takes 50 ns to process a task. The same task can be processed in 6 segment pipeline with a clock cycle of 10 ns. Determine the speedup ratio of pipeline for 100 tasks. What is maximum speedup ratio? 4. Explain the following: i. Functions of peripherals interface ii. Modes of transfer in DMA iii. Speedup ratio iv. Divide overflow v. Difference between RISC & CISC 5. An instruction is stored at location 300 with its address field at location 301. The address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is i. Direct ii. Immediate iii. Relative iv. Register indirect v. Index with R1 as the index register

17 QUESTION BANK Course Name: Computer Organization Unit 1: 1 & 2 Course Code: TCS-401 Faculty :Ms. Preeti Raturi Semester: IV SHORT QUESTIONS 1. Define the term Computer Architecture. 2. Define Multiprocessing. 3. What is meant by instruction? 4. What is Bus? Draw the single bus structure. 5. Define Pipeline processing. 6. Draw the basic functional units of a computer. 7. Briefly explain Primary storage and secondary storage. 8. What is register? 9. Define RAM. 10. Give short notes on system software. 11. Write down the operation of control unit? 12. Define Memory address register. 13. What is stack & queue? 14. Define Addressing modes. 15. Write the basic performance equation? 16. Define clock rate. 17. List out the various addressing techniques. 18. Draw the flow of Instruction cycle. 19. Suggest about Program counter. 20. List out the types in displacement addressing. 21. What is meant by stack addressing? 22. Define carry propagation delay. 23. Draw a diagram to implement manual multiplication algorithm. 24. Perform the 2 s complement subtraction of smaller number(101011) from larger number(111001). PART-B 1. Write briefly about computer fundamental system? 2. Explain memory unit functions. 3. Explain memory locations and addresses. 4. Explain Software interface. 5. Explain instruction set Architecture? Give examples. 6. What is bus explain it in detail?

18 7. Explain briefly about performance evaluation by using various bench marks. List out the types of bench marks and mention its advantage and disadvantage. 8. Explain the operations of stacks and queues. 9. Discuss about different types of addressing modes. 10. Explain in detail about different instruction types and instruction sequencing. 11. Explain Fixed point representation. 12. How floating point addition is implemented. Explain briefly with a neat diagram. 13. Give the difference between RISC and CISC. 14. Write an algorithm for the division of floating point number and illustrate with an example.

19 QUESTION BANK Course Name: Computer Organization Course Code: TCS-401 Faculty :Ms. Preeti Raturi Semester: IV Unit 3 PART-A 1. What are the basic operations performed by the processor? 2. Define Data path. 3. Define Processor clock. 4. Define Latency and throughput. 5. Discuss the principle operation of micro programmed control unit. 6. What are the differences between hardwired and micro programmed control units? 7. Define nanoprogramming. 8. What is control store? 9. What are the advantages of multiple bus organization over a single bus organization? 10. Write control sequencing for the executing the instruction. Add R4,R5,R What is nano control memory? 12. What is the nano instruction format of Qm-1? 13. What is the capacity of nano control memory? 14. Define micro routine. 15. What is meant by hardwired control? 16. What are the types of micro instruction? 17. Name the methods for generating the control signals. PART-B 1. Draw and explain typical hardware control unit. 2. Draw and explain about micro program control unit. 3. Write short notes on (i)micro instruction format (ii) Symbolic micro instruction. 4. Explain multiple bus organization in detail.

20 QUESTION BANK Course Name: Computer Organization Unit 4 Course Code: TCS-401 Faculty :Ms. Preeti Raturi Semester: IV PART-A 1. What is Pipelining? 2. What are the major characteristics of a Pipeline? 3. What are the various stages in a Pipeline execution? 4. What are the types of pipeline hazards? 5. Define structural, data, and control hazard. 6. List two conditions when processor can stall. 7. List the types of data hazards. 8. List the techniques used for overcoming hazard. 9. What is instruction level parallelism? 10. What are the types of dependencies? 11. What is delayed branching? 12. Define deadlock. 13. Draw the hardware organization of two stage pipeline. 14. What is branch prediction? 15. Give two examples for instruction hazard. 16. List the various pipelined processors. 17. Why we need an instruction buffer in a pipelined CPU? 18. What are the problems faced in instruction pipeline? 19. Write down the expression for speedup factor in a pipelined architecture. PART-B 1. Explain different types of hazards that occur in a pipeline. 2. Explain various approaches used to deal with conditional branching. 3. Explain the basic concepts of pipelining and compare it with sequence processing with a neat diagram. 4. Explain instruction pipelining. 5. What is branch hazard? Describe the method for dealing with the branch hazard? 6. What is data hazard? Explain the methods for dealing with data hazard? 7. Explain the function of six segment pipeline and draw a space diagram for six segment pipeline solving the time it takes to process eight tables. 8. Explain the influence of instruction sets. 9. Draw and explain data path modified for pipelined execution. 10. Explain about various exceptions.

21 QUESTION BANK Course Name: Computer Organization Unit 5 Course Code: TCS-401 Faculty :Ms. Preeti Raturi Semester: IV PART- A 1. What is Memory system? 2. Give classification of memory. 3. Define cache. 4. What is Read Access Time? 5. Define Random Access Memory. 6. What are PROMS? 7. Define Memory refreshing. 8. What is SRAM and DRAM? 9. What is volatile memory? 10. Define data transfer or band width. 11. What is flash memory? 12. What is multi level memories? 13. What is address translation page fault routine, page fault and demand paging? 14. What is associate memory? 15. Define Seek time and latency time. 16. What is TLB? 17. Define Magneto Optical disk. 18. Define Virtual memory. 19. What are the enhancements used in the memory management? 20. Define the term LRU and LFU. 21. Define memory cycle time. 22. What is static memories? 23. What is locality of reference? 24. Define set associative cache. 25. What is meant by block replacement? 26. List the advantages of write through cache. 27. Give formula to calculate average memory access time. 28. Define conflict. 29. What is memory interleaving? 30. What is DVD? 31. Give the features of ROM cell. 32. List the difference between static RAM and dynamic RAM. 33. What is disk controller? 34. How a data is organized in the disk?

22 PART-B 1. Illustrate the characteristics of some common memory technologies. 2. Describe in detail about associative memory. 3. Discuss the concept of Memory interleaving and give its advantages. 4. Discuss the different mapping techniques used in cache memories and their relative merits and demerits. 5. Comparing paging and segmentation mechanisms for implementing the virtual memory. 6. What do you mean by virtual memory? Discuss how paging helps in implementing virtual memory. 7. Discuss any six ways of improving the cache performance. 8. Explain the virtual memory translation and TLB with necessary diagram. 9. Explain the organization of magnetic disk and magnetic tape in detail.

23 Syllabus Course Name: Theory of Automata and Formal Language Course Code:TCS -403 Faculty :Mr. Dhajvir Singh Rai Semester:4 th Unit I Introduction to defining language, Kleene closures, Arithmetic expressions, defining grammar, Chomsky hierarchy, Finite Automata (FA), Transition graph, generalized transition graph. Unit II Nondeterministic finite Automata (NFA), Deterministic finite Automata (DFA), Construction of DFA from NFA and optimization, FA with output: Moore machine, Mealy machine and Equivalence, Applications and Limitation of FA. Unit III Arden Theorem, Pumping Lemma for regular expressions, Myhill-Nerode theorem, Context free grammar: Ambiguity, Simplification of CFGs, Normal forms for CFGs, Pumping lemma for CFLs, Decidability of CFGs, Ambiguous to Unambiguous CFG. Unit IV Push Down Automata (PDA): Description and definition, Working of PDA, Acceptance of a string by PDA, PDA and CFG, Introduction to auxiliary PDA and Two stack PDA. Unit V Turing machines (TM): Basic model, definition and representation, Language acceptance by TM, TM and Type 0 grammar, Halting problem of TM, Modifications in TM, Universal TM, Properties of recursive and recursively enumerable languages, unsolvable decision problem, undecidability of Post correspondence problem, Church s Thesis, Recursive function theory. Text Books: 1. Hopcroft, Ullman, Introduction to Automata Theory, Language and Computation, Nerosa Publishing House, 3rd Edition 2. K.L.P. Mishra and N.Chandrasekaran, Theory of Computer Science(Automata, Languages and Computation), PHI, 3rd Edition Reference Books: 1. Martin J. C., Introduction to Languages and Theory of Computations, TMH 2. Papadimitrou, C. and Lewis, C.L., Elements of theory of Computations, PHI 3.Cohen D. I. A., Introduction to Computer theory, John Wiley & Sons 4. Kumar Rajendra, Theory of Automata (Languages and Computation), PPM

24 LESSON PLAN SEMESTER/YEAR: 4 th /2 nd COURSE: THEORY OF AUTOMATA & FORMAL LANGUAGES S. No. UNIT-1 Topic Name Reference/ Text Book/ Web (R/T/W) DEPARTMENT: CSE CODE: TCS-403 No. Of Lectures Delivery Method Remarks 1. Introduction to defining language T1,R1 1 Chalk & Talk 2. Kleene closures, Arithmetic expressions, T1,R1 1 Chalk & Talk 3. defining grammar, T1,T2 1 Chalk & Talk 4. Chomsky hierarchy, T1,R1 1 Chalk & Talk 5. Finite Automata (FA) T1,R1 2 Chalk & Talk 6. Transition graph T1,T2 1 Chalk & Talk 7. generalized transition graph T1,R1 2 Chalk & Talk 8. Exercise T1,R1 1 Chalk & Talk UNIT-2 9. Nondeterministic finite Automata (NFA) T1,R1 2 Chalk & Talk 10. Deterministic finite Automata (DFA) T1,R1 2 Chalk & Talk 11. Construction of DFA from NFA and optimization T1,R1 2 Chalk & Talk 12 FA with output: Moore machine and Equivalence T1,R1 1 Chalk & Talk 13. Mealy machine and Equivalence T1,R1 1 Chalk & Talk 14. and Limitation of FA T1,T2 2 Chalk & Talk Unit Arden Theorem T1,R1 2 Chalk & Talk 16. Pumping Lemma for regular expressions T1,R1 2 Chalk & Talk 17. Myhill-Nerode theorem T1,R1 1 Chalk & Talk 18. Context free grammar T1,R1 2 Chalk & Talk 19. Ambiguity T2,R1 1 Chalk & Talk 20. Simplification of CFGs T2 1 Chalk & Talk 21. Normal forms for CFGs T2,R1 1 Chalk & Talk 22. Pumping lemma for CFLs T2 2 Chalk & Talk

25 23. Decidability of CFGs T2,R1 1 Chalk & Talk 24. Ambiguous to Unambiguous CFG T2 1 Chalk & Talk Unit Push Down Automata (PDA): Description and definition T2,R1 1 Chalk & Talk 26. Working of PDA T2 2 Chalk & Talk 27. Acceptance of a string by PDA T1 2 Chalk & Talk 28. PDA and CFG 1 Chalk & Talk 29. Introduction to auxiliary PDA T1,T2 1 Chalk & Talk 30. Two stack PDA T2 2 Chalk & Talk Unit Turing machines (TM): Basic model, definition and T1 1 Chalk & Talk representation 32. Language acceptance by TM, TM and Type 0 grammar T1,R1 2 Chalk & Talk 33. Halting problem of TM, Modifications in TM T1,R1 1 Chalk & Talk 34. Universal TM, Properties of recursive and recursively T1 2 Chalk & Talk enumerable languages 35. unsolvable decision problem, undecidability of Post T2 1 Chalk & Talk correspondence problem 36. Church s Thesis T2 1 Chalk & Talk 37. Recursive function theory T1,R1 1 Chalk & Talk Total Lectures: 52 REMARKS/RECOMMENDATIONS FOR FUTURE: EXTRA CLASS TAKEN (IF ANY): TEXT BOOKS: [T1] Aho, Sethi & Ullman, "Compiler Design", Addision Wesley/ Pearson [T2] O. G. Kakde; Compiler Design,4/e; Universities Press (2008) REFERENCE BOOKS: [R1] Chattopadhyay Santanu; Compiler Design; Phi Learning (2009) Signature of HOD: Date:

26 ASSIGNMENT SHEET Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Assignment No.1 Branch:CSE Semester: 4 th Unit/Title: I/Introduction to defining language Date of Issue: Date of Submission: 1. What is automaton? Explain DFA and NDFA with examples. 2. What are the limitations of FSM? 3. Let L be a set accepted by accepted by a Non-deterministic finite Automaton then there exists a deterministic finite automaton that accepts L. Prove it. 4. Find a regular expression corresponding to the language of all strings containing exactly two 0 s for {0, 1}*. 5. Find a regular expression corresponding to the language of all strings in which number of 0 s is even for {0, 1}*. 6. What is linear bounded automaton? Explain with the help on an example. 7. What is context sensitive language? Explain is detail. 8. Construct a finite automaton which will accept those strings of binary number which are di4thsible by Write and explain the algorithm for minimizing the number of states of a DFA. 10. What do you mean by substitution and homomorphism? Prove that the class of regular sets is closed under homomorphism and inverse homomorphism.

27 ASSIGNMENT SHEET Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Assignment No.2 Branch:CSE Semester: 4 th Unit/Title: II/ Nondeterministic finite Automata (NFA) Date of Issue: Date of Submission: Q.1 What are Mealy and Moore machines? Let M 1 = {θ,, Δ, S, α, q 0 } be a Mealy machine. Show that there is a Moore machine M 2 equivalent to M 1. Q.2 Convert Moore machine to equivalent Mealy M/c. Given: Present state Next state Output q 1 q 1, q 2 0 q 2 q 1, q 3 0 q 3 q 1, q 3 1 Q.3 Show by an example that fir some regular language L, any FA recognizing L must have more than one accepting states. Characterize those regular languages for which this is true. Q.4 Write the Arden s method to convert an NFA to DFA. Illustrate with some example. Q.5 What are the properties of FSM? Q.6 Explain the method how to find equivalence of Moore and Mealy machines. Q.7 What is the difference in between Moore and Mealy machines? Q.8 What are the advantages of representing states using FSM? Q.9 Design any Mealy machine and convert it to Moore machine. Q.10 Design any Moore machine and convert it to Mealy machine.

28 ASSIGNMENT SHEET Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Assignment No. 3 Branch:CSE Semester: 4 th Unit/Title: III/ Pumping Lemma for regular expressions Date of Issue: Date of Submission: Q1. Prove that (aa*bb*)* = ^+a(a+b)*b. Q2. What do you mean by Pumping lemma? Using concept of Pumping Lemma prove that the language L = {a n b n n>1} is not regular. Q3. Prove that (aaa*)* = (aa + aaa)*. Q4. State and prove Myhill-Nerode Theorem for minimization of finite Automaton. Q.5 Discuss halting problem of Turing machine. Q.6 Using concept of Pumping Lemma prove that the set L = {a p p is a prime number} is not regular. Q.7 Explain two types acceptance by push down automata. Q.8 State and prove pumping lemma for regular sets. Q.9 Show that if there are strings x and y in the language L so that x is a prefix of y and x not equal to y, then no DPDA can accept L by empty stack. Q10. Prove that every CFL, L without є-production can be generated by a grammar for which every production can be generated by a grammar for which every production is of the form A aα where A is a variable, a is a terminal and α is a (possibly empty) string of variables. Convert the following grammar to GNF: G = ({A1, A2, A3}, {a, b}, P, A1) where P consists of following productions: A1 A2A3 A2 A3A1/b A3 A1A2/a

29 DEV DEV BHOOMI BHOOMI INSTITUTE INSTITUTE OF OF TECHNOLOGY, TECHNOLOGY, DEHRADUN DEHRADUN ASSIGNMENT SHEET Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Assignment No. 4 Branch:CSE Semester: 4 th Unit/Title: IV/ Push Down Automata (PDA) Date of Issue: Date of Submission: Q1. Let G be the grammar S as asbs є: epsilon Prove that L(G) = {x each prefix of x has at least as many a s as b s}. Q.2 Let G be the grammar S ab ba A a as baa B b bs abb For the string aaabbabbba find i) leftmost derivation ii) parse tree. Q3. Find CSG generating the language: { SS/S є {a, b} + }. Q4. What are the differences in between context free and context sensitive grammar? Q5. What is Griebach normal form? Q6. Let G be S AB, A a, B C b, C D, D E and E a. Eliminate unit productions and get an equivalent grammar. Q7. Convert the following grammar to GNF: S AB, A BS b, B SA a. Q.8 Convert the following grammar to Chomsky s normal form: S aad, A ab bab, B b, D d. Q.9 What is Chomsky s normal form? Explain with the help of example.write the unrestricted grammar for generating the language L = { a i b i c i i>= 1}

30 ASSIGNMENT SHEET Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Assignment No. 5 Branch:CSE Semester: 4 th Unit/Title: V/Turing machines (TM) Date of Issue: Date of Submission: Q1. Design a PDA which accepts the language: L = { wcw t /w є (a, b)* } Q2. Design a Turing machine which accepts the language L = { ww/w є (a, b)* }. Q3. What are universal Turing machines? Q4. Explain Chomsky hierarchy of grammar. What is relation between languages of classes? Q.5 Prove the equivalence of type O grammars and Turing machines. Q.6 Show that Fibonacci numbers are generated by a primitive recursive function. Q.8 Show that the function f(x,y) = x*y is primitive recursive. Q.9 Write a short note on PCP problem. Q.10 Design a TM for accepting the set of strings with an equal number of 0 a s and 1 a s.

31 TUTORIAL SHEET Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Unit/Title: 1/ Introduction to defining language Tutorial Sheet No. 1 Date of Discussion: Semester: 4 th 1. If L is accepted by an NFA with ε-transition then show that L is accepted by an NFA without ε-transition. 2. Construct a DFA equivalent to the NFA. M=({p,q,r},{0,1}, δ,p,{q,s}) Where δis defined in the following table. 0 1 P {q,s} {q} Q {r} {q,r} R {s} {p} S - {p} 3. Show that the set L={an bn/n>=1} is not a regular. (6) b)construct a DFA equivalent to the NFA given below: (10) 0 1 P {q,q} {p} Q {r} r R {s} - S {s} {s} 4. Check whether the language L=(0n1n / n>=1) is regular or not? Justify your answer. 5. Let L be a set accepted by a NFA then show that there exists adfa that accepts L.

32 TUTORIAL SHEET Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Unit/Title: II/ Nondeterministic finite Automata (NFA), Tutorial Sheet No. 2 Date of Discussion: Semester: 4 th 1. Convert the following NFA to a DFA. Discuss on the relation between DFA and minimal DFA 2. Construct a NDFA accepting all string in {a, b} with either two consecutive a s or two Consecutive b s. 3. Give the DFA accepting the following language Set of all strings beginning with a 1 that when interpreted as a binary integer is a Multiple of Draw the NFA to accept the following languages. (i) Set of Strings over alphabet {0, 1,.9} such that the final digit has appeared before. (ii)set of strings of 0 s and 1 s such that there are two 0 s separated by a number of positions that is a multiple of Let L be a set accepted by an NFA. Then prove that there exists a deterministic finite automaton that accepts L.Is the converse true? Justify your answer. (10)

33 TUTORIAL SHEET Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai sunit/title: III/ Context free grammar Tutorial Sheet No. 3 Date of Discussion: Semester: 4 th 1. a. What are the closure properties of CFL? State the proof for any two properties. b. Construct a CFG representing the set of palindromes over (0+1)*. 2. a. if G is the grammar S SbS a show that G is ambiguous. b. Let G= (V,T, P,S) be a CFG. If the recursive inference procedure tells that terminalstring w is in the language of variable A, then there is a parse tree with root A and yield w. 3. Discuss in detail about ambiguous grammar and remoivng ambiguity from grammar. 4. Prove that if G is a CFG whose language contains at least one string other than, then there is a grammar G1 in Chomsky Normal Form such that L(G1) = L(G) { }. 5. Consider the grammar E E + E E*E (E) I I a+b Show that the grammar is ambiguous and remove the ambiguity.

34 TUTORIAL SHEET Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Unit/Title: IV/ Context free grammar Tutorial Sheet No. 4 Date of Discussion: Semester: 4 th 1. If L is Context free language then prove that there exists PDA M such that L=N(M). 2. Explain different types of acceptance of a PDA.Are they equivalent in sense of language acceptance? Justify your answer. 3. Construct a PDA accepting {an bm an/ m, n>=1} by empty stack. Also construct the corresponding context-free grammar accepting the same set. 4. Prove that L is L(M2 ) for some PDA M2 if and only if L is N(M1) for some PDA M. 5. Define Deterministic Push Down Automata DPDA. Is it true that DPDA and PDA are equivalent in the sense of language acceptance is concern? Justify Your answer.

35 TUTORIAL SHEET Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Unit/Title: V/ Push Down Automata (PDA) Tutorial Sheet No. 5 Date of Discussion: Semester: 4 th 1. Define a PDA. Give an Example for a language accepted bypda by empty stack. 2. If L is Context free language then prove that there exists PDA M such that L=N(M). 3. Explain different types of acceptance of a PDA. Are they equivalent in sense of language acceptance? Justify your answer 4. Construct the grammar for the following PDA. M=({q0, q1},{0,1},{x,z0},δ,q0,z0,φ) and where δis given by δ(q0,0,z0)={(q0,xz0)}, δ(q0,0,x)={(q0,xx)},δ(q0,1,x)={(q1, ε)}, δ(q1,1,x)={(q1, ε)},δ(q1, ε,x)={(q1, ε)}, δ(q1, ε, Z0 )={(q1, ε)}. (12)b) Prove that if L is N(M1) for some PDA M1 then L is L(M2 ) for some PDA M2. 5. Construct a PDA that recognizes the language {ai bj ck i,j,k>0 and i=j or i=k}. 6. Discuss about PDA acceptance 1)From empty Stack to final state. 2)From Final state to Empty Stack.

36 TUTORIAL SHEET Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Unit/Title: V/ Push Down Automata (PDA) Tutorial Sheet No. 6 Date of Discussion: Semester: 4 th 1. If L is Context free language then prove that there exists PDA M such that L=N(M). 2. Explain different types of acceptance of a PDA. Are they equivalent in sense of language acceptance? Justify your answer 3. a)construct the grammar for the following PDA. M=({q0, q1},{0,1},{x,z0},δ,q0,z0,φ) and where δis given by δ(q0,0,z0)={(q0,xz0)}, δ(q0,0,x)={(q0,xx)},δ(q0,1,x)={(q1, ε)},δ(q1,1,x)={(q1, ε)},δ(q1, ε,x)={(q1, ε)}, δ(q1, ε, Z0 )={(q1, ε)}. (12) b) Prove that if L is N(M1) for some PDA M1 then L is L(M2 ) for some PDA M2. 4. Construct a PDA that recognizes the language {ai bj ck i,j,k>0 and i=j or i=k}. 5. Construct a Context free grammar G which accepts N(M), where M=({q0,q1},{a,b},{z0,z},δ,q0,z0,Φ) and where δis given by δ(q0,b,z0)={(q0,zz0)} δ(q0, ε,z0)={(q0, ε)} δ(q0,b,z)={(q0,zz)} δ(q0,a,z)={(q1,z)} δ(q1,b,z)={(q1, ε) δ(q1,a,z0)={(q0,z0)}

37 TUTORIAL SHEET Unit/Title: Turing machines (TM) Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Tutorial Sheet No. 7 Date of Discussion: Semester: 4 th 1. Explain in detail notes on Turing Machine with example. 2. Consider the language L={a,b}*{aba}{a,b}*={x ε{a,b}* x containing the substring aba}. L is the regular language, and we can draw an FA recognizing L. 3. Design a Turing Machine M to implement the function multiplication using the subroutine copy. 4. Explain how a Turing Machine with the multiple tracks of the tape can be used to determine the given number is prime or not. 5. Design a Turing Machine to compute f(m+n)=m+n, V m,n>=0 and simulate their action on the input 0100.

38 TUTORIAL SHEET Unit/Title: Turing machines (TM) Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Tutorial Sheet No. 8 Date of Discussion: Semester: 4 th 1. Define Turing machine for computing f(m, n)=m-n ( proper subtraction). 2. Explain how the multiple tracks in a Turing Machine can be used for testing given positive integer is a prime or not. 3. Explain in detail The Turing Machine as a Computer of integer functions. 4. Design a Turing Machine to accept the language L={0n 1n/n>=1} 5. Construct a Turing Machine that recognizes the language {wcw / w {a, b} + }

39 Question Bank Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Branch:CSE Semester: 4 th Unit/Title: I/Introduction tofinite AUTOMATA 1. Define finite automata. 2. Write the difference between the + closure and * closure. 3. Define alphabet, string, powers of an alphabet and concatenation of strings. 4. Define language and Grammar give an example. 5. What is a transition table and transition graph?

40 Question Bank Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Branch:CSE Semester: 4 th Unit/Title: I/ Nondeterministic Finite Automata 1. Give the DFA accepting the language over the alphabet 0, 1 that has the set of allstrings beginning with Give the DFA accepting the language over the alphabet 0,1 that have the set of allstrings that either begins or end(or both) with Define NFA. 4. Difference between DFA and NFA. 5. Write the notations of DFA. 6. Define ε-nfa. 7. Define the language of NFA. 8. Is it true that the language accepted by any NFA is different from the regularlanguage? Justify your Answer. 9. Define Regular Expression. 10. List the operators of Regular Expressions 11. State pumping lemma for regular languages 12. Construct a finite automaton for the regular expression 0*1*. 13. List out the applications of the pumping lemma. 14. Define Epsilon Closures. 20. State minimization of DFA.

41 Question Bank Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Branch:CSE Semester: 4 th Unit/Title: Context Free Grammars 1. Define CFG. 2. Define production rule. 3. Define terminal and non terminal symbols. 4. Write about the types of grammars. 5. What is ambiguity? 6. Define sentential form. 7. Define parse tree. 8. What is a derivation? 9. What is a useless symbol and mention its types. 10. What is null production and unit production? 11. What are the two normal forms of CFG? 12. State Greibach normal form of CFG. 13. Mention the application of CFG. 14. Construct a CFG for the language of palindrome string over {a, b}.write the CFGfor the language, L=(anbn n). 15. Construct a derivation tree for the string using the grammar S->A0S 0 SS, A-> S1A Show that id+id*id can be generated by two distinct leftmost derivation in thegrammar E- >E+E E*E (E) id.

42 17. Let G be the grammar S->aB/bA,A->a/aS/bAA,B->b/bS/aBB.obtain parse tree for the string aaabbabbba. 18. Find L(G)where G=({S},{0,1},{S->0S1,S->ε},S). 19. construct a context free Grammar for the given expression (a+b) (a+b+0+1)* 20. Let the production of the grammar be S-> 0B 1A, A-> 0 0S 1AA, B-> 1 1S 0BB.for the string 0110 find the right most derivation

43 Question Bank Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Branch:CSE Semester: 4 th Unit/Title: Pushdown Automata 1. Give an example of PDA. 2. Define the acceptance of a PDA by empty stack. Is it true that the language accept by a PDA by empty stack or by that of final state is different languages? 3. What is additional feature PDA has when compared with NFA? Is PDA superior over NFA in the sense of language acceptance? Justify your answer. 4. Explain what actions take place in the PDA by the transitions (moves) a. δ(q,a,z)={(p1,γ1),(p2, γ2),..(pm, γm)} and δ(q, ε,z)={(p1,γ1),(p2, γ2),..(pm,γm)}. b. What are the different ways in which a PDA accepts the language? Define them. Is a true that non deterministic PDA is more powerful than that of deterministic PDA? Justify your answer. 5. Explain acceptance of PDA with empty stack. 6. Is it true that deterministic push down automata and non deterministic push a. Down automata are equivalent in the sense of language of acceptances? Justify your answer. 7. Define instantaneous description of a PDA. 8. Give the formal definition of a PDA. 9. Define the languages generated by a PDA using final state of the PDA and empty stack of that PDA. 10. Define the language generated by a PDA using the two methods of accepting a language. 11. Define the language recognized by the PDA using empty stack. 12. For the Grammar G defined by the productions

44 S A/ B A 0A/ ε B 0B/ 1B/ ε Find the parse tree for the yields (i) 1001 (ii) Construct the Grammar with the productions E E+E E id Check whether the yield id + id + id is having the parse tree with root E or not. 14. What is ambiguous and unambiguous Grammar? 15. Show that E E+E/E*E/( E ) / id is ambiguous. 16. S as/ asbs/ ε is ambiguous and find the un ambiguous grammar. 17. Define the Instantaneous Descriptions ( ID ) 18. List out the applications of the pumping lemma for CFG. 19. State the pumping lemma for context-free languages. 20. Use the CFL pumping lemma to show each of these languages not to be context-free { aibjck i<j<k}

45 Question Bank Course Name: THEORY OF AUTOMATA & FORMAL LANGUAGES Course Code:TCS-403 Faculty :Mr. Dhajvir Singh Rai Branch:CSE Semester: 4 th Unit/Title: Turing Machines 1. Define a Turing Machine. 2. Define multi tape Turing Machine. 3. Explain the Basic Turing Machine model and explain in one move. What are the actions take place in TM? 4. Explain how a Turing Machine can be regarded as a computing device to compute integer functions. 5. Describe the non deterministic Turing Machine model. Is it true the non deterministic. 6. Turing Machine models are more powerful than the basic Turing Machines? (In the sense of language Acceptance). 7. Explain the multi tape Turing Machine mode. Is it more power than the basic turing machine? Justify your answer. 8. Using Pumping lemma Show that the language L={anbncn n>=1} is not a CFL. 9. What is meant by a Turing Machine with two way infinite tape. 10. Define instantaneous description of a Turing Machine. 11. What is the class of language for which the TM has both accepting and rejecting configuration? Can this be called a Context free Language? 12. The binary equivalent of a positive integer is stored in a tape. Write the necessary transition to multiply that integer by What i s the role of checking off symbols in a Turing Machine? 14. Mention any two problems which can only be solved by TM. 15. Draw a transition diagram for a Turing machine to compute n mod 2.

46 16. Difference between multi head and multi tape Turing machine. 17. Define Halting Problem. 18. Define LBA. 19. List out the hierarchy summarized in the Chomsky hierarchy. 20. DD raw a transition diagram for a Turing machine accepting of the following languages

47 SYLLABUS Subject Name : Data Base Management System Subject Code : TCS-404 Faculty :Mr. Saurabh Singh Semester: 4 th DATABASE MANAGEMENT SYSTEM Introduction: An overview of database management system, database system Vs file system,database system concepts and architecture, data models schema and instances, dataindependence and data base language and interfaces, Data definitions language, DML, OverallDatabase Structure. Data modeling using the Entity Relationship Model: ER model concepts, notation for ER diagram, mapping constraints, keys, Concepts of SuperKey, Candidate key, primary key, Generalization, aggregation, reduction of an ER diagrams totables, Extended ER model, relationships of higher degree. Relational data Model and Language: Relational data model concepts, integrity constraints:entity integrity, referential integrity, Keys constraints, Domain constraints, relational algebra,relational calculus, tuple and domain calculus. Introduction to SQL: Characteristics of SQL. Advantage of SQL.SQL data types and literals.types of SQL commands.sql operators and their procedure. Tables, views, Queries and subqueries. Aggregate functions. Insert, update and delete operations. Joins, Unions, Intersection,Minus, Cursors in SQL. Data Base Design & Normalization: Functional dependencies, normal forms, first, second, third normal forms, BCNF, inclusiondependences, loss less join decompositions, normalization using FD, MVD, and JDs, alternativeapproaches to database design. Transaction Processing Concepts: Transaction system, Testing of serializability,serializability of schedules, conflict & view serializable schedule, recoverability, Recoveryfrom transaction failures, log based recovery, checkpoints, deadlock handling. Concurrency Control Techniques: Concurrency control, locking Techniques for concurrencycontrol, Time stamping protocols for concurrency control, validation based protocol, multiplegranularity, Multi version schemes, Recovery with concurrent transaction. Text Books: 1 Korth, Silbertz, Sudarshan, Database Concepts, McGraw Hill, 5th Edition 2 Elmasri, Navathe, Fundamentals Of Database Systems, Addision Wesley,5thedition References: 1 Date C J, An Introduction To Database System, Pearson, 8th Edition. 2 Bipin C. Desai, An introduction to Database Systems, Galgotia Publication 3 Leon & Leon, Database Management System, Vikas Publishing House. 4 Majumdar& Bhattacharya, Database Management System, TMH 5 Ramakrishnan, Gehrke, Database Management System, McGraw Hill 6 Kroenke, Database Processing: Fundamentals, Design and Implementation, Pear

48 LESSON PLAN SEMESTER/YEAR : 4 th /2 nd COURSE: Database Management System S. No. Topic Name DEPARTMENT : CSE COURSE CODE : TCS-404 Reference/ No. Of Text Book/ Lectur Web es (R/T/W) Delivery Method 1. An overview of database management system, database T1,T2 1 Chalk &Talk system Vs file system 2. Database system concepts and architecture T1,T2 2 Discussion & PPT 3. Data models schema and instances, data independence T2 3 PPT and data base language and interfaces, 4. Data definitions language, DML, Overall Database T1,T2 2 PPT Structure. 7. ER model concepts, notation for ER diagram T1 2 Chalk &Talk Remarks 8. Mapping constraints, keys, Concepts of Super Key, T1 2 Chalk &Talk Candidate key, primary key 9. Generalization, aggregation, reduction of an ER T1 2 Chalk &Talk diagrams to tables 10. Extended ER model, relationships of higher degree. T1,R1 2 Chalk &Talk 11. Relational data model concepts T1 1 Chalk &Talk 12. Integrity constraints: entity integrity, referential integrity T1,R1 2 Chalk &Talk 13. Keys constraints, Domain constraints T1 1 Chalk &Talk 14. Relational algebra, relational calculus, tuple and domain T1 2 Chalk &Talk calculus. 15. Characteristics of SQL, Advantage of SQL, SQL data T1,R1 2 Chalk &Talk types and literals. 16. Types of SQL commands. SQL operators and their T1 1 PPT procedure. 17. Tables, views, Queries and sub queries. T1 2 PPT 18. Aggregate functions. Insert, update and delete T1, R1 2 PPT operations. 19. Joins, Unions, Intersection, Minus, Cursors in SQL. R1 2 Chalk &Talk 20. Data Base Design & Normalization: Functional R1 1 PPT dependencies 21. Normal forms, first, second, third normal forms T1,R1 3 PPT 23. BCNF, inclusion dependences, loss less join T1 3 PPT decompositions 24. Normalization using FD, MVD, and JDs T1,R1 1 Chalk &Talk 25. Alternative approaches to database design. T1 1 Chalk &Talk

49 26. Transaction Processing Concepts: Transaction system T1,T2 1 PPT 27. Testing of Serializability T1,R2 1 PPT 28. Serializability of schedules T1,R1 1 Chalk &Talk 29. Conflict & view serializable schedule T1,T2 2 Chalk &Talk 30. Recoverability, Recovery from transaction failures T1,R3 1 Chalk &Talk 31. Log based recovery, checkpoints T1 2 Chalk &Talk 32. Deadlock handling T1,T2 1 Chalk &Talk 33. Concurrency Control Techniques: Concurrency control T1 1 Chalk &Talk 34. Locking Techniques for concurrency control T2,R2 1 Chalk &Talk 35. Time stamping protocols for concurrency control T2 2 PPT 36. Validation based protocol, multiple granularity T2 2 Chalk &Talk 37. Multi version schemes T2,R4 2 Chalk &Talk 38. Recovery with concurrent transaction. T2 1 PPT Total Lectures: 60 REMARKS/RECOMMENDATIONS FOR FUTURE: EXTRA CLASS TAKEN (IF ANY): TEXT BOOKS: [T1] Korth, Silbertz, Sudarshan, Database Concepts, McGraw Hill, 5th Edition [T2] Elmasri, Navathe, Fundamentals Of Database Systems, Addision Wesley,5th edition REFERENCE BOOKS: [R1] Date C J, An Introduction To Database System, Pearson, 8th Edition. [R2] Bipin C. Desai, An introduction to Database Systems, Galgotia Publication [R3] Majumdar & Bhattacharya, Database Management System, TMH [R4] Ramakrishnan, Gehrke, Database Management System, McGraw Hill Signature of HOD: Date: