Sequential Logic Synthesis

Transcription

1 Sequential Logic Synthesis Logic Circuits Design Seminars WS2010/2011, Lecture 9 Ing. Petr Fišer, Ph.D. Department of Digital Design Faculty of Information Technology Czech Technical University in Prague Evropský sociální fond Praha & EU: Investujeme do vaší budoucnosti

2 Sequential Synthesis Tasks: State minimization State assignment Combinational logic synthesis & optimization Retiming FSM extraction FSM composition/decomposition PI-SCN-9, ČVUT FIT, Petr Fišer,

3 Sequential Synthesis Assumptions: Synchronous model Mealy/Moore type D flip-flops Single clock No direct combinational feedbacks No clock gating PPIs PIs Combinational Logic Register (DFFs) CLK POs PPOs PI-SCN-9, ČVUT FIT, Petr Fišer,

4 Sequential Circuits Models State-based model Description Finite-State Machine (FSM) Berkeley KISS format (table) Mealy / Moore type Can be incompletely specified some transitions are missing (DCs) Can be non-deterministic transitions to two or more states under the same condition Operations State minimization State encoding Determinisation Pros / Cons + explicit state notion - no area and delay notion Structural model Description Netlist Berkeley BLIF format Mealy / Moore type implementation-specific Can be incompletely specified but not in the final realization Cannot be non-deterministic determinisation necessary Operations Combinational logic optimization Retiming Pros / Cons - no state notion + explicit area and delay notion PI-SCN-9, ČVUT FIT, Petr Fišer,

5 FSM Description Formally: X set of input symbols Y set of output symbols S set of states : X S S state transition function : X S Y output function (Mealy) : S Y output function (Moore) S 0 initial state Practice: Transition (& output) table Graph PI-SCN-9, ČVUT FIT, Petr Fišer,

6 Non-Deterministic FSM Description Formally: X set of input symbols Y set of output symbols S set of states X S S state transition relation move to a set of states X S Y output relation (Mealy) generate a set of outputs S Y output function (Moore) S 0 initial state Practice: Incompletely specified KISS???? PI-SCN-9, ČVUT FIT, Petr Fišer,

7 Non-Deterministic vs. Incompletely Specified FSMs Non-deterministic FSM From a given state, under a given input symbol, we go to more states simultaneously these transitions happen when moving to the structural description, we need to determinize the FSM Incompletely specified FSM From a given state, under a given input symbol, we can go to any state these transitions may never happen when moving to the structural description, we can arbitrarily exploit these DCs and choose the most advantageous transition Incompletely specified FSM (2) From a given state, under a given input symbol, we can go to any state, from a given set these transitions do not alter the FSM operation when moving to the structural description, we can arbitrarily exploit these DCs and choose the most advantageous transition PI-SCN-9, ČVUT FIT, Petr Fišer,

8 FSM vs. FA Finite State Machine (FSM) Accepts input symbols, produces output symbols No terminal state (X, Y, S, S 0,, ) Finite Automaton Accepts input symbols, possibly ends up in a terminal state Does not produce any output accepts or does not accept an input sequence (X, Y, S, S 0,,, F) PI-SCN-9, ČVUT FIT, Petr Fišer,

9 Sequential Synthesis Source FSM State minimization State encoding Minimized FSM Encoded FSM Combinational logic extraction and synthesis Synthesized sequential circuit Retiming Sequential circuit optimized for delay PI-SCN-9, ČVUT FIT, Petr Fišer,

10 State Minimization Completely specified deterministic FSMs no don t cares Polynomial-time exact algorithm Incompletely specified deterministic FSMs don t cares in the FSM specification NP-hard Non-deterministic FSMs NP-hard PI-SCN-9, ČVUT FIT, Petr Fišer,

11 State Minimization Completely Specified FSMs Theorem Two states are equivalent if and only if they lead to identical outputs and their next-states are equivalent State equivalency relation is transitive classes of equivalency may be determined Algorithm determining the equivalence classes 1. All states are in one equivalence class 2. Iteratively split the classes Two approaches: a) Check transitions from states in the class implication table. O(n 2 ) b) Check transitions into states in the class Hopcroft s algorithm. O(n.log n) 3. Convergence point: no further splitting is possible the equivalence classes form new states Note: the minimum FSM is unique PI-SCN-9, ČVUT FIT, Petr Fišer,

12 State Minimization Incompletely Specified FSMs Theorem Two states are compatible if and only if: for any input sequence applied to the FSM starting from these two states, the output sequences match Two states are compatible if and only if: they lead to identical outputs their next states are compatible State compatibility is not an equivalence relation Algorithm determining the compatibility classes we are looking for maximum compatibility classes can be easily converted to the maximum clique problem NP-hard approximate methods (STAMINA) Note: The minimum FSM is not unique PI-SCN-9, ČVUT FIT, Petr Fišer,

13 State Encoding Generally: Binary encoding The least number of flip-flops (log N) Gray code Any two adjacent states have the Hamming distance 1 used in asynchronous circuits design One-hot (1 of N) N flip-flops required Any two states have the Hamming distance 2 fail-safe designs The combinational logic is usually smaller Moore-type controllers M of N encoding Compromise PI-SCN-9, ČVUT FIT, Petr Fišer,

14 State Encoding Classes of methods: 1. Symbolic optimization two-level model Multi-valued two-level minimization used The final encoding is determined from the minimized design (PLA) formulation of a constrained encoding problem 2. Targeted to multi-level optimization Trying to find a good encoding for multi-level implementation Looking for possible cube/kernel extractions No big success In SIS: NOVA, JEDI PI-SCN-9, ČVUT FIT, Petr Fišer,

15 Non-Deterministic FSM Determinisation Non-deterministic and deterministic FSMs are equivalent [Rabin 59] Every non-deterministic FSM can be determinised yielding up to 2 N deterministic FSM states Straightforward way: one-hot encoding PI-SCN-9, ČVUT FIT, Petr Fišer,

16 Retiming Fully synthesized sequential circuit supposed Retiming moves the registers in the circuit affects area (number of registers may change) affects delay (move registers from critical path) Preserves the network topology Preserves the combinational logic Exact retiming algorithms are polynomial-time PI-SCN-9, ČVUT FIT, Petr Fišer,

17 Retiming Retiming of a network node (gate) Move registers from the input to the output Move registers from the output to the input & & PI-SCN-9, ČVUT FIT, Petr Fišer,

18 Algorithm Retiming Transform the circuit to a weighted cyclic graph Nodes (vertices) are gates Labeled by gate delays Edges are signals Weights of edges are numbers of registers in the path Circuit delay = longest path without registers Goal: minimize the longest path, while keeping constraints PI-SCN-9, ČVUT FIT, Petr Fišer,

19 Retiming Operation: Transform edge weights, so that w (u, v) = w(u, v) + r(v) r(u) where r(i) is any integer (even negative) node labeling (retardation) Valid retiming: all edge weights are positive Example: r(u) = -1 r(v) = -1 r(w) = 0 r(x) = 0 PI-SCN-9, ČVUT FIT, Petr Fišer,

20 State Extraction Recover the FSM from a netlist by Reachability analysis 1. Start from an initial state 2. Given a state, determine which states are reachable for all input symbols 3. Given a state subset, determine the reachable state subset 4. Stop when converged PI-SCN-9, ČVUT FIT, Petr Fišer,