Advanced Digital Logic Design EECS 303
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1 Advanced Digital Logic Design EECS Teacher: Robert Dick Office: L477 Tech Phone:
2 Outline 1. Finite state machines Robert Dick Advanced Digital Logic Design
3 Section outline 1. Finite state machines 3 Robert Dick Advanced Digital Logic Design
4 FSM design overview State diagram for FSM State table Derive state variable and output functions Simplify and implement the functions 4 Robert Dick Advanced Digital Logic Design
5 Sometimes, system specified in way that naturally maps to FSM Sometimes, path from specification to FSM is unclear Transform the specifications so they can naturally be represented as FSMs E.g., regular expression NFA DFA FSM It s fine to go directly to FSM Use transformations when they help you 5 Robert Dick Advanced Digital Logic Design
6 Word description to state diagram Design a vending machine controller that will release (output signal r) an apple as soon as 30 have been inserted The machine s sensors will clock your controller when an event occurs. The machine accepts only dimes (input signal d) and quarters (input signal q) and does not give change When an apple is removed from the open machine, it indicates this by clocking the controller with an input of d The sensors use only a single bit to communicate with the controller 6 Robert Dick Advanced Digital Logic Design
7 Word description to state diagram We can enumerate the inputs on which an apple should be released For d, i = 0, for q, i = 1 ddd + ddq + dq + qd + qq d(dd + dq + q) + q(d + q) d(d(d + q) + q) + q(d + q) 0(0(0 + 1) + 1) + 1(0 + 1) 7 Robert Dick Advanced Digital Logic Design
8 Word description to state diagram 0(0(0 + 1) + 1) + 1(0 + 1) 0 1 A/0 0 B/0 0 C/ D/1 1 E/ Robert Dick Advanced Digital Logic Design
9 Word description to state diagram 0(0(0 + 1) + 1) + 1(0 + 1) X 0 C/0 X A/0 0 B/0 1 D/1 1 E/0 X 8 Robert Dick Advanced Digital Logic Design
10 Word description to state diagram 0(0(0 + 1) + 1) + 1(0 + 1) X 0 C/0 X A/0 0 B/0 1 D/1 1 8 Robert Dick Advanced Digital Logic Design
11 State diagram to state table next current state state i=0 i=1 output (r) A B E 0 B C D 0 C D D 0 D A A 1 E D D 0 9 Robert Dick Advanced Digital Logic Design
12 Section outline 1. Finite state machines 10 Robert Dick Advanced Digital Logic Design
13 Implication chart algorithm 1 Construct implication chart, one square for each combination of states taken two at a time. 2 Square labeled S i, S j, if outputs differ than square gets X (0). Otherwise write down implied state pairs for all input combinations. 3 Advance through chart top-to-bottom and left-to-right. If square S i, S j contains next state pair S m, S n and that pair labels a square already labeled X (0), then S i, S j is labeled X. 4 Continue executing Step 3 until no new squares are marked with X (0). 5 For each remaining unmarked square S i, S j, then S i and S j are equivalent. 11 Robert Dick Advanced Digital Logic Design
14 Implication chart minimization B BC, DE C BD, DE CD D E BD, DE CD 1 0 A B C D 12 Robert Dick Advanced Digital Logic Design
15 Implication chart minimization B BC, DE C BD, DE CD D E BD, DE CD 1 0 A B C D D any other state 12 Robert Dick Advanced Digital Logic Design
16 Implication chart minimization B 0 C 0 0 D E A B C D 13 Robert Dick Advanced Digital Logic Design
17 Implication chart minimization B 0 C 0 0 D E A B C D Easy Merge C and E 13 Robert Dick Advanced Digital Logic Design
18 Minimization can be more complicated Incompletely specified machines are difficult to minimize Therefore, some merges can block others Need a formulation amenable to backtracking 14 Robert Dick Advanced Digital Logic Design
19 Incompletely specified Moore state reduction s s 0 1 q A D B 0 B X A X C A X 1 D B C 1 Consider merging A and B or B and C 15 Robert Dick Advanced Digital Logic Design
20 Section outline 1. Finite state machines 16 Robert Dick Advanced Digital Logic Design
21 Assign values to states Keep state variable functions and output variable functions simple Allow cubes to be reused among different state variable functions 17 Robert Dick Advanced Digital Logic Design
22 is difficult Assuming p states and k state variables (2 k )! (2 k possible assignments p)! Let s simplify that, assume p is an even power of two and k = lg 2 p then, 2 k = p 18 Robert Dick Advanced Digital Logic Design
23 is difficult Therefore, we have p! (p p)! = p! 0! = p! /1 = p! possible assignments... and that s a loose bound p! O (2 p ) has a huge solution space It s also a hard problem 19 Robert Dick Advanced Digital Logic Design
24 Allow the extraction of common cubes for different state variable functions State variables States connected by transitions should be adjacent Output functions States with equivalent outputs should be adjacent Heuristic assignment popular Mustang is popular Attraction between states based on ability to extract common cubes 20 Robert Dick Advanced Digital Logic Design
25 Can do reasonably good state assignment by following guidelines. Make states have adjacent assignments (differing by only one bit) if: They have the same next (child) state in the state diagram for the same input They have the same previous (parent) state in the state diagram They have the same output for the same input 21 Robert Dick Advanced Digital Logic Design
26 State map Recall that Karnaugh maps help us visualize adjacency Use state maps to visualize state adjacency Recall that we have n states, so we require lg 2 (4) bit state variables lg 2 (4) = 2 What if we hadn t done state minimization? Five states three state variable bits required 22 Robert Dick Advanced Digital Logic Design
27 State map A C E G 1 B D F H a, b, and c are state variable bits A, B, C, etc. are states State maps help select adjacent assignments for adjacent states 23 Robert Dick Advanced Digital Logic Design
28 0(0(0 + 1) + 1) + 1(0 + 1) X 0 C/0 X A/0 0 B/0 1 D/ Robert Dick Advanced Digital Logic Design
29 guidelines States with same child for same input: {B, C} States with same parent: {B, C}, {C, D} States with same output: {A, B, C} Prioritize: {B, C}, {C, D}, {A, B, C}, etc. 25 Robert Dick Advanced Digital Logic Design
30 0 1 0 A B 1 D C 26 Robert Dick Advanced Digital Logic Design
31 Symbolic state state table next current state state i=0 i=1 output (r) A B C 0 B C D 0 C D D 0 D A A 1 27 Robert Dick Advanced Digital Logic Design
32 State table next current state (j state (jk) k + ) i=0 i=1 output (r) Robert Dick Advanced Digital Logic Design
33 Section outline 1. Finite state machines 29 Robert Dick Advanced Digital Logic Design
34 Logic function definitions Use Karnaugh maps (or other methods) to simplify functions j + (j, k, i) k + (j, k, i) r(j, k) 30 Robert Dick Advanced Digital Logic Design
35 State variable and output simplification Robert Dick Advanced Digital Logic Design
36 State variable and output simplification Robert Dick Advanced Digital Logic Design
37 State variable and output simplification Robert Dick Advanced Digital Logic Design
38 Implementation Implement the state variable functions in combinational logic Use sequential elements along feedback paths Implement the output variable functions in combinational logic 34 Robert Dick Advanced Digital Logic Design
39 Moore block diagram outputs combinational logic sequential elements feedback combinational logic inputs 35 Robert Dick Advanced Digital Logic Design
40 Mealy block diagram sequential elements outputs feedback combinational logic inputs 36 Robert Dick Advanced Digital Logic Design
41 Outline 1. Finite state machines Robert Dick Advanced Digital Logic Design
42 with Don t-cares Can use advanced technique introduced in previous lecture Find the maximal compatibles Use these to generate the prime compatibles Write expression in POS form Multiply to get SOP form Formulate as a binate covering problem This technique is optimal but difficult for incompletely specified machines is a hard problem 38 Robert Dick Advanced Digital Logic Design
43 Incompletely specified Moore state reduction s + s 0 1 q A D B 0 B X A X C A X 1 D B C 1 From Hachtel and Somenzi s Logic Synthesis and Verification Algorithms 39 Robert Dick Advanced Digital Logic Design
44 Incompletely specified Moore state reduction s + s 0 1 q A D B 0 B X A X C A X 1 D B C 1 B 1 C 0 1 D 0 0 AB A B C 39 Robert Dick Advanced Digital Logic Design
45 Maximal compatibles Choosing the compatible state sets is not straight-forward Some combinations block potential future combinations Know conflicting states from the compatibility table 40 Robert Dick Advanced Digital Logic Design
46 Compatibles and implications B 1 C 0 1 D 0 0 AB A B C {C, D}, {B, C}, {A, B} 41 Robert Dick Advanced Digital Logic Design
47 Class sets The combination of a pair of states may require the combination of another state pair Thus, using the maximal compatibles is insufficient Need additional prime compatibles that have smaller class sets Starting from the maximal compatibles, which are primes, generate other primes In order of decreasing compatible size, if the compatible has a non-empty class set, enter all subsets that are not already contained in other prime compatibles with empty class sets in the table 42 Robert Dick Advanced Digital Logic Design
48 Prime compatibles B 1 C 0 1 D 0 0 AB A B C A, B B, C C, D AB D 43 Robert Dick Advanced Digital Logic Design
49 Prime compatible selection Once the prime compatibles are known, it is necessary to select a subset that Has minimal number of selected prime compatibles Covers all states Would be unate covering Contains all class sets implied by the selected prime compatibles This makes it binate covering Recall unate covering, similar solution works Branch and bound 44 Robert Dick Advanced Digital Logic Design
50 Binate covering {C, D} {A, B} 45 Robert Dick Advanced Digital Logic Design
51 Binate covering {C, D} {A, B} {C, D} + {A, B} 45 Robert Dick Advanced Digital Logic Design
52 Binate covering {C, D} {A, B} {C, D} + {A, B} {A, B} need to include A ({A, B} + {B, C}) need to include B ({B, C} + {C, D}) need to include C ({C, D} + {D}) need to include D ({C, D} + {A, B}) {C, D} class set requirements 45 Robert Dick Advanced Digital Logic Design
53 Binate covering J 1 = {A, B} J 2 = ({A, B} + {B, C}) J 3 = ({B, C} + {C, D}) J 4 = ({C, D} + {D}) J 5 = ({C, D} + {A, B}) 46 Robert Dick Advanced Digital Logic Design
54 Binate covering J 1 = {A, B} J 2 = ({A, B} + {B, C}) J 3 = ({B, C} + {C, D}) J 4 = ({C, D} + {D}) J 5 = ({C, D} + {A, B}) term prime compatible A, B B, C C, D D J 1 1 J J J J Robert Dick Advanced Digital Logic Design
55 Binate covering term prime compatible A, B B, C C, D D J 1 1 J J J J Find a set of columns, S, such that, for every row A 1-column in the row is in S or a 0-column in the row is not in S 47 Robert Dick Advanced Digital Logic Design
56 Additional examples CS NS(I) 0 1 Out A A C 0 B B B X C A C 1 48 Robert Dick Advanced Digital Logic Design
57 Today s Topics FSM design example (trying to use more examples) with don t-cares 49 Robert Dick Advanced Digital Logic Design
58 General CAD references If you will be working in digital circuit design, bookmark these sites Designers talk about the current state of CAD and circuit design Electronics design trade journal Won t find current research Will find industry trends 50 Robert Dick Advanced Digital Logic Design
59 Outline 1. Finite state machines Robert Dick Advanced Digital Logic Design
60 Recommended reading Jayaram Bhasker. A VHDL Primer. Prentice-Hall, NJ, 1992 Chapter 1 Chapter 2 52 Robert Dick Advanced Digital Logic Design
61 Next lecture Design representations VHDL for combinational and sequential systems 53 Robert Dick Advanced Digital Logic Design
1 Construct implication chart, one square for each combination of states. 2 Square labeled S i, S j, if outputs differ than square gets X (0).
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