ECE 2300 Digital Logic & Computer Organization. More Finite State Machines
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1 ECE 2300 Digital Logic & Computer Organization Spring 2018 More Finite State Machines Lecture 9: 1
2 Announcements Prelab 3(B) due tomorrow Lab 4 to be released tonight You re not required to change partner(s) from this lab onwards Lecture 9: 2
3 Example: Procedural Assignments reg Y, Z; (posedge clk) begin Y = ~Z; Z = A & B; end Blocking assignments = reg Y, Z; (posedge clk) begin Y <= ~Z; Z <= A & B; end Nonblocking assignments A B A B Z Y Z Y Lecture 9: 3
4 FSM Design Procedure (1) Understand the problem statement and determine inputs and outputs (2) Identify states and create a state diagram (3) Determine the number of required D FFs (4) Implement combinational logic for outputs and next state This lecture (5) Simulate the circuit to test its operation Lecture 9: 4
5 Example FSM: Pattern Detector Monitors the input, and outputs a 1 whenever a specified input pattern is detected Example: Output a 1 whenever 111 is detected on the input over 3 consecutive clock cycles Overlapping patterns also detected ( ) Input In Output Out Reset causes FSM to start in initial state Clock input not shown (always present) Lecture 9: 5
6 State Diagrams Reset Moore Init Got1 Got11 Got111 Out = 1 Reset Mealy Init Got1 Got11 Out = 1 Lecture 9: 6
7 Transition/Output Table Shows the next state (S * ) and output values for each combination of current state (S) and inputs Used to derive the minimized state transition (S * ) and output Boolean equations Lecture 9: 7
8 Reset Moore Transition/Output Table 1 Init Got1 Got11 Got111 Out = 1 Current State (S) Next State (S * ) Out Init Init Got1 0 Got1 Init Got11 0 Got11 Init Got111 0 Got111 Init Got111 1 Version 1: uses descriptive state names Lecture 9: 8
9 Reset Moore Transition/Output Table 2 Init Got1 Got11 Got111 Out = 1 [00] [01] [10] [11] S1 S0 S1 * S0 * Out Version 2: uses state binary encodings Lecture 9: 9
10 Minimized Equations for S* and Out S1 S0 S1 * S0 * Out Lecture 9: 10
11 Mealy Transition/Output Table 1 Reset Init Got1 Got11 Out = 1 Current State (S) Next State (S * ), Out Init Init, 0 Got1, 0 Got1 Init, 0 Got11, 0 Got11 Init, 0 Got11, 1 Version 1: uses descriptive state names Lecture 9: 11
12 Mealy Transition/Output Table 2 Reset Init Got1 Got11 [00] [01] [10] Out = 1 S1 S0 S1 * S0 *, Out , 0 0 1, , 0 1 0, , 0 1 0, 1 Version 2: uses state binary encodings Lecture 9: 12
13 Minimized Equations for S * and Out S1 * S0 *, Out S1 S , 0 0 1, , 0 1 0, , 0 1 0, 1 Lecture 9: 13
14 FSMs in Verilog <module statement> <input and output declarations> <reg declarations> <parameter or typedef statement> <always block for next state> Suggested coding style for FSM <always block for output> <always block for state FFs> endmodule Lecture 9: 14
15 Reset Moore FSM in Verilog Init Got1 Got11 Got111 Out = 1 [00] [01] [10] [11] module PatDetectMoore (Clk, In, Reset, Out); input Clk, In, Reset; output Out; reg Out; reg [1:0] Scurr, Snext; parameter [1:0] Init = 2'b00, Got1 = 2'b01, Got11 = 2'b10, Got111 = 2'b11; Lecture 9: 15
16 Reset Moore FSM in Verilog Init Got1 Got11 Got111 Out = 1 [00] [01] [10] [11] (In, Scurr) begin case (Scurr) Init: if (In == 1) Snext = Got1; else Snext = Init; Got1: if (In == 1) Snext = Got11; else Snext = Init; Got11: if (In == 1) Snext = Got111; else Snext = Init; Got111: if (In == 1) Snext = Got111; else Snext = Init; default: Snext = Init; endcase end next state comb logic Lecture 9: 16
17 Reset Moore FSM in Verilog Init Got1 Got11 Got111 Out = 1 [00] [01] [10] [11] (Scurr) if (Scurr == Got111) Out = 1; else ; output comb logic (posedge Clk) if (Reset == 1) Scurr <= Init; else Scurr <= Snext; clock state FFs (synchronous reset) endmodule Lecture 9: 17
18 Reset Mealy FSM in Verilog Init Got1 Got11 [00] [01] [10] module PatDetectMealy (Clk, In, Reset, Out); input Clk, In, Reset; output Out; Out = 1 reg Out; reg [1:0] Scurr, Snext; parameter [1:0] Init = 2'b00, Got1 = 2'b01, Got11 = 2'b10; Lecture 9: 18
19 Reset Mealy FSM in Verilog (In, Scurr) begin case (Scurr) Init: if (In == 1) Snext = Got1; else Snext = Init; Got1: if (In == 1) Snext = Got11; else Snext = Init; Got11: if (In == 1) Snext = Got11; else Snext = Init; default: Snext = Init; endcase end Init Got1 Got11 [00] [01] [10] Out = 1 next state comb logic Lecture 9: 19
20 Reset Mealy FSM in Verilog Init Got1 Got11 [00] [01] [10] (Scurr, In) if ((Scurr == Got11) && (In == 1)) Out = 1; else ; Out = 1 output comb logic (posedge Clk) if (Reset == 1) Scurr <= Init; else Scurr <= Snext; clock state FFs (synchronous reset) endmodule Lecture 9: 20
21 Example FSM: Pushbutton Lock Two pushbutton inputs, X1 and X2 One output, UL ( Unlock ) UL = 1 when X1 is pushed, followed by X2 being pushed twice (X1, X2, X2) Represent X1 and X2 as two bit input 00: neither button pushed 10: X1 pushed 01: X2 pushed 11: both pushed, reset the lock Lecture 9: 21
22 Pushbutton Lock: Moore State Diagram Output: UL=1 with sequence X1, X2, X2 Input: 00 (neither), 10 (X1), 01 (X2), 11 (reset) X1 X1-X2 UL = 0 UL = 0 [01] [10] Init UL = 0 [00] 1 1 X1-X2-X2 UL = 1 [11] Lecture 9: 22
23 Moore Transition/Output Table 1 Current State (S) Input 0 0 (neither) Next State (S*) Input 0 1 (X2) Input 1 0 (X1) Input 1 1 (reset) Init Init Init X1 Init 0 X1 X1 X1-X2 Init Init 0 X1-X2 X1,X2 X1-X2-X2 Init Init 0 X1-X2-X2 X1-X2-X2 X1-X2-X2 X1-X2-X2 Init 1 Version 1: uses descriptive state names UL Lecture 9: 23
24 Moore Transition/Output Table 2 S1 S0 Input 0 0 Input 0 1 S1* S0* UL Input 1 0 Input Version 2: uses state binary encodings Lecture 9: 24
25 Pushbutton Lock: Mealy State Diagram Output: UL=1 with sequence X1, X2, X2 Input: 00 (neither), 10 (X1), 01 (X2), 11 (reset) 0 0 / UL=0 1 0 / UL=0 X1 0 1 / UL=0 X1-X2 [01] [10] / UL= / UL=0 0 1 / UL=0 0 0 / UL= / UL=0 Init [00] 1 1 / UL=0 X1-X2-X2 [11] / UL=1 Lecture 9: 25
26 Mealy Transition/Output Table S1* S0*, UL S1 S0 Input 0 0 Input 0 1 Input 1 0 Input , 0 0 0, 0 0 1, 0 0 0, , 0 1 0, 0 0 0, 0 0 0, , 0 1 1, 0 0 0, 0 0 0, , 1 1 1, 1 1 1, 1 0 0, 0 uses state binary encodings Lecture 9: 26
27 FSM for D Flip-Flop D = 0 D CLK Q State0 State1 Q = 0 Q = 1 [0] [1] D = 1 D = 0 D = 1 Input: D Output: Q Clock is implicit in the state diagram Moore state diagram Lecture 9: 27
28 Analyzing the FSM S0* S1* What does this FSM do? Lecture 9: 28
29 Transition and Output Equations S 0 * = S 1 * = Out = S0* S1* Lecture 9: 29
30 1. Complete the transition/output table and state diagram Exercise: State Diagram 2. Identify the functionality of the FSM (Hint: Pattern detector?) S 0 * = In S 1 * = In S 1 S 0 +In S 0 Out = S 1 S 0 [00] [11] Out = 1 S1 S0 [01] [10] S1* S0* Out Lecture 9: 30
31 Next Time H&H 2.9, 4.6, 4.9 More FSMs Timing, Clocking Lecture 9: 31
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