REFERENCED BIT RESERVE SCHEME WITH BIT MASKING FOR TEST DATA COMPRESSION FOR IP EMBEDDED CORES

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1 International Journal of Mechanical Engineering and Technology (IJMET) Volume 8, Issue 8, August 2017, pp , Article ID: IJMET_08_08_060 Available online at ISSN Print: and ISSN Online: IAEME Publication Scopus Indexed REFERENCED BIT RESERVE SCHEME WITH BIT MASKING FOR TEST DATA COMPRESSION FOR IP EMBEDDED CORES Chakrapani K, Muthaiah R School of Computing, SASTRA University, Thanjavur, Tamil Nadu, India ABSTRACT As innovation procedures scale up and plan complexities develop, framework onchip incorporation keeps on rising quickly. As indicated by these patterns, expanding test information volume is viewed as a potential overhead in the testing business. In this paper, another test information Compression technique based on Referenced Bit Reserve Scheme with Bit Masking (RBR) Code is displayed. The essential motivation of Bit-Mask is to make a record of confounded qualities and their respective positions to pack unique number of guidelines; this could be utilized only or joined along with the reference directions for unraveling the code words. In this work, a reference set with variable veil numbers are connected, which were used with the RBR calculation to decrease the code word length with increased recurrence directions. Additionally, a novel RBR choice calculation was proposed to expand the guideline coordinate rates. For this procedure, an RBR calculation is intended to lessen the calculation time of encoding calculation. This coding strategy encodes 2n perfect or contrarily better instance into just one test data portion or multiple experimental data portions. The recreation result demonstrates that the compression ratio and calculation time is decreased. From the analysis of Experimental inferences indicate that the propounded RBR technique enhances a compression ratio and a test time on International Symposium on Circuits and Systems '89 circuits in multifarious cases compared to the inferences of the previous work without a substantial burden on the hardware. Key words: Intellectual Property, System On Chip, Run-length-based codes, Word reference codes, Actual codes. Cite this Article: Chakrapani K, Muthaiah R, Referenced BIT Reserve Scheme with BIT Masking for Test Data Compression for IP Embedded Cores, International Journal of Mechanical Engineering and Technology, 8(8), 2017, pp INTRODUCTION IP cores are utilized as a part of present SOCs. Examining an SOC comprised of multiple IP cores is exceptionally troublesome in the auxiliary data of the keys may be close to bottom level. Under such circumstances, no other alteration can be connected to the base or their scan editor@iaeme.com

2 Referenced BIT Reserve Scheme with BIT Masking for Test Data Compression for IP Embedded Cores connectives, and even self-regulating generation of test pattern or defect imitation mechanisms can t be used. In the mid of testing, the cores should be connected with some pre-figured test sets (perhaps very compacted) which are given by the core vendors. Now one compression test information strategy which I based on code appears the perfect decision for decreasing the test information. A single chip constitutes a System On Chip (SoC) which is a whole framework that might comprise of intellectual property (IP) cores. Attributable to the exclusive way of cores and also it is a great trouble to improve the test regularly. Depending on Soc Test system architecture some predefined characterized tests are given to the client by the intellectual property cores. For a particular scheduled testing reason, the dissembling of the core is done by the test wrapper, whereas test access mechanism (TAM) provides the service of a correspondence bus to bus test information from sink to source. Test source gives some vectors related to test, and it could be either off-chip or on-chip. This technique is to apply test designs from the distance that is without a physical contact from automatic test equipment (ATE) and the Test sink can be installed on-chip signature analyzer or off-chip automatic test equipment that will act as a source to yield examination with put away reaction. Here that is in this work, there is an arrangement by the test vectors which is provided by the intellectual property core in which a test is mentioned indirectly, and also there is an acceptance in which every core should have at least one test. This paper is organized as follows: Introduction Previous Research Proposed Testing Architecture - Reference Bit Reserve (RBR) Algorithm - Outcome and Discussion Conclusion 2. PREVIOUS RESEARCH In the previous one decade, specialists have proposed diverse testing techniques for VLSI circuits. The written works related to the proposed work have been talked about to a superior degree in this segment. To encode test 3D shapes [1], will Code-based test information compressions utilize the information pressure codes. This process includes packing the first information into images, and afterward replacing every image with a code word to frame the compacted information. With the help of decoder which changes every code-word in the compacted information to the relating image we can achieve the decompression. There are three principle sorts of code based vector compressions. 1. Run-length-based codes 2. Word reference codes 3. Actual codes Jas and Touba have initially given a plan in which run-length codes that are encoded keeps on running of 0 s which utilizes altered stretch code words [2]. Then To abbreviate the length of the codes, Chandra and Chakrabarty given a plan in which Golomb codes [20] that are encoded keeps running of 0 s but with variable-length code words [3]. [4] and [5] also improved the stretch of the codes in view of the likelihood transportation of the length of the run-length. Mostly, If the coding runs with both 0 s and 1 s might be superior when compared to the coding which only keeps running with 0 s [6-9]. As of late, [10] exhibited another example run-length pressure strategy that encoded 2n keeps running of examples that are good or conversely perfect, either inside a solitary test information fragment or over numerous test information portions. At the point when every single conceivable image doesn't happen in the information, then for compression we can the codes which refer the word. A strategy is proposed by the Sismanoglou et al. which is concentrated to upgrade the pressure proportion CR [11] by the reuse of parts of the lexicon sections. Measurable coding editor@iaeme.com

3 Chakrapani K, Muthaiah R doles out longer code words to images that happen less often as possible, and shorter ones to those that happens pretty much of the time. an ideal Huffman coding[18,19] is proposed by the X. Kavousianos et al. which enhanced the CR [12]. Basically there are three sorts of test get to structures. 1. Multiplexing, 2. Conveyance and 3.Daisy-chaindesign. By utilizing these structures, a test transport and Test Rail design. A novel way to deal with lessen the test time of SoC is proposed in [13], which depends on hereditary neighborhood seek calculation. The proposed strategy determines the issue of TAM under the confinement, for example, centre bunch and centre position group. The strategy permits the framework intended to enhance TAM and settles on proper decisions. Another way to deal with decreased test time in view of the data transmission coordinating idea, is underlining the multi-recurrence TAM plan. Utilizing the technique for serialization and de-serialization, a high data transfer capacity source and sink are associated with the low transmission capacity source and sink until transfer speed matches. In the second approach, the issue with the post-silicon approval technique, which has restricted investigate get to transfer speed to get to interior signs, is depicted in [15]. A TAM for the different indistinguishable centers is appeared in [16], which use the uniform way of the centre and applies test at the same time, which minimizes test time for centre under test. In another approach, testing of different indistinguishable centre is done in a manner that, rather than taking run of the mill test reaction information from the centre, it takes a greater part based esteem. The TAM design presented in this work depends on chip comparator and lion's share analyzer. Minimization of the test application time for SOC which it is displayed in[17] can be fastened by the reconfiguration of the numerous sweeps. Integration of the test scheduling and the test access mechanism (TAM) design can considerably increase the TAT. Previously, to attain the optimal test time the flexible-width TAM architecture fully uses the resources. Nevertheless, based on the requirements of test access mechanism assignments, the core layout design may not be modified and to increase the complexity it might need the connectivity of random TAM wires to a core. To get a solution to our problem, test access mechanism design and the arrangement of layout of SOC are combined in this paper. In the same way, from the efficient TAM assignment to cores we can deduce the core structure. Therefore as a consequence of such an ideal solution of SOC cores bifurcation of TAM wires is enabled and also wired in a way such that the chances of getting back this intermittent TAM wires into a single core is outstandingly lowered Novelty of the Work In this study, on the basis of test data compression strategy a new world dictionary (named as a reference set)is shown which gives a remarkable compression to pre-calculated test sets and results in the extensive decrease in testing time. The bit mask based word references are exactly chosen in which the dictionary is skill fully used and these bit mask based word reference uses files which are fixed in length. The propounded strategy prefers to use a small number of ATE channel so that there will be a great reduction in the internal scan chains in the core when tested; By the usage of MISR or some diverged procedures the test reaction can be compressed. This particular approach does not need any different clock cycles as of previous coding methods, to determine the decompressed test design for every end bit of the scan chain from the chip to the ATE. This reference-based approach accordingly diminishes testing time as well as dispenses with the requirement for new handshaking and organization between the SOC and the ATE. This method is along these lines focused on towards a diminished test area overhead and minimized the testing time, where a contracted interface between the analyzer and the SOC is attractive editor@iaeme.com

4 Referenced BIT Reserve Scheme with BIT Masking for Test Data Compression for IP Embedded Cores 3. PROPOSED TESTING ARCHITECTURE Dictionary based strategies are very normal in the data compression area. While factual strategies utilize a measurable design of the information and according to the frequencies of an event encode the symbols using variable-size code-words, A reference set is set up by selecting the strings of the symbols in dictionary based techniques and later they are encoded into equal size tokens utilizing the reference set. Strings are stored in the reference set, and that can be static or versatile. The proposed test data compression taking into consideration the input data account augmentations and reduction of lines as new information is handled. Fig 1 describes the SOC Testing Architecture. This testing structure consists of ATE, ATPG, and Test Chip along with encoders. The ATPG gives about the test data generation with data compression and also it will generate the all testing vector designs so that it can test usage of irregular era. Figure 1 SOC Testing Architecture 3.1. Isolated Reference Set In specific cases, for example, in little code thickness design, that contains a large number of one of a kind, directions or due to algorithmic attributes, to pack the works a lot many LUT will be needed. An extensive LUT will be having a few impediments: it calls for an expensive chip territory, increased power utilization, a high LUT inertness, and an extensive code-word length. In this way, it is drawing us to decrease the word reference measure. Compacting these high-recurrence guidelines with an equal code-word length from other low-recurrence directions would bring about unskillful compression. To beat this issue and to get shorter code-word lengths these highly obtained directions are isolated into one more additional little reference set. For this Bit-mask approach two LUTs are used. A single directed code is compressed by using substantial LUT, and a remarkable degree of highrecurrence code-words are compressed using small LUTs. The small LUT can be alterable for discarding any of this individual or reference set groupings. The particular word reference established for the proposed design appears in Fig editor@iaeme.com

5 Chakrapani K, Muthaiah R 3.2. Variable Mask Numbers The maximum overhead in this was 13 bits in which 4 bits are for mask,3 bits are used to register the location of the 4-bit fixed mask,2 bits for mask, and 4 bits are used to register the location of the 2-bit fixed mask. By chance if a 4-bit fixed and a 2-bit fixed masks are used then it will yield superior outcomes for the benchmarks. In spite of the fact that the maximum overhead was 13 bits, that half of the directions were condensed to use the 4-bit altered mask in the benchmarks. In addition to this here the 4f mask and the 4f-2f masks are also added, and one of the bits is used to know if any of the code-word uses maybe a couple masks. The encoding organization appears in Table 1, which contains four states, for example, uncompressed code word coordinated with little word reference, coordinated with the expansive reference set, and organized using an inconsistent number of masks. Figure 2 Specific architecture for the proposed design Table 1 Format of encoding for our approach 4. REFERENCE BIT RESERVE (RBR) ALGORITHM According to the representation of the diagram the proposed reference bit determination is computed. The guidelines have been altered to hubs, and the edge between two hubs will give that those two directions are coordinated to one another using the Bit-Mask approach. On the whole, the hubs are distinguished into five different cases according to the recurrence and also the association design. Case a: A high recurrence hub for the most part associated with high recurrence hubs. Case b: A high recurrence hub in the main related to low recurrence hubs editor@iaeme.com

6 Referenced BIT Reserve Scheme with BIT Masking for Test Data Compression for IP Embedded Cores Case c: A low recurrence hub for the most part associated with high recurrence hubs. Case d: A low recurrence hub in the main related to low recurrence hubs. Case e: A low recurrence hub with a couple of associations. Cases a, b, and d will be the better decisions for the change in CR, and the large amount of reserve can be attained by the Case b hubs. The benefits of Case c hubs are highly restricted since the highly recurrence hubs are chosen from the reference set. In this manner, they are unacceptable for the word reference. The hubs in Case 5 are never chosen in the calculation in the fact that their low recurrence and couple of associations result in the small reserve. Algorithm 1: RBR Input: a.32-bit unique vectors of instruction b.reference set size c. Mask types Output:Optimal reference set Begin Transform ideal code-word to a graph G=(V, E){ if (hubs=bitmask) { Hub i= original size-compressed codewordsx recurrence value-32 bits Edge value i= original size-compressed codewords x recurrence of matched value } Then Reference bit reserve(si) = Calculate the total reserve bits for all hubs Select the profitable node i=i*=arg max f(si) Remove the profitable hub i Insert g to the reference set Delete the remaining edges} Update the hubs and edges} End Input: a.32-bit unique vectors of instruction b.reference set size c. Mask types Output:Optimal reference set Begin Transform ideal code-word to a graph G=(V, E) { if (hubs=bitmask) { Hub i= original size-compressed codewordsx recurrence value-32 bits Edge value i= original size-compressed codewords x recurrence of matched value } Then Reference bit reserve(si) = Calculate the total reserve bits for all hubs Select the profitable node i=i*=arg max f(si) Remove the profitable hub i Insert g to the reference set Delete the remaining edges } Update the hubs and edges } End. An RBR Algorithm is an enhanced form of the Algorithms proposed so far. The new calculation first changes each exciting direction into one hub. The two edges which are in between of the two hubs in direction will give that those two codes were correlated to one another by the usage of the Bit-Mask compression method. This suggested method then editor@iaeme.com

7 Chakrapani K, Muthaiah R discovers a bit reserving of all hubs then adds the efficient hub to the reference set. After that the high yielding hub will be expelled from Fig.3. Because of all the neighboring hubs of the highly productive hub can be secured by the most beneficial hub, the hub sparing of each adjacent hub ought to remove the edge which is connected to the highest gainful node, all the edges of then neighboring hubs are removed. These means are reused till the reference set is filled up. Figure 3 RBR The highest productive hub accomplishes savings from the mix of its hub sparing and edge reserve codes of different centres. However, associated directions can't be actually embedded into the reference set. Whether these associated codes ought to be chosen into the word reference set in the accompanying rounds is exclusively dictated by their recurrence values. This technique provides a favourable position. At the point when just the edges associated with the highly productive hub are expelled after the highly beneficial hub is chosen and then fixed firmly into the reference set. Perhaps, this algorithm is going to pick any one of the neighbours from the highly gainful hub to represent the new profitable hub. Still this may lead to the selection of number of inaccurate or Case chubs and which are bonded to the word reference. Fig.3 demonstrates a case of determination utilizing RBR. All Symbols are illustrated as 32-bit wide; the reference set contains 1024 sections; just a single 2-bit mask is utilized, and the overhead of the distinguishing tag is a 2-bit. Each hub contains its recurrence esteem when all the symbols are moved into their respective hubs. At the point when two hubs were correlated to one another by the usage of Bit-Mask, then the algorithm will make two directional edges to associate that hubs; this indicated that the weight relating to the genuine edge sparing when the associated hub is compacted by the coordinated hub. The hub saving for each hub approached nearly (code-word length 10 + a label width 2), which is duplicated by its recurrence. Edge sparing is measured up to (codeword length 10 + a label width 2 +a bitmask 6), which is duplicated by the recurrence of the coordinated hub. Hub A is clearly the highly productive hub; the bit sparing estimation of SA is superior to that of remaining hubs. In RBR, once after the Node A is chosen and embedded into the word reference, all other edges which consists of B, C, and E Nodes are erased. For B, C, and E Nodes which can be condensed by Node A utilising the Bit-Mask, the edge editor@iaeme.com

8 Referenced BIT Reserve Scheme with BIT Masking for Test Data Compression for IP Embedded Cores sparing from the edge of Node A is removed from their hub sparing. In another word, the hub sparing of Node B is initially raised to 200. After Node A is chosen and embedded into the reference set, the hub sparing of Node B is redesigned into 60 ( ) Bit masking with RBR The masking with RBR and an example of RBR with a mask are given in Algorithm 2 and in Fig.4 respectively. Algorithm 2: Bit masking with RBR Figure 4 Bit masking with RBR Input: a.32-bit unique instruction vectors b.small Reference set size c.big Reference set size d.mask types Output:Compressed code word based reference set Begin Transform ideal codeword to a graph G=(V, E){ if (hubs=bitmask) { Optimize the LUT } Then Update LUT Calculate the total reserve bits for all hubs Select the profitable node i=i* = arg max f(si) Remove the profitable hub i Insert g to the reference set Delete the remaining edges } Update the hubs and edges } End. The production of this single decoding table by RBR-based compression techniques makes a typical structure and this structure hinders the decompression engine to perform well and also with this decomposition architecture parallelized decompression cannot be performed. So, the possibilities to attain the decompression by the usage of multi-decoding tables which are accessed by changing the original compression algorithm and decompression engine are more by the application of the suggested separated dictionary structure for the dictionary-based compression strategies. For instance, we should have an algorithm to get the editor@iaeme.com

9 Chakrapani K, Muthaiah R profile of decompression level parallelism. By this study, the algorithm will make sure that, the next instruction will fall into different dictionaries and also making them to access in parallel at the same time. From this speculation the decompression of certain instruction sequences cannot be done identically. This problem can be solved in two ways: 1) The decompression level parallelism will rise by refining the compiler and 2) there should be a loss in CR to rise the decompression level parallelism which can be achieved by reproducing some instructions which should exactly be like original instructions into different dictionaries. Moreover, the parallel version of decompression engine should be redesigned. 5. OUTCOME AND DISCUSSION The modeling and implementation of the proposed LRC plan are done in VHDL and simulation is completed in Model Sim 6.5. Parameters like power, Area are analyzed in Xilinx 14.2 ISE. In this Work, tests of256 test examples are analyzed and some moves between sequential patterns. The validation of the analyzed patterns is done by, applying to the bench mark circuits of different complexity. Comes about for every strategy are arranged and contrasted and the past techniques. The obtained results proved that the reduced Dynamic power dissipation is by RBT scheme. Figure 5 Simulation Output of E-RBT Fig.5. demonstrates that yield of the RBT code for clk=1 and control flag set =1, the yield J are introduced to zero while for control signs are zero, the yield affirms that 8-bit mode work. The compression improvement percentage is figured utilizing ( ) Where Cr=compression ratio, CRothers= average Cr of other methods, CRours= average Cr of RBT method. To process the average and peak power control which is same as utilized by previous methods. The decrease in average power utilization is figured using the accompanying Equations individually. (1) ( ) (2) editor@iaeme.com

10 Referenced BIT Reserve Scheme with BIT Masking for Test Data Compression for IP Embedded Cores where average power utilizations of the test vector got from Mintest program, the expression "X" in represents average power of separate techniques. Table 2 and 3 shows comparison of compression ratio and scan-in average power respectively. Table 2 Comparisons of Compression ratio(%) Benchmark circuits Proposed RBR ARL EFDR FDR MIN TEST S S S S S S Table 3 Scan-in average power: Comparison of RBR with others Benchmark circuits RBR ARL EFDR FDR MIN TEST S S S S S Average The test application time (TAT) for compressed test depends on the compression ratio, system clock frequency and decompression architecture. The test time is the same as the transfer time when there is no compression. If the total bits in uncompressed test are TD and ATE transfers data to SoC at the rate of fate, then the TAT of uncompressed test set (TATno comp) is given in equation (3) (3) Table 4 Test application time: RBR vs others (in ATE clock cycles in sec) Benchmar k circuits Proposed RBR ARL EFDR FDR MIN TEST S S S S S S editor@iaeme.com

11 Chakrapani K, Muthaiah R Table 5 Fault coverage comparison (%) of Benchmark Circuit PROPOSED RBR ARL EFDR FDR S S S S S S Table 4 and 5 gives Test application time between RBR with others and certain benchmarks respectively. It also gives how many test patterns are required to hit target fault coverage for existing Methods and proposed RBT algorithm. Hence the performance of fault coverage comparison for ISCAS 89 benchmark circuits is improved using RBR. 6. CONCLUSIONS Thus the possibilities to attain the decompression by the usage of multi-decoding tables which are accessed by changing the original compression algorithm and decompression engine are more by applying the proposed RBR architecture for the based compression methods. By this study, the algorithm will make sure that, the next instruction will fall into different dictionaries and also making them to access in parallel at the same time. From this speculation the decompression of certain instruction sequences cannot be done identically. This problem can be solved in two ways: 1)The decompression level parallelism will rise by refining the compiler and 2) there should be a loss in CR to rise the decompression level parallelism which can be achieved by reproducing some instructions which should exactly be like original instructions into different dictionaries. Moreover, the parallel version of decompression engine should be redesigned. REFERENCES [1] Touba, N. A. (2006). Survey of test vector compression techniques. IEEE Design & Test of Computers, 23(4), [2] Jas, A., & Touba, N. A. (1998, October). Test vector decompression via cyclical scan chains and its application to testing core-based designs. In Test Conference, Proceedings., International (pp ). IEEE. [3] Chandra, A., & Chakrabarty, K. (2001). System-on-a-chip test-data compression and decompression architectures based on Golomb codes. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 20(3), [4] Chandra, A., & Chakrabarty, K. (2003). Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Transactions on Computers, 52(8), [5] Gonciari, P. T., Al-Hashimi, B. M., & Nicolici, N. (2003). Variable-length input Huffman coding for system-on-a-chip test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(6), [6] El-Maleh, A. H. (2008). Test data compression for system-on-a-chip using extended frequency-directed run-length code. IET Computers & Digital Techniques, 2(3), [7] Chandra, A., & Chakrabarty, K. (2003). A unified approach to reduce SOC test data volume, scan power and testing time. IEEE transactions on computer-aided design of integrated circuits and systems, 22(3), editor@iaeme.com

12 Referenced BIT Reserve Scheme with BIT Masking for Test Data Compression for IP Embedded Cores [8] Nourani, M., & Tehranipour, M. H. (2005). RL-Huffman encoding for test compression and power reduction in scan applications. ACM Transactions on Design Automation of Electronic Systems (TODAES), 10(1), [9] Yu, Y., Yang, Z., & Peng, X. (2012, May). Test data compression based on variable prefix dual-run-length code. In Instrumentation and Measurement Technology Conference (I2MTC), 2012 IEEE International (pp ). IEEE. [10] Lee, L. J., Tseng, W. D., Lin, R. B., & Chang, C. H. (2012). $2^{n} $ Pattern Run-Length for Test Data Compression. IEEE transactions on computer-aided design of integrated circuits and systems, 31(4), [11] Sismanoglou, P., & Nikolos, D. (2011, December). Test data compression based on the reuse of parts of the dictionary entries. In Electronics, Circuits and Systems (ICECS), th IEEE International Conference on (pp ). IEEE. [12] Kavousianos, X., Kalligeros, E., & Nikolos, D. (2007). Optimal selective Huffman coding for test-data compression. IEEE transactions on computers, 56(8). [13] F. R. Ohnsorg, Binary Fourier Representation, In Spectrum Analysis Techniques Symposium, Sept [14] Yogi, N., & Agrawal, V. D. (2010, April). Application of signal and noise theory to digital VLSI testing. In VTS (pp ). [15] Yogi, N., & Agrawal, V. D. (2009, August). BIST/Test-Decompressor Design using Combinational Test Spectrum. In Proc. 13th VLSI Design and Test Symp. [16] Chin, C. K., & McCluskey, E. J. (1984). Weighted pattern generation for built-in self-test. Center for Reliable Computing, Computer Systems Laboratory, Depts. of Electrical Engineering and Computer Science, Stanford University. [17] Lee, D., & Roy, K. (2012). Viterbi-based efficient test data compression. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(4), [18] JNVR Swarup Kumar and R Deepika. An Optimized Block Estimation Based Image Compression and Decompression Algorithm. International Journal of Computer Engineering and Technology, 7 (1), 2016, pp [19] Ashwini Atulkar and Abhishek Jain. A Video Compression Technique Utilizing Spatio - Temporal Lower Coefficients. International Journal of Electronics and Communication Engineering & Technology, 7 (1), 2016, pp editor@iaeme.com