Tips for Making Video IP Daniel E. Michek. Copyright 2015 Xilinx.
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1 Tips for Making Video IP Daniel E Michek
2 Challenges for creating video IP Design Test Many interfaces, protocols, image sizes Asynchronous clock domains for multiple inputs Hard to visualize video when developing IP Large amounts of data make multi-frame verification difficult in simulation Implement Design reuse for different protocols Control logic and interrupts Real-time testing churn
3 Magnifier Loop Application Crop a region of interest, magnify, and merge
4 Magnifier Loop Application
5 Tip: Separate video inputs & outputs from the video processing domain Video IP Control Clock Domain (AXI Lite) MicroBlaze / Zynq GP ~100 MHz Input Domain HDMI / SDI ~150 MHz Input Domain HDMI / SDI Input Domain HDMI / SDI Video Processing Domain Scaler / Deinterlacer / Chroma / Color Space Conversions / On Screen Display / Cropping / Video DMA / Noise Reduction / Color Filter Array / Gamma / Defective Pixel Correction / Enhancement / Statistics / Anything AXI Streaming for video ~150+ to 200 MHz, faster than In/Out Synchronous to memory when applicable Output Domain HDMI / SDI ~150 MHz Output Domain HDMI / SDI Output Domain HDMI / SDI
6 Clocking domains - multi input / single processing / output
7 AXI4-Stream video signaling interface Function Width Direction AXI4-Stream Signal Name Video Data 8*n IN s_axis_video_tdata m_axis_video_tdata Valid 1 IN s_axis_video_tvalid m_axis_video_tvalid Ready 1 OUT s_axis_video_tready m_axis_video_tready Start of Frame 1 IN s_axis_video_tuser m_axis_video_tuser End of Line 1 IN s_axis_video_tlast m_axis_video_tlast Video Specific Name Data Valid Ready SOF EOL
8 The AXI Interface AXI4-Stream No addresses channel, no read and write response, always just master to slave Effectively an AXI4 write data channel AXI4-Stream Transfer Unlimited burst length AXI4 max 256 AXI4-Lite does not burst Virtually same signaling as AXI4 Data Channels Protocol allows merging, packing, width conversion Supports sparse, continuous, aligned, unaligned streams MASTER SLAVE
9 Tip: Enabling Platform Framework Based Design Value-get Generating the platform framework Processing Systems Board Level Interfaces Fully Configurable Platform Designs All of your board level interfaces with connectivity IP & presets Application based platforms Value-add Your design is the differentiator for the All Programmable SoC HLS / RTL System Generator SDSoC & SDAccel applications Zynq+ / MathWorks Coder Workflows Value-add Data Path & Logic
10 Tip: Automated Platform Design Connectivity and Insertion Find unconnected interfaces from the IP Integrator design Import via Matlab command line to create matching gateways User fills in logic between interfaces Automatic insertion connects the System Generator and IP Integrator systems
11 Working with AXI4-Stream in System Generator Tip: Stop shaking hands Video data has TReady / TValid handshake Utilize FIFO at end of processing chain to make data path pressure-free Almost full de-asserts handshakes to upstream IP
12 Building an image cropper Tip: Manipulate side band signals, not the data Pass all of the data (delayed) Modify the side band signals for Valid, End of Line, Start of Frame
13 Scaling the cropped window Tip: Watch how you parse 2D to minimize BRAM Upscaling Vertical Filter then Horizontal Filter Interpolate a new line Interpolate new pixels for the current and new line Interleave new pixels Dump new line
14 Delaying the original image Tip: FIFOs make easy line buffers Delaying by pixels Delay read enable until a certain number of TValids occur Delaying by lines Delay read enable until a certain number of TLasts occur
15 Alpha mask and blending Tip: When it s time, only process the data Mask Data determines how to shape the magnifier loop Alpha blending in DSP48E1: (F-B)*a+B == F*a + B*(1-a)
16 Processor based control Tip: Leverage the gateways to get on the bus Gateways automatically convert to AXI4-Lite interfaces Simplified modeling of software for initial and update conditions Multiple clock domains allow fast data vs slow control path
17 Full system with visual & waveform testing Tip: Use qualitative and quantitative verification
18 Enabling the stack approach: control & move data Tip: Use automation to build the platform Layer Example Automation Application User code Examples / Linux Presentation Drivers HW Handoff Session IP Addresses Connection Transport AXI MM Connection (data) Network AXI Interconnect Connection (control) MAC Memory controller Block PHY DDR I/F Board
19 IP Integrator Block Diagram Tip: Automatically package and re-insert IP
20 Summary Design, Test, Implement AXI simplifies working with video Can easily oversample, simplified markers for End Of Line and Start Of Frame AXI4-Lite interfaces and registers are automatic Matrix viewers, MCode make it easy to work and simulate video Work with any image type using imread Can also use Hardware Co-Simulation for improved simulation performance Automatic export as IP Detects any AXI interfaces Delivers drivers for AXI4-Lite
21 Thank You More Information is Available in DocNav Follow Xilinx on:
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