Hardware Design. University of Pannonia Dept. Of Electrical Engineering and Information Systems. MicroBlaze v.8.10 / v.8.20

Transcription

1 University of Pannonia Dept. Of Electrical Engineering and Information Systems Hardware Design MicroBlaze v.8.10 / v.8.20 Instructor: Zsolt Vörösházi, PhD. This material exempt per Department of Commerce license exception TSU

2 Objectives After completing this module, you will be able to: List the MicroBlaze 8.10 / 8.20 Features List the functionality that defines an arbiter, a master, and a slave List the various buses available in the MicroBlaze processor List the various high performance links in the MicroBlaze processor 13-2 Hardware Design

3 Outline MicroBlaze Features Buses 101: Arbiter, Master, Slave MicroBlaze System Interfaces Processor Local Bus (PLB) Advanced Extensible Interface (AXI) (AMBA 3rd/4th gen.) Local Memory Bus (LMB) Fast Simplex Link (FSL) Xilinx Cache Link (XCL) Summary 13-3 Hardware Design

4 MicroBlaze Literature MicroBlaze soft-processor FAQ: urces/proc_central/microblaze_faq.pdf MicroBlaze soft-processor core MicroBlaze reference guide*: uals/xilinx13_1/mb_ref_guide.pdf (*or this file can be found in the EDK install dir)

5 MicroBlaze Block Diagram Optional MMU for Linux2.6 and MPU block for ease of software use PLB based system 13-5 Hardware Design Enhanced FSL for CPU to hw/sw accelerator

6 MicroBlaze Processor Scalable 32-bit soft processor Core Harvard architecture RISC instruction set (app. 85 instruction + sub classes) Big Endian (BE) bit/byte reversed format (optionally Little Endian LE) Single-Issue pipeline Supports either 3-stage (resource focused) or 5-stage pipeline (performance focused) Configurable Instruction and Data Caches Direct mapped (1-way associative) Optional Memory Mgt or Memory Protection Unit Required for Linux OS (Linux 2.6 is currently supported) Floating-point unit (FPU) Based upon IEEE 754 format Barrel Shifter Hardware multiplier 32x32 multiplication to generate a 64-bit result Hardware Divider (FSL) Fast Simplex Link FIFO Channels for Easy, Direct Access to Fabric and Hardware Acceleration Hardware Debug and Trace Module 13-6 Hardware Design

7 New MicroBlaze Processor v8 Features New features and improvements NEW*: High-performance AXI4 interface and AMBA - AXI4 peripherals Memory Management Unit (MMU) implements virtual memory management PPC405 processor MMU compatible Virtual memory management provides greater control over memory protection, which is especially useful with applications that can use an RTOS Processing improvements New float-integer conversion and float-square root instructions Speeds up FP Int conversion Int FP conversion FP square root Enhanced XMD (Debug) support AXI4 streaming interface (uni-directional) 13-7 Hardware Design

8 New MicroBlaze Processor v8 Features AXI Streaming Interface AXI4 streaming interface to/from MicroBlaze/ARM processor Uni-directional, point-to-point FIFO-based communication Built-in programmable depth FIFO 2 Simplex connection processor to/from FIFO AXI streaming interface on fabric side Direct connection to CPU core Native to MicroBlaze processor hardware Enable up to 16 in/out pairs (channels) Dedicated register to/from FIFO assembler instructions 13-8 Hardware Design

9 MicroBlaze Processor Performance All instructions (total 85) take one clock cycle, except the following Load and store (two clock cycles).e.g. memory reaching instructions Multiply (two clock cycles) Branches (three clock cycles, can be one clock cycle) For further details, see: microblaze.pdf (in the XPS/EDK install package) Operating frequency fast speed grade, 5 stage pipeline 307 MHz on the Virtex-6 (-3) FPGA 245 MHz on the Virtex-5 (-3) FPGA 154 MHz on the Spartan -6 (-3) FPGA 119 MHz on the Spartan-3 (-5) FPGA Performance of 1.15 DMIPS/MHz (=Dhrystone MIPS means Fmax ultimate clock speed ) Fabric utilization in LUT s size optimized/speed optimized 779/1,134 LUTs in the Virtex-6 FPGA 240/330 LUTs in the Virtex-5 FPGA 770/1,154 LUTs in the Spartan-6 FPGA 1,258/1,821 LUTs in the Spartan-3 FPGA 13-9 Hardware Design

10 Outline MicroBlaze features Buses 101: Arbiter, Master, Slave MicroBlaze System Interfaces Processor Local Bus (PLB) Advanced Extensible Interface (AXI) Local Memory Bus (LMB) Fast Simplex Link (FSL) Xilinx Cache Link (XCL) Summary Hardware Design

11 Buses 101 A bus is a multi-wire path on which related information is delivered Address, data, and control buses Processor and peripherals communicate through buses Peripherals may be classified as: Arbiter (A), master (M), or slave (S), or both master/slave (e.g. bridge - B) Arbiter Master Arbiter Master Master/ Slave (Bridge) Slave Slave Slave Hardware Design

12 Buses 101 Bus masters (M) have the ability to initiate a bus transaction Bus slaves (S) can only respond to a request Bus arbitration (A) is a three-step process: A device (M) requesting to become a bus master asserts a bus request (BR) signal The arbiter continuously monitors = poll the request and outputs an individual grant signal (BG) to each master according to the master s priority scheme and the state of the other master requests at that time The requesting device samples its grant signal until the master is granted access. The master then initiates a data transfer between the master and a slave when the current bus master releases the bus Arbitration mechanisms: make decision, who will the next master for a data transaction Fixed priority, round-robin, hybrid Hardware Design

13 CoreConnect Bus Architecture The IBM CoreConnect bus architecture standard provides three buses for interconnecting cores, library macros, and custom logic: Processor Local Bus (PLB) On-Chip Peripheral Bus (OPB) * Device Control Register (DCR) ** bus IBM offers a no-fee, royalty-free CoreConnect bus architecture license Licenses receive the PLB arbiter, OPB arbiter, and PLB/OPB bridge designs along with bus-model toolkits and bus-functional compilers for the PLB, OPB, and DCR buses Required only if you create your own CoreConnect bus architecture peripheral or you are using the Bus Functional Model (BFM) * OPB bus is deprecated, hence won t be discussed (from EDK v.11.x) ** DCR bus is PowerPC specific, hence won t be discussed Hardware Design

14 Busses 101 The MicroBlaze processor core is organized as a Harvard architecture Multi-Port (MPMC) / External (EMC) Memory Controller IIC CacheLinks Local Memory LMB Buses DLMB ILMB DXCL MicroBlaze FSL IXCL Co-Processor DPLB IPLB Separate busses for data and instruction UART GPIO Ethernet BRAM Interrupt Controller Timer/PWM PLB ARB Hardware Design

15 Outline MicroBlaze Introduction Buses 101: Arbiter, Master, Slave MicroBlaze System Interfaces Processor Local Bus (PLB) Advanced Extensible Interface (AXI) (AMBA 3rd/4th gen.) Local Memory Bus (LMB) Fast Simplex Links (FSL) Xilinx Cache Link (XCL) Summary Hardware Design

16 MicroBlaze System (SOC: System-On-a-Chip) BRAM Local Memory Bus Fast Simplex Link 0,1.15 MicroBlaze 32-Bit RISC Core Arbiter I-Cache BRAM Configurable Sizes D-Cache BRAM PLB Processor Local Bus Another segment of PLB necessary when slow devices to be operated at slower bus speed enabling higher-performance system Arbiter required only when a peripheral is master capable and wants to write to peripheral on the other segment Bus Bridge PLB Processor Local Bus Arbiter Custom Functions Custom Functions CacheLink 10/100/1000 EtherNet Memory Controller UART GPIO On-Chip Peripheral SDRAM SDR/DDR/DDR2/DDR3 Off-Chip Memories FLASH/SRAM Hardware Design

17 Outline MicroBlaze Introduction Buses 101: Arbiter, Master, Slave MicroBlaze System Interfaces Processor Local Bus (PLB) Advanced Extensible Interface (AXI) Local Memory Bus (LMB) Fast Simplex Links (FSL) Xilinx Cache Link (XCL) Summary Hardware Design

18 MicroBlaze System Processor Local Bus (v4.6 PLB) BRAM Local Memory Bus Fast Simplex Link 0,1.15 MicroBlaze 32-Bit RISC Core Arbiter I-Cache BRAM Configurable Sizes D-Cache BRAM PLB Processor Local Bus Another segment of PLB necessary when slow devices to be operated at slower bus speed enabling higher-performance system Arbiter required only when a peripheral is master capable and wants to write to peripheral on the other segment Bus Bridge PLB Processor Local Bus Arbiter Custom Functions Custom Functions CacheLink 10/100 E-Net Memory Controller UART GPIO On-Chip Peripheral SDRAM Off-Chip Memory FLASH/SRAM Hardware Design

19 PLB Bus Connection infrastructure for high-bandwidth master and slave devices Fully synchronous to one clock Centralized bus arbitration PLB arbiter 32 or 64-bit address (upper 32-bit are connected to GND by default) 32, 64, or 128-bit data bus Selectable shared bus or point-to-point interconnect topology Point-to-point optimization available for 1 master, 1 slave configuration Point-to-point topology supports 0 cycle latency via arbitration removal Selectable address pipelining support (2-level only) Dynamic master request priority based arbitration Vectored resets and address/qualifier registers Hardware Design

20 PLB Interconnect / Architecture One Arbiter to 16 PLB Masters, each connect all of their signals to the PLB arbiter The PLB Arbiter multiplexes signals from Masters onto a shared bus to which all the inputs of the Slaves are connected One Arbiter to n PLB Slaves OR together their outputs to drive a shared bus back to the PLB Arbiter The PLB Arbiter handles bus arbitration and the movement of data and control signals between Masters and Slaves Hardware Design

21 PLB Bridge The PLB-to-PLB bridge is required when two PLB segments are connected Different bus speed (clock domains) Different bus width (conversion) The bridge translates PLB transactions on one side into the PLB transactions of the other side The bridge functions as a Slave on one PLB side and a Master on the other PLB side For a typical system with two PLB segments, one bridge is necessary for transactions originating from MB processor A second bridge is required if a peripheral on the other side is master capable and wants to address a peripheral on the processor side Hardware Design

22 Outline MicroBlaze Introduction Buses 101: Arbiter, Master, Slave MicroBlaze System interfaces Processor Local Bus (PLB) Advanced Extensible Interface (AXI) Local Memory Bus (LMB) Fast Simplex Links (FSL) Xilinx Cache Links (XCL) Summary Hardware Design

23 AXI is Part of AMBA: Advanced Microcontroller Bus Architecture Enhancements for FPGAs AMBA 3.0 (2003) Same Spec AMBA 4.0 (Just Announced) Interface Features Similar to Memory Map / Full Traditional Address/Data Burst (single address, multiple data) PLBv46, PCI Streaming Data-Only, Burst Local Link / DSP Interfaces / FIFO / FSL Lite Traditional Address/Data No Burst (single address, single data) Hardware Design PLBv46-single OPB

24 The ARM AXI Is... An interface and protocol definition Widely used industry standard Is not... A bus The AXI specification describes an interface on a piece of IP. It does not specify how systems of IP will be connected Hardware Design

25 PLB is a Bus Spec AXI is an Interface Spec Processor PLB PLB46 Shared Access Bus AXI Masters Interconnect AXI Slaves Peripherals PLB PLB PLB AXI AXI Interconnect IP IP Implementation is is not not described in in the the spec spec Several companies build build and and sell sell AXI AXI interconnect IP IP Xilinx is is building its its own own AXI AXI AXI AXI AXI AXI AXI AXI AXI AXI Arbiter AXI is an interface specification, not a bus specification Hardware Design Arrows indicate master/slave relationship, not direction of dataflow Master Slave

26 Basic AXI Transactions Read address channel Read data channel Write address channel Write data channel Write response channel Non-posted write model: there will always be a write response Hardware Design

27 AXI Interface: AXI4 Also called full AXI, AXI Memory Mapped (MM) Single address multiple data AXI4 Read Burst up to 256 data beats Targeted Xilinx support AXI4 Write Hardware Design

28 AXI Interface: Lite No burst Data width 32 or 64 only Xilinx IP will only support 32 bits Simple logic shim to connect AXI4 master to AXI4-Lite slave Reflect master s transaction ID AXI4-Lite Read AXI4-Lite Write Hardware Design

29 AXI Interface: Streaming No address channel Not read and write, always just master to slave Unlimited burst length AXI4-Streaming Transfer Hardware Design

30 Outline MicroBlaze Introduction Buses 101: Arbiter, Master, Slave MicroBlaze System interfaces Processor Local Bus (PLB) Advanced Extensible Interface (AXI) Local Memory Bus (LMB) Fast Simplex Links (FSL) Xilinx Cache Links (XCL) Summary Hardware Design

31 MicroBlaze System Local Memory Bus BRAM Local Memory Bus Fast Simplex Link 0,1.15 MicroBlaze 32-Bit RISC Core Arbiter I-Cache BRAM Configurable Sizes D-Cache BRAM PLB Processor Local Bus Another segment of PLB necessary when slow devices to be operated at slower bus speed enabling higher-performance system Arbiter required only when a peripheral is master capable and wants to write to peripheral on the other segment Bus Bridge PLB Processor Local Bus Arbiter Custom Functions Custom Functions CacheLink 10/100 E-Net Memory Controller UART GPIO On-Chip Peripheral SDRAM Off-Chip Memory FLASH/SRAM Hardware Design

32 Local Memory Bus (LMB) The Local Memory Bus (LMB) provides single-cycle access to onchip dual-port block RAM for MicroBlaze processors The LMB provides simple synchronous protocol for efficient block RAM transfers DLMB: Data interface, local memory bus (block RAM only) ILMB: Instruction interface, local memory bus (block RAM only) Hardware Design

33 Outline MicroBlaze Introduction Buses 101: Arbiter, Master, Slave MicroBlaze System Interfaces Processor Local Bus (PLB) Advanced Extensible Interface (AXI) Local Memory Bus (LMB) Fast Simplex Link (FSL) Xilinx Cache Link (XCL) Summary Hardware Design

34 MicroBlaze System Fast Simplex Links (FSL) BRAM Local Memory Bus Fast Simplex Link 0,1.15 MicroBlaze 32-Bit RISC Core Arbiter I-Cache BRAM Configurable Sizes D-Cache BRAM PLB Processor Local Bus Another segment of PLB necessary when slow devices to be operated at slower bus speed enabling higher-performance system Arbiter required only when a peripheral is master capable and wants to write to peripheral on the other segment Bus Bridge PLB Processor Local Bus Arbiter Custom Functions Custom Functions CacheLink 10/100 E-Net Memory Controller UART GPIO On-Chip Peripheral SDRAM Off-Chip Memory FLASH/SRAM Hardware Design

35 The Software Streaming Data Challenge (FSL) Suppose you want to move data through a hardware/software processing application with following characteristics Data may be of a streaming or burst (löketszerű) nature Deterministic latency between hardware and software (ns, clk etc.) Possible solutions include Disadvantages: Bus peripheral, maybe PLB Multiple clock-cycle overhead Address decode time Arbitration, loss of hardware/software coherency Custom microprocessor instruction access to peripheral hardware May require processor to be stalled (passive state) Complex logic can slow overall processor speed May require assembly language to access special instruction Fast Simplex Links! Hardware Design

36 Another Alternative: Fast Simplex Links ( FSL) Uni-directional point-to-point FIFO-based communication Dedicated (unshared) and non-arbitrated architecture Dedicated MicroBlaze C and ASM instructions for easy access High speed, access in as little as two clocks on processor side, 600 MHz at hardware interface Available in Xilinx Platform Studio (XPS) as a bus interface library core from Hardware Create or Import Peripheral Wizard FSL_M_Clk FSL_S_Clk FSL_M_Data [0:31] FSL_M_Control FSL_M_Write FSL_M_Full FIFO 32-bit data FSL_S_Data [0:31] FSL_S_Control FSL_S_Read FSL_S_Exists FIFO Depth Hardware Design

37 FSL Features 32-bit wide interface Configurable FIFO depths 1 to 8192 using SRL16 (shift regs) logic or dedicated block RAM Synchronous or asynchronous FIFO clocking with respect to the MicroBlaze system clock Selectable use of control bit Simple software interface using predefined C instructions; Automatically generated C drivers Blocking and non-blocking software instructions for data and control (get and put) Blocking FSL instruction made interruptable Return from interrupt will resume the FSL instruction Exception (event) from FSL can be generated Disable interrupt while FSL executing Addition of dynamic assignment of FSL channel (getd and putd) Channel number from register rather than immediate Hardware Design

38 Outline MicroBlaze Introduction Buses 101: Arbiter, Master, Slave MicroBlaze System Interfaces Processor Local Bus (PLB) Advanced Extensible Interface (AXI) Local Memory Bus (LMB) Fast Simplex Link (FSL) Xilinx Cache Link (XCL) Summary Hardware Design

39 MicroBlaze System Xilinx Cache Links BRAM Local Memory Bus Fast Simplex Link 0,1.15 MicroBlaze 32-Bit RISC Core Arbiter I-Cache BRAM Configurable Sizes D-Cache BRAM PLB Processor Local Bus Another segment of PLB necessary when slow devices to be operated at slower bus speed enabling higher-performance system Arbiter required only when a peripheral is master capable and wants to write to peripheral on the other segment Bus Bridge PLB Processor Local Bus Arbiter Custom Functions Custom Functions CacheLink 10/100 E-Net Memory Controller UART GPIO On-Chip Peripheral SDRAM Off-Chip Memory FLASH/SRAM Hardware Design

40 Xilinx Cache Link (XCL) High-performance solution for memory accesses The MicroBlaze CacheLink interface is designed to connect directly to a memory controller with integrated FSL Buffers i.e. MicroBlaze can connect directly to data ports of EDK supported multi-port (MPMC) or external (EMC) memory controllers The CacheLink Interface is only available on MicroBlaze when caches are enabled The CacheLink cache controllers handle 4 or 8-word cache lines (32bit/word) All individual CacheLink accesses follow the FSL FIFO based transaction protocol Hardware Design

41 Outline MicroBlaze Introduction Buses 101: Arbiter, Master, Slave MicroBlaze System Interfaces Processor Local Bus (PLB) Advanced Extensible Interface (AXI) Local Memory Bus (LMB) Fast Simplex Link (FSL) Xilinx Cache Link (XCL) Summary Hardware Design

42 Summary Current version of MicroBlaze (8.10 / 8.20) supports both AXI and PLB interfaces Either PLB bus or AXI interface can be present on the processor PLB is a shared bus connection infrastructure for high-bandwidth master and slave devices AXI is an interface providing high performance through point-topoint connection FSL is used for data transfer where deterministic latency is required LMB provides local memory where data, stack, interrupt service routines can reside. It provides fixed and deterministic latency XCL is available only when cache is enabled Hardware Design