Manchester encoder on Linear feedback shift register Pseudo arbitrary sequence engenderer Recollection controller

Transcription

1 Manchester encoder on Linear feedback shift register Pseudo arbitrary sequence engenderer Recollection controller S Ashok Reddy 1 & S Mahaboob Basha 2 1 M-Tech Dept of ECE, Geethanjali Engineering College NANNUR-V, KURNOOL-DIST 2 Assistant Professor Dept ECE, Geethanjali Engineering College NANNUR-V, KURNOOL Abstract: DIST Mail Id:- syedmahaboob45@gmail.com In this paper a plenarily reused VLSI architecture of FM0/Manchester encoding technique for recollection application has been proposed. In this paper we are encoding the 1 bit data into 16 bit data and storing it into a recollection of certain address location given by the linear feedback shift register (LFSR),whose input is taken from the pseudo desultory sequence engenderer (PRSG). The encoded 16 bit data is stored into recollection controller; the encoded data is decoded back into 1 bit data under the condition: when MSB bit is at logic state 1. By utilizing FM0/Manchester encoding and decoding technique, the data will be secure, this process is facile and more expeditious to carry out. This paper develops a plenarily reused VLSI architecture, and additionally exhibits an efficient performance. Keywords: FM0/ Manchester encoder, Linear feedback shift register (LFSR), Pseudo arbitrary sequence engenderer (PRSG), Recollection controller. 1. INTRODUCTION The dedicated short range communication is a protocol for one or two way medium range communication. The DSRC can be briefly relegated into two categories: automobile-toautomobile and automobile-to roadside. In automobile-to-automobile, the DSRC enables the message sending and broadcasting among automobile. The automobile-to-roadside fixates on the astute conveyance accommodation, such as electronic toll accumulation (ETC).The DSRC architecture having the transceiver. The transceiver having the baseband processing, RF front end and microprocessor. The microprocessor is utilized to transfer the injuctive authorization to the baseband processing and RF front end. the RF front end is utilized to transmit and receive the wireless signals Available online: P a g e 1584

2 utilizing the antenna. The baseband rudimentary modules: Microprocessor, processing is responsible for modulation, Baseband Processing and RF Front - End. error rectification, encoding and The Microprocessor interprets ordinant synchronization. The transmitted signal dictations from media access control to consists of the arbitrary binary sequence, it schedule the tasks of baseband processing is very arduous to obtain the dc-balance.the and RF front - end. The Baseband fm0 and Manchester are provide the transmitted signal and then the dc-balance. The (SOLS) kindred attribute oriented logic simplification having the two methods: area Processing is responsible for modulation, error rectification, clock synchronization and encoding. The RF front-end transmits and receives the wireless signal through the compact retiming and balance logic antenna. operation sharing. The area compact 2. RELEATED WORK retiming used to reduce the transistor counts.the balance logic operation sharing is utilized to coalesce the fm0 and Manchester encoding. However, the coding diversity between both solemnly limits the potential to design a VLSI architecture that can be plenarily reused with each other. This paper proposes a VLSI architecture design utilizing Homogeneous attribute Oriented Logic Simplification (SOLS) technique. The SOLS consists of two core methods: Area - Compact Retiming and Balance Logic - Operation Sharing. The Area - Compact Retiming relocates the hardware resource to Fig. 1. System architecture of DSRC reduce the transistors count. The Balance transceiver Logic - Operation Sharing efficiently The Standard system architecture of DSRC coalesces FM0 and Manchester encodings Transceiver is shown in Fig. 1. The upper with the plenarily reused hardware and bottom components are dedicated for transmission and receiving, respectively. architecture. With SOLS technique, this paper constructs a plenarily reused VLSI This Transceiver is relegated into three Available online: P a g e 1585

3 architecture of Manchester and FM0 encodings for DSRC applications. The experiment results reveal that this design achieves an efficient performance compared with sophisticated works. The literature [1] proposes the plenarily reused VLSI architecture of FM0/Manchester encoding utilizing kindred attribute oriented logic simplification (SOLS) technique for Dedicated short range communication. The SOLS technique ameliorates the hardware utilization rate from 57.14% to 100% for both FM0 and Manchester encodings. 2.The literature [2] proposes a VLSI architecture of Manchester encoder for optical communications. This design utilizes the CMOS inverter and the gated inverter as the switch to construct Manchester encoder. It is executed by 0.35-μm CMOS technology and its operation frequency is 1 GHz. 3.The literature [3] later supersedes the architecture of switch in [2] by the nmos contrivance. It is performed in 90-nm CMOS technology, and the maximum operation frequency is as high as 5 GHz. 4.The literature [4] evolves a high-speed VLSI architecture relatively plenarily reused with Manchester and Miller encodings for radio frequency identification (RFID) applications. This architecture is performed in 0.35-μm CMOS technology and the maximum operation frequency is 200 MHz. 3. IMPLEMENTATION Fm0 encoding The FM0 having the following three rules. 1) If X is the logic-0,the fm0 code has the transition between the A and B. 2) If X is the logic-1,there is no transition is sanctioned between the A and B. 3) The transition is allocated in each FM0 code. The wave form is given below the following diagram.the fm0 having the clock and then the x.the clock and then the cycle having the cycle in each transaction. Fig:-2 FM0 encoding Manchester encoding The Manchester encoding is realized with the XOR operation for using the CLOCK and X. The clock always has a transition within the one cycle. Available online: P a g e 1586

4 Fig:-3 Manchester encoding The State Code Principle For Fm0/Manchester The Manchester encoding is an XOR operation only. The FM0 code starts with the FSM principle. The FSM of FM0 code classified into four states. The four states as shown in the below figure. Fig:-4 FSM of FM0 Fig:-5 State diagram Suppose the initial state is S1, and its state code is 11 for A and B, respectively. 1) If the X is logic-0, the state-transition must follow both rules for FM01 and 3. The only one next-state that can gratify both rules for the X of logic-0 is S3. If the X is logic-1, the state-transition must follow both rules for FM0 2 and 3. The only one next-state that can slake both rules for the X of logic-1 is S4. Thus, the state-transition of each state can be plenarily constructed. The FSM of FM0 can withal conduct the transition table of each state A(t) and B(t) represent the discrete-time state code of current-state at time instant t. Their anterior-states are denoted as the A(t 1)and the B(t 1), respectively. With this transition table, the Boolean functions of A(t) and B(t) are given as A(t) = B(t 1) B(t) = X B(t 1) With both A(t) and B(t), the Boolean function of Available online: P a g e 1587

5 FM0 code is denoted as CLK A(t) +~ CLK B(t) 4. EXPERMENTAL RESULTS Fig:-6 Process Fig:-7 Ciructe Fig:-8 Simulation Results 5. CONCLUSION The coding diversity between FM0 and Manchester encodings causes the circumscription on hardware utilization of VLSI architecture design. The plenarily reused VLSI architecture utilizing SOLS technique for both FM0 and Manchester encodings are proposed. The SOLS technique eliminates the inhibition on hardware utilization by two core techniques: Area Compact Retiming and Balance Logic Operation Sharing. The ACR technique relocates the hardware resource to reduce the transistor count. The BLOS efficiently amalgamates the FM0 and Manchester encodings with the identical logic components. The SOLS technique amends the Hardware Utilization Rate (HUR) from 57.14% to 100% for both FM0 and Manchester encodings. The balanced hardware architecture is realized in different CMOS technology. For further reduction in transistor count of the proposed design, the transmission gate logic is considered in the circuit design of MUX_1, MUX_2 and XNOR. This paper not solitary develops a plenarily reused VLSI architecture, but additionally exhibits an efficient Available online: P a g e 1588

6 performance compared with the subsisting works. 6. REFERENCES [1] Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications Yu- Hsuan Lee, Member, IEEE, and Cheng-Wei Pan [2] P. Benabes, A. Gauthier, and J. Oksman, A Manchester code generator running at 1 GHz, in Proc. IEEE, Int. Conf. Electron., Circuits Syst., vol. 3. Dec. 2003, pp [3] A. Karagounis, A. Polyzos, B. Kotsos, and N. Assimakis, A 90nm Manchester code generator with CMOS switches running at 2.4 GHz and 5 GHz, in Proc. 16th Int. Conf. Syst., Signals Image Process., Jun. 2009, pp [4] Y.-C. Hung, M.-M. Kuo, C.-K. Tung, and S.-H. Shieh, High-speed CMOS chip design for Manchester and Miller encoder, in Proc. Intell. Inf. Hiding Multimedia Signal Process., Sep. 2009, pp [5] M. A. Khan, M. Sharma, and P. R. Brahmanandha, FSM based FM0 and Miller encoder for UHF RFID tag emulator, in Proc. IEEE Adv. Comput. Conf., Mar. 2009, pp [6] J.-H. Deng, F.-C. Hsiao, and Y.-H. Lin, Top down design of joint MODEM and CODEC detection schemes for DSRC coded-fsk systems over high mobility fading channels, in Proc. Adv. Commun. Technol.Jan. 2013, pp [7] F. Ahmed-Zaid, F. Bai, S. Bai, C. Basnayake, B. Bellur, S. Brovold,et al., Vehicle safety communications Applications (VSC-A) final report, U.S. Dept. Trans., Nat. Highway Traffic Safety Admin., Washington,DC, USA, Rep. DOT HS , Sep [8] J. B. Kenney, Dedicated short-range communications (DSRC) standards in the United States, Proc. IEEE, vol. 99, no. 7, pp ,Jul [9] J. Daniel, V. Taliwal, A. Meier, W. Holfelder, and R. Herrtwich, Design of 5.9 GHz DSRC-based vehicular safety communication, IEEE Wireless Commun. Mag., vol. 13, no. 5, pp , Oct [10] I.-M. Liu, T.-H. Liu, H. Zhou, and A. Aziz, Simultaneous PTL buffer insertion and sizing for minimizing Elmore delay, in Proc. Int.Workshop Logic Synth., May 1998, pp Available online: P a g e 1589