Design of local ESD clamp for cross-power-domain interface circuits

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1 This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* Design of local ESD clamp for cross-power-domain interface circuits Chun-Yu Lin a), Yu-Kai Chiu and Shuan-Yu Yueh Department of Electrical Engineering, National Taiwan Normal University No. 162, Section 1, He-ping East Road, Taipei 106, Taiwan a) Abstract: To effectively protect the cross-power-domain interface circuits from electrostatic discharge (ESD) damages, a PMOS-based local ESD clamp was proposed in this work. The test circuits of prior and proposed designs have been implemented in silicon chip. The proposed design has the small chip area, low leakage current, and low peak transient voltage; therefore, it can help to reduce the overstress voltages across the interface circuits under ESD tests. With the better performances, the proposed local ESD clamp can be a better solution for cross-power-domain interface circuits. Keywords: cross-power-domain interface circuits, electrostatic discharge (ESD). Classification: Integrated circuits References IEICE 2016 DOI: /elex Received August 17, 2016 Accepted September 16, 2016 Publicized October 7, 2016 [1] ESDA/JEDEC Joint Standard JS [2] C. Duvvury, et al.: Internal chip ESD phenomena beyond the protection circuit, IEEE Trans. Electron Devices 35 (1988) 2133 (DOI: / ). [3] Y. Koo and K. Lee: SCR-based ESD protection device with low trigger and high robustness for I/O clamp, IEICE Electron. Express 9 (2012) 200 (DOI: /elex.9.200). [4] G. Notermans, et al.: Gate oxide protection and ggnmosts in 65 nm, Proc. EOS/ESD Symp. (2008) 6. [5] N. Kitagawa, et al.: An active ESD protection technique for the power domain boundary in a deep submicron IC, Proc. EOS/ESD Symp. (2006) 196. [6] S.-H. Chen, et al.: Active ESD protection design for interface circuits between separated power domains against cross-power-domain ESD stresses, IEEE Trans. Device and Materials Reliability 8 (2008) 549 (DOI: /TDMR ). [7] S.-H. Chen, et al.: Local CDM ESD protection circuits for cross-power domains in 3D IC applications, IEEE Trans. Device and Materials Reliability 14 (2014) 781 (DOI: /TDMR ). 1

2 [8] J. Chun and C. Chen: Leakage power reduction using the body bias and pin reordering technique, IEICE Electron. Express 13 (2016) (DOI: /elex ). [9] C.-T. Wang and M.-D. Ker: Design of 2 VDD-tolerant power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm CMOS technology, IEEE Trans. Electron Devices 57 (2010) 1460 (DOI: /TED ). [10] M.-D. Ker and P.-Y. Chiu: New low-leakage power-rail ESD clamp circuit in a 65-nm low-voltage CMOS process, IEEE Trans. Device and Materials Reliability 11 (2011) 474 (DOI: /TDMR ). [11] F. Ma, et al.: Investigation of boundary-mos-triggered SCR structures for on-chip ESD protection, Electronics Letters 47 (2011) 246 (DOI: /el ). [12] M.-D. Ker and S.-H. Chen: Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology, IEEE J. Solid-State Circuits 42 (2007) 1158 (DOI: /JSSC ). 1 Introduction Multiple power domains are used in a chip, such as digital/analog circuit blocks, mixed-voltage circuit blocks, 3-dimension (3D) integrations, and other specified circuit considerations. To evaluate the ESD robustness of the chip, the ESD tests across separated power domains are also specified in the ESD-test standards [1]. These ESD tests may cause damages at cross-power-domain interface circuits beyond the ESD protection circuits of I/O cells [2, 3]. Therefore, several ESD protection designs have been presented to avoid ESD damages at the cross-power-domain interface circuits [4, 5, 6, 7]. The back-to-back diodes have been generally used to connect the separated power domains, as shown in Fig. 1. The back-to-back diodes with the assistance of power-rail ESD clamp circuits can conduct the ESD currents under cross-power-domain ESD stresses. To further reduce the overstress voltages across the interface circuits, the local ESD clamp has been applied to the separated power domains [6, 7], as shown in Fig. 1. Although the primary ESD currents are discharged through the back-to-back diodes and power-rail ESD clamp circuits, the local ESD clamp can help to reduce the overstress voltages across the interface circuits. The local ESD clamp must be rapidly triggered and have low clamping voltage. Besides, the area and leakage Fig. 1. ESD protection for cross-power-domain interface circuits. 2

3 current must be considered during the circuit design [8, 9]. For example, Fig. 2(a) shows a prior design of the local ESD clamp [7]. It was known the leakage current of NMOS was often larger than that of PMOS with the same dimension in advanced CMOS process [10]. In this work, one improved local ESD clamp with PMOS-based design for the cross-power-domain interface circuits is proposed and verified in a 0.18μm CMOS process. 2 Design and verification of local ESD clamp In order to effectively protect the cross-power-domain interface circuits from ESD damages, the turn-on speed of local ESD clamp is wished to be as fast as better. The initial-on ESD protection concept with PMOS-based ESD clamp was ever presented in the literature [11, 12]. The PMOS device is initially on as the IC is floating without any power bias, but it is kept off as the IC is in the normal circuit operation conditions. In this work, the PMOS-based ESD clamp is further applied to the local ESD clamp. Fig. 2(b) shows the proposed design with the initial-on concept. In this design, six transistors are designed to control the clamp device of PMOS (M Pclamp ). Under ESD stress condition, the gate of M Pclamp is biased at low voltage, and the M Pclamp is turned on to protect the interface circuits. While normal circuit operating condition, the gate of M Pclamp is biased at high voltage, and the M Pclamp is kept off. Both prior and proposed designs have been designed and simulated in a 0.18μm CMOS process. In both circuits, the dimensions of clamp devices (M Nclamp and M Pclamp ) are 120μm/0.36μm. Figs. 3(a)~(f) explain the operation of each transistor under all conditions. Under ESD stress condition, the current flows of prior and proposed designs are shown in Figs. 3(a) and 3(d), respectively. Under normal circuit operation with power-on VDD 2, the on/off states of transistors in prior and proposed designs are shown in Figs. 3(b) and 3(e), respectively. Under normal circuit operation with power-down VDD 2, the on/off states of transistors in prior and proposed designs are shown in Figs. 3(c) and 3(f), respectively. Besides, Fig. 4(a)~(f) show the transient voltage at each node of prior and proposed designs under all conditions. These simulation results confirm that each transistor can operate as expected. Fig. 2. (a) Local ESD clamp of (a) prior design and (b) proposed design. (b) 3

4 (a) (b) (c) (d) (e) (f) Fig. 3. Operations of prior design under (a) ESD stress, (b) normal power on, and (c) normal power down. Operations of proposed design under (d) ESD stress, (e) normal power on, and (f) normal power down. (a) (b) (c) (d) (e) (f) Fig. 4. Simulated transient voltages of prior design under (a) ESD stress, (b) normal power on, and (c) normal power down. Simulated transient voltages of proposed design under (d) ESD stress, (e) normal power on, and (f) normal power down. 4

5 The test circuits have been fabricated in a 0.18μm CMOS process. Fig. 5 shows the layout top view and chip micrograph of test circuits. The prior and proposed designs occupy the chip areas of 32 14μm 2 and 37 14μm 2, respectively. In order to observe the turn-on behavior of the local ESD clamp, the transmission-line-pulsing (TLP) system is used to generate the pulses in the time domain of ESD event. The transient voltage and current waveforms can be captured. For example, as the ESD-like pulse is equal to ~60mA in quasi-static state, Fig. 6 shows the measured voltage and current waveforms. The proposed design has the lower peak transient voltage across the local ESD clamp, so it can be used to effectively protect the cross-power-domain interface circuits. Fig. 5. circuits. Chip micrograph (upper) and layout top view (lower) of test (a) (b) Fig. 6. Measured transient voltage and current waveforms of (a) prior design and (b) proposed design. 5

6 Under normal circuit operating condition, both test circuits are kept off with some leakage current. As 3.3V supplied across local ESD clamp, the leakage currents of prior and proposed designs at room temperature are 1.03nA and 0.36nA, respectively. All the design parameters and measured characteristics are summarized in Table I. 3 Comparison The local ESD clamp with small chip area, low leakage current, and low peak transient voltage is desired. The figure of merit (FOM) used in this work: FOM 1 Area (1) Leakage V peak where Area means the chip area of local ESD clamp, Leakage is measured under 3.3V bias at room temperature, and V peak denotes the peak transient voltage. The FOM of prior and proposed designs are /m 2 *Ω and /m 2 *Ω, respectively, as listed in Table I. Therefore, the proposed design can achieve the better FOM. Table I. Design parameters and measurement results of test circuits Clamp Test Circuit Device Area (μm 2 Leakage FOM ) V (na) peak (V) (10 15 /m 2 *Ω) (μm/μm) Prior 120/ Proposed 120/ Conclusion The new local ESD clamp realized with the initial-on concept is proposed for cross-power-domain interface circuits. Verified in silicon chip, the proposed design has the small chip area, low leakage current, and low peak transient voltage. Such local ESD clamp can help to efficiently protect the cross-power-domain interface circuits from ESD damages. Acknowledgments This work was supported by Ministry of Science and Technology, Taiwan, under Contract MOST E CC2. The authors would like to thank National Chip Implementation Center (CIC), Taiwan, for the support of chip fabrication. 6