組込みシステムシンポジウム2013 Embedded Systems Symposium 2013 ESS /10/17 Java JavaRock-Thrash LSI HDL Java JavaRock-Thrash FIR FFT IP Developm

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1 Java JavaRock-Thrash LSI HDL Java JavaRock-Thrash FIR FFT IP Development of JavaRock-Thrash : a High Level Synthesis tool based on Java language Keisuke Koike, Takefumi Miyoshi, Satoshi Funada and Hironori Nakajo In recent years, as designing an LSI is getting more complex, high level synthesis has been expected to be a useful designing tool. However, running frequency and occupied resource of a circuit designed with a high level synthesizer are sometimes inferior to those designed with an HDL. In this research, we have been developing a high level synthesizer called JavaRock- Thrash with mechanisms for speedup and reducing circuit scale based on designing with a Java language. In designing circuits of an FIR filter and an FFT with our tool, comparing with designing with IP cores, though circuit sizes are times as large as ones of IP cores, execution time is limited up to 1.7 times slower. From this results, our tool can be expected to be applied for hardware acceleration or prototyping of LSI design. 1. LSI RTL FPGA FPGA ASIC / Tokyo University of Agriculture and Technology e-trees.japan, Inc. FPGA HDL FPGA HDL Stream-C 5) HDL 3 ( 1 ) ( ) ( 3 ) (3) 41

2 7) (1) () JavaRock 1)13) Java VHDL Java Java Java Java JavaRock Java Verilog HDL JavaRock-Thrash JavaRock-Thrash..1 Java JavaRock 1)13) MaxCompiler ), Liquid Metal 3), Sea Cucumber 10) Java JavaRock-Thrash 1 JavaRock JavaRock- Thrash Java JavaRock VHDL JavaRock-Thrash Verilog HDL JavaRock JavaRock-Thrash Data Flow Graph DFG JavaRock 1 1 JavaRock-Thrash 1 MaxCompiler ) Liquid Metal 3) Java Java JavaRock-Thrash JavaRock-Thrash JavaRock-Thrash 5. Sea Cucumber 10) JavaRock JVM Java JavaRock-Thrash JavaRock-Thrash Sea Cucumber Java JavaRock-Thrash Java Verilog HDL 10) HDL JavaRock-Thrash new Sea Cucumber Java Verilog HDL 4

3 . DFG ILP 9) Force-Directed Scheduling 8) ASAP 1) 6) JavaRock-Thrash ASAP DFG 1) 11) 1) 1 JavaRock-Thrash FPGA LUT 3. JavaRock-Thrash 1 JavaRock-Thrash JavaRock-Thrash Java config Java Verilog HDL config xml IP / JVM Verilog HDL config 1.v JavaRock-Thrash/ Verilog HDL 作成部 入力ファイル Java Compiler Frontend 出力ファイル.java Java Compiler Backend.class JavaRock-Thrash Fig. 1 compilation flow of java 1 class TopClass{ 3 int numx; 4 final int[] arrayx = new int[104]; 5 final SubClass sub = new SubClass(); 6 } 7 8 class SubClass{ 9 11 short numa; 1 14 double numb; 15 } Java Fig. An example of converting member variables Java source code 1 Verilog HDL Java OpenJDK Verilog HDL DFG, CFG Control Flow Graph Verilog HDL 4. JavaRock-Thrash JavaRock-Thrash Java 4.1 JavaRock-Thrash Verilog HDL TopClass SubClass 3 TopClass SubClass JavaRock-Thrash Java 43

4 o_submod_numa i_submod_numb i_fld_matx_addr_0 i_fld_matx_datain_0 o_fld_matx_dataout_0 i_fld_matx_r_w_0 TopClass SubClass sub o_fld_numa i_fld_numb addr_0 datain_0 dataout_0 r_w_0 DualPortRAM arrayx D-FF numx 3 3 D Q addr_1 datain_1 dataout_1 r_w_1 3 Fig. 3 An example of converting member variables block diagram 1 class ClassX{ 3 int average(int datanum, int[] matx){ 4 5 } 6 } 4 Java Fig. 4 An example of converting method and parameter list Java source code final RAM FPGA RAM SubClass JRThrashExtToTop RAM I/O JRThrashReadOnlyPort I/O 4. JavaRock-Thrash req busy addr_0 datain_0 Dual Port RAM dataout_0 r_or_w_0 addr_1 datain_1 dataout_1 r_or_w_ ClassX average_req average_busy average_return average_datanum average_matx_addr average_matx_datain average_matx_dataout average_matx_r_w 5 Fig. 5 An example of converting method and parameter list block diagram return 4 average 5 RAM RAM 5 5. JavaRock-Thrash Java Java RTL JavaRock-Thrash IP IP Java IP 7) RTL 44

5 1 class TopClass{ 3 final SubClass suba = new SubClass(); 4 final SubClass subb = new SubClass(); 5 6 void startthreads(){ 7 8 // 9 suba.start(); 10 subb.start(); 11 1 try{ 13 // 14 suba.join(); 15 subb.join(); } 17 catch(exception e){} 18 } 19 } 0 1 class SubClass extends Thread{ 3 public void run(){ 4 5 } 6 } unrolltype = JRThrash.pipeline 3 unrollnum = 4, 4 loopvariablename = i ) 5 6 public void multstream(){ 7 8 for(int i=0; i<18; ++i) 9 c[i] = a[i] * b[i]; 10 } Fig. 7 7 A description example of loop unrolling 1 public void multstream(){ 3 for(int i=0; i<18; i+=4){ 4 c[i] = a[i] * b[i]; 5 c[i+1] = a[i+1] * b[i+1]; 6 c[i+] = a[i+] * b[i+]; 7 c[i+3] = a[i+3] * b[i+3]; 8 } 9 } Fig. 6 6 Java A description example of Java Thread 8 Fig. 8 Loop after unrolling Java TopClass SubClass suba, subb TopClass SubClass Thread SubClass start SubClass run start 6 10 SubClass join synchronized wait notify multstream JRThrashUnroll JavaRock-Thrash 8 a[i] b[i] a[i+1] b[i+1] c[i] c[i+1] contorol step a[i+] b[i+] a[i+3] b[i+3] c[i+] 8 c[i+3] 9 9 Fig. 9 An example of scheduling the unrolled loop unrollnum loop- VariableName unrolltype 3 unrollnum loop- VariableName unrolltype a b for

6 availablenum = 45, latency = 0, 3 throughput = 1, outputpname = p, 4 5 ) 6 int MAC(short a, short b, int c){ 7 return (int)(a*b+c); 8 } 9 10 public void macstream(){ 11 1 for(int i=0; i<18; ++i) 13 w[i] = MAC(x[i], y[i], z[i]); 14 } 10 Fig. 10 A description example of defining a computing unit with a method 3 MAC a b p c p = a*b+c 11 MAC Fig. 11 A computing unit defined with a MAC method MAC JRThrashConverted- IntoIPcore IP IP 10 MAC 11 IP JavaRock-Thrash IP macstream MAC IP 6. JavaRock-Thrash config config 3 DSP IP IP IP IP IP RAM RAM RAM. JavaRock-Thrash 7. JavaRock-Thrash FIR FFT IP JavaRock-Thrash Xil- 1 FIR Table 1 Features of the Fir Filter bit 33 Filter Architecture Transpose Multiply Accumulate IP 46

7 inx ISE 13.4 Core Generator Virtex-5 xc5vlx50t LUT DSP 7 FIR 1 FIR JavaRock-Thrash IP 048 FFT FFT IP JavaRock-Thrash Cooley- Tukey IP Cooley-Tukey Radix- Lite Core Generator FIR 3 FIR JRT IP FFT 4 FFT JRT IP FIR 4.0 JavaRock-Thrash IP 8.1 JRT LUT IP 4.7 JavaRock-Thrash FFT Table Features of the FFT 104 radix-/cooley-tukey Implementation Options(IP ) radix- Lite LUT 3 JRT IP.7 LUT LUT 8. for 8.3 FIR FFT 4 3 JRT LUT FIR LUT 4.7 FFT LUT.9 FFT FIR FIR JavaRock- Thrash JavaRock-Thrash 8.4 HDL HDL JavaRock- Thrash 4) 64 FFT Cooley-Tukey FPGA XC3S MHz 4 JavaRock-Thrash 4) ) FPGA FPGA 4) 64 JavaRock-Thrash HDL 47

8 Table 3 3 IP JavaRock-Thrash FIR Comparison of the IP core and the circuit generated JavaRock-Thrash FIR Filter reg lut slice DSP [MHz] [ms] IP JRT Table 4 4 IP JavaRock-Thrash FFT Comparison of the IP core and the circuit generated JavaRock-Thrash FFT reg lut slice DSP [MHz] [µs] IP JRT JavaRock-Thrash Java FIR FFT IP RTL 1) High-level synthesis. ) Maxeler technologies. maxcompiler. 3) Joshua Auerbach, David F. Bacon, Perry Cheng, and Rodric Rabbah. Lime: a javacompatible and synthesizable language for heterogeneous architectures. Proceedings of the ACM International Conference on Object Oriented Programming Systems Languages and Applications, Vol. 45, No. 10, pp , October ) Arman Chahardahcherik, Yousef S. Kavian, and Otto Strobel andridha Rejeb. Implementing fft algorithms on fpga. IJCSNS International Journal of Computer Science and Network S 148 ecurity, Vol. 11, pp , ) Maya B. Gokhale, Janice M. Stone, Jeff Arnold, and Mirek Kalinowski. Streamoriented fpga computing in the streams-c high level language. Proceedings of the 000 IEEE Symposium on Field-Programmable Custom Computing Machines, pp , ) M. J. M. Heijligers and J. A. G. Jess. Highlevel synthesis scheduling and allocation using genetic algorithms based on constructive topological scheduling techniques. Proceedings of the ASP-DAC95/CHDL95/VLSI95. Asia and South Pacific Design Automation Conference. IFIP International conference on Computer Hardware Description Languages and their Applications. IFIP International Conference on Very Large Scale Integration, pp , ) Jamshaid Sarwar Malik, Paolo Palazzari, and Ahmed Hemani. Effort, resources, and abstraction vs performance in high-level synthesis: finding new answers to an old question. SIGARCH Comput. Archit. News, Vol.40, No. 5, pp , March 01. 8) Pierre G. Paulin and John P. Knight. Forcedirected scheduling for the behavioral synthesis of asics. IEEE Trans. on CAD of Integrated Circuits and Systems, pp , ) S. Tosun, O. Ozturk, N. Mansouri, E. Arvas, M. Kandemir, Y. Xie, and W-L. Hung. An ilp formulation for reliability-oriented highlevel synthesis. Proceedings of the 6th International Symposium on Quality of Electronic Design, pp , ) Justin L. Tripp, Preston A. Jackson, and Brad Hutchings. Sea cucumber: A synthesizing compiler for fpgas. Proceedings of the Reconfigurable Computing Is Going Mainstream, 1th International Conference on Field-Programmable Logic and Applications, pp , ) Chu yi Huang, Yen shen Chen, Youn long Lin, and Yuchin Hsu. Data path allocation based on bipartite weighted matching. Matching, Proceedings of the IEEE Design Automation Conference, pp , ),. Fpga java. 53, pp , ),. Javarock hw/sw.. AI,, Vol. 11, No. 70, pp ,