MetaRTL: Raising the Abstraction Level of RTL Design
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1 MetaRTL: Raising the Abstraction Level of RTL Design Jianwen Zhu Electrical and Computer Engineering University of Toronto March 16, zhu DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 1 Outline Motivation Previous work Problems of synthesizable HDL MetaRTL Results DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 2
2 Importance of RTL Abstraction RTL abstraction Semantics: FSMD (Gaski) Synthesizable VHDL/Verilog (IEEE) Established industrial standard for ASIC design Backend interface for higher level design de facto soft IP exchange standard DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 3 Problems of Synthesizable HDLs Designed as a simulation language. Not designed with design reuse in mind. Not designed with a type system as powerful as that of software languages. Do not provide any abstractions for memories. Do not simulate fast enough at the RTL level. DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 4
3 Outline Motivation Previous work Problem of synthesizable HDL MetaRTL Results DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 5 Library-Based Approach Syntactically existing language: Defines a programming style for hardware modeling Simulation convenience: simulator for free (g++) Semantically new language: Squeeze new semantics into old constructs Synthesis headache: which semantics should I apply? Efforts: SystemC: Cynlib: OCAPI: Schaumont et. al. DAC 99 DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 6
4 Language-Based Approach New language Defines a computational model (semantics) Defines language construct (syntax) to capture the model Compilation overhead: needs a new compiler Unambiguous synthesis Efforts Numerous work on parallel extension of C/C++ OOVHDL: IEEE working group VHDL+: extension of VHDL Superlog: extension of Verilog with C constructs V++: complete new language for synchronous reactive semantics DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 7 Our Approach Semantic level: Rethink what should be abstracted away, what should not Address the problems to be described Raise the abstraction level of RTL design Syntax level Can be applied to library-based SLDL Can be embedded into C-based SLDL DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 8
5 Outline Motivation Previous work Problems of synthesizable HDLs MetaRTL Results DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 9 Simulation Semantics HDL designed for simulation How to synthesize delay How to synthesize signal synthesis subset Problematic constructs excluded Infer hardware that exhibits discrete event semantics if( a = 0 ) then c <= b; end if; b a c DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 10
6 Design Reuse Hardware reuse by component instantiation Not sufficient for sequential components No interface protocol captured u1 : Comp( start, done, din, dout ); start = 1 ; for in in 0 to 8 do wait until clk event and clk = 1 ; din <= a(i); end for; while( done = 0 ) do wait until clk event and clk = 1 ; start <= 0 ; end while; while( done = 1 ) do wait until clk event and clk = 1 ; b() := dout; := + 1; end while; Component user s interface code start done Comp din dout DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 11 Type System Type system: most effective error prevention in software Untyped system in synthesizable HDL enumerate type bit vector More abstract data type needed at RTL level DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 12
7 Memory Abstraction Any interesting application involves the use of memory Multimedia: data sample storage Networking: routing table, protocol states No abstraction of memory at RTL level Interface protocol with memory Dynamic allocation: pointer concept Address calculation: array and record access struct { int field1; struct { char field3; } field2; } *p1; short a, *p2; char b[10]; a = 0; b[3] = a ; p1 >field1 = 1; p1 >field2.field3 = 2; p2 = &a; DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 13 Outline Motivation Previous work Problems of synthesizable HDLs MetaRTL Results DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 14
8 MetaRTL Overview Syntactic-sugar-free, obect-oriented, polymorphic language Difference from imperative program Specifies hardware obects Field has modifiers: storage class always method: component logic public method: interface protocol DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 15 MetaRTL Syntax MetaRTL ::= (Class)* Class ::= class ID [[ Formal (, Formal)* ] ] f (Field Method)* g Type ::= ID [[ Actual (, Actual)* ] ] Formal ::= class ID Type ID Actual ::= Type Expr Field ::= sclass Type ID [ = Expr ]; sclass ::= in out inout reg wire latch Type Method ::= [ always public] Type ID [ ( Param (, Param)* ] ) f (Stmt)* g Param ::= [ in out inout ] Type ID Stmt ::= [LeftValue = ] Expr ; if ( Expr ) Stmt [else Stmt] switch ( Expr ) (CaseStmt)+ [ID] : Stmt do Stmt while( Expr ); while (Expr) Stmt break ; return Expr ; CaseStmt ::= case Expr : Stmt default : Stmt Expr ::= Literal this LeftValue Expr.ID([ Expr (, Expr)* ] ) LeftValue ::= ID Type.ID Expr.ID DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 16
9 Synthesis Semantics Field 7! Storage in, out, inout fields 7! ports wire field 7! wire latch, reg fields 7! registers Normal field 7! memory Method 7! Logic Assignment: predicated connection semantics Method dispatch: protocol inlining Statement: logic State label: state boundary DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 17 Type System Arithmetic data types used in place of bit vectors Polymorphism Parameterize over constants Parameterize over type Subtyping: extensible hardware design DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 18
10 Design Reuse Type system improves reuse Explicit capture of interface protocol Combinational components: connection and glue logic Sequential components: partial FSMD Port mapping is replaced by method dispatch DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 19 Memory Abstraction Obect reference and array, field access Access by name vs access by explicit address Memory bank and address allocation left to synthesis tool Automatic insertion of memory interface protocol DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 20
11 Outline Motivation Previous work Problems of synthesizable HDLs MetaRTL Results DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 21 Implementation Embed MetaRTL in experimental SLDL MetaSyn: MetaRTL 7! synthesizable VHDL MetaJ MetaC Parse Inter proc. Analysis Memory Allocation VHDL HDL export FSMD extraction Protocol Inlining DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 22
12 Experimental Result Toronto DSP benchmark set TSMC 0.35um technology Completed by Mr. Prakash: first year undergraduate before any digital logic courses Benchmark MetaC VHDL Area (#lines) (#lines) (um 2 ) fft fir iir latnrm lmsfir mmult smult sra DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 23 Conclusion RTL semantics can be made more abstract RTL syntax can be as simple as one page Future work Synthesis algorithms Embedding in SLDL DATE 2001, Munich Copyright c Jianwen Zhu, 2000, ECE, Univ. of Toronto 24
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