Cadence Virtuoso Simulation of a pixel

Size: px
Start display at page:

Download "Cadence Virtuoso Simulation of a pixel"

Transcription

1 MEMS AND MICROSENSORS 2018/2019 Cadence Virtuoso Simulation of a pixel 11/12/2018 Giorgio Mussi giorgio.mussi@polimi.it Introduction In this lab, we will use Cadence Virtuoso to simulate a sub-array of 4 pixels of a 3T CMOS image sensor. We will learn how to launch Cadence Virtuoso, how to use the Schematic Editor to add instances in our circuit, and how to use the Analog Design Environment (ADE) to run simulations. We will first place the components from scratch, using the Schematic Editor. Then, we will open a preconfigured schematic and we will use the ADE to simulate it. The pre-configured schematic contains 4 pixels that belong to 4 different rows of the same column of a CMOS image sensor used for 25-fps video acquisition. The readout method is based on the rolling shutter architecture. With the help of the ADE, we will be able to evaluate: the full-well charge (the maximum photocurrent), and its limitation due to DC voltage drops; the non-linearity related with the depletion capacitance of the photodiode; timing issues related with the readout of a matrix of pixel. Used models will be ideal: unfortunately, we do not have access to a Process Design Kit (PDK). Hence, some simulation details will be inaccurate due to the non-accurate modelization of the devices. In addition, the lack of the PDK does not allow us to layout our pixel, as there s no layout associated with our ideal components.

2 Environment Setup Linux Environment Setup As first step, you need to start the Linux environment where Cadence Virtuoso tools are installed. Open virtualdesktop in your web browser: and log in with your Polimi account. Open NX Client, and wait until the Linux environment opens. Once the environment is ready, you will be able to launch Cadence Virtuoso.

3 Library Import Before starting to use the software, you need to import a library required for simulations. The library is a compressed file that contains the model of the transistor. You need to extract it in the proper folder. Open Firefox (in Linux, not in Windows), browse to ftp://ftp.elet.polimi.it/outgoing/giacomo.langfelder/mems_and_microsensors_fem_modes_videos/e18/. Click on MEMIS16.tar, to download the file. Save it (do not open it) in your Download folder. Move the downloaded file into your Home folder (/data/home/guest0xxx).

4 Open the Linux terminal: Applications > System Tools > Terminal. Type tar -xvf MEMIS16.tar and press enter. The file is now extracted. Check your Home folder. You should now find a folder named MEMIS16. Cadence Virtuoso Launch Now you can launch Cadence Virtuoso. Open the Terminal, type virtuoso.sh and press ENTER. Cadence Virtuoso should start. The opened window is called CIW (Command Interpreter Window). Close What s New tab.

5 Now you need to add the imported library (MEMIS16) to Cadence Virtuoso. Open the Library Manager, the tool where you can manage your designs: from the CIW, Tools > Library Manager. The Library Manager window will appear.

6 From the Library Manager, Edit > Library Path. A Read Only File pop-up appears, press OK. Add the library: in the Library Path Editor window, Edit > Add Library. Browse through your Home folder (/data/home/guest0xxx), using the drop-down menu.

7 Select MEMIS16 Library and press OK. A new library, in blue, will appear in the Library Path Editor.

8 Save the library definition list. From the Library Path Editor, File > Save As. In the Files To Save section, click on BROWSE Change the path to your Home. You can find it on the left-most side of the window. Press SAVE, then OK.

9 You should now find the MEMIS16 library as the first entry in the Library column of the Library Manager. You are ready to use Cadence Virtuoso.

10 Schematic Entry We are ready to design our pixel. To open a new schematic cell, from the Library Manager, first click on MEMIS16, then go to File > New > Cell View. The library is MEMIS16. Name the cell pixel. Check that schematic type is chosen. Every time a license pop-up appears, click Always. The Schematic Editor is now open.

11 You can use ftp://ftp.elet.polimi.it/outgoing/paolo.minotti/mems_and_microsensors/e19/cadence-seshortcuts.pdf as a reference for schematic entry shortcuts! As first instance, place the photodiode. Press I (keyboard shortcut), then browse to ahdllib > diode_sch. Click CLOSE. Set the parameters of the diode as shown. area is the area of the photodiode: name it as L*L, assuming a square photodiode, whose side is L. is is the dark current density. cjo is the depletion capacitance density.

12 Once all the parameters are correctly entered, click Hide. You can use either scientific or engineering notation. The engineering suffix should be placed right after the number, with no space. Hence, 10u is 10 micro and 20K is 20 thousands. If you enter a number with decimals, e.g. 0.5, always double check that between the 0 and the 5 there is a dot and not a comma. If you don t write a number as an entry, but you use a variable, e.g. L, you can defer to the simulator (ADE) the choice of the value of that parameter. Before placing the instance in your schematic (by just clicking with the left button of your mouse), press R twice, so that you rotate it, thus having the cathode above the anode. Place instances not too close one each other; this will make the visualization of your schematic easier. While placing an instance, if you press F3, a pop-up appears; you can change the properties of the instance you are adding, e.g., you can change the orientation, you can flip it If you want to stop a command from being active, press Esc. If you want to change the properties of an instance, click on it, then press Q. The model of this photodiode includes the depletion capacitance non-linearity.

13 Place the photocurrent generator, a current source: press I, then browse to analoglib > idc. Put iph1 as DC current. When you enter a value, do not write the unit (m, V, A ): it will be updated automatically.

14 Place the supply voltage source: press I, analoglib > vdc. Insert 3 as DC voltage. Place the reset signal generator: press I, analoglib > vpulse. Insert the parameters as below. tfr is the inverse of the frame rate: how often are we taking a picture, i.e. how often are you resetting the pixels? tdelay is the reset delay. Assuming a rolling shutter readout technique, this is the first pixel that will be reset, i.e. delay is 0. If you have more than one pixel on the same column, the second one will have a 1*tdelay delay, the third one will have a 2*tdelay delay, and so on treset is the reset time interval, during which the reset transistor is kept closed.

15 Place the three transistors, with minimum size, 350 nm: press I, MEMIS16 > mos_level2. Insert the parameters as below. Place three of them: reset switch, source follower, row-selection switch. Rotate them as shown.

16 Place two capacitors: press I, analoglib > cap. You need to place two capacitors, because the model of the MOS transistor in MEMIS16 library does not include parasitic capacitances. You need to add a capacitor from the integration node to ground, and a capacitor from the gate to the source. Use CT as the value of the capacitance to ground, and 10a as the value of the gate-source capacitance. Place the row-selection voltage signal. You can copy the reset generator, as their properties will be similar. Click on the reset voltage source, press C, click to select the reference point for copy, then click to select the destination point for copy. Place the vpulse instance below the gate of the row-selection transistor. Select the just-added vpulse instance, press Q. Change its parameters as below. You need to change the delay time, i.e. when we want to readout this pixel: you need to wait treset, then tint (the integration time), then 0*tdelay as this is the first pixel that will be read out. If you have other pixels in the column, they will have a constantly increasing delay time. treadout is the readout time, i.e. the time the row-selection switch is closed.

17 Place the DC current source that will bias the source follower when the row-selection switch is closed: press I, analoglib > idc, and use 2u as DC current. Finally, below everything, we can place the ground instance, that defines the zero-volt potential: press I, analoglib > gnd. Now you need to properly connect all the instances. Follow the diagram below. You should connect the instances through wires (shortcut W), and connect the proper terminals together. If you want to start a wire, press W. If you want to stop placing wires, press Esc. If you want to suddenly end a wire, double tap the left mouse button. Remember to connect the bulk of the transistors with the source. In this lab, body effect is not simulated, but if you leave the bulk un-connected, any simulation will fail. The final schematic is shown in the next page.

18

19 Simulation For sake of simplicity, we will simulate a pre-configured schematic, so that we are sure that everything is set up properly. Always Check and save your design before running any simulation. From the Library Manager, select the 4pix cell in MEMIS16 library, and open the schematic view.

20 The schematic will open. In blue you find the net labels. They are used both for connecting terminals, without the need to connect them with a schematic wire, and for simulation outputs referencing. You will find 4 pixels. Imagine that they that belong to the same column of a CMOS image sensor.

21 Using the right button of the mouse, you can zoom on the pixel at the bottom, which is basically the same structure you designed in the Schematic Entry section.

22 Analog Design Environment Setup You can launch the Analog Design Environment, and load a pre-configured simulation state. From the Schematic Editor, Launch > ADE L. An empty ADE appears.

23 Load the pre-configured simulation state: from ADE window, Session > Load State. A window appears. In Load State Option (upper section of the window), select Cellview, then press OK.

24 The ADE window is now populated. Three different tabs are present: Design Variables, Analyses, Outputs. Design Variables In this tab you can easily change the parameters of your circuit before running any simulation. E.g., you can change the photocurrent of the first pixel (iph1), or you can change the size of the photodiode (L). fr Frame Rate [Hz] tdelay Delay time between subsequent rows (with a rolling shutter readout) treset Reset duration treadout Readout duration CT Parasitic capacitance between the integration node and ground L Size of each photodiode, so that Area = L^2 tint Integration time iph1 Photocurrent of PIX1 iph2 Photocurrent of PIX2 iph3 Photocurrent of PIX3 iph4 Photocurrent of PIX4 tfr Frame Period [s]; tfr = 1/fr Analyses In this tab you can choose the type of simulation. In our case, we will run (i) a DC simulation, that will compute the DC voltages and the DC operating points of the circuit, and (ii) a TRAN simulation, that computes the response of the circuit as function of time. Outputs In this tab you can choose which variables/parameters/expression will be automatically evaluated/plotted after running any simulation. You can select them by selecting the corresponding Plot tickbox.

25 Run & Analysis Single-pixel analysis Tick all pixel1-related outputs. Press Play Button, on the right side of the ADE, to run the simulation.

26 Selected outputs are displayed in a graph. If you want to zoom in xy mode, use the right mouse button. If you want to zoom in x (horizontal) mode, press X, then use the right mouse button. If you want to zoom in y (vertical) mode, press Y, then use the right mouse button.

27 From ADE window, Results > Annotate > DC Node Voltages. Then, Results > Annotate > DC Operating Points. In the Schematic Editor, all terminals will have their DC (bias) voltage annotated. Which is the value of the DC voltage at the integration node (PIX1)? Which is the value of the DC voltage at the source of the source follower (OUT1)? Note that DC voltage of SEL1 was set to 3 V.

28 Maximum photocurrent You can set up a parametric sweep on iph1, e.g. from 1 aa, to 1 pa, to evaluate the maximum photocurrent. Tick PIX1 and OUT1. From ADE window, Tools > Parametric Analysis. Parametric Analysis window appears. In Add Variable box, select iph1. As start point, type 1a. As End Point, type 1p. As Total Steps, type 7. Press Play (in Parametric Analysis, not in ADE). The outputs are displayed in a graph. Size and/or adjust the window for better visualization. After running a parametric sweep, click on the + icon on the left-most side of the waveform window to browse through the different sweeps.

29 As expected, the higher the photocurrent, the higher the slope. For iph = 1 pa, the pixel is saturated. Note that the integration time was set to 15 ms. Saturation should be avoided within 15 ms, not 40 ms (40 ms = 1 / 25 Hz = 1 / 25 fps). Re-run the simulation, now from 40 fa, up to 400 fa. Which is the maximum photocurrent? It is enough to look at PIX1 to evaluate it? Which is the maximum voltage variation of the integration node?

30 Non-linearity We can run a parametric analysis on CT, to evaluate non-linearity effects. Tick PIX1 and OUT1. Set iph1 to 60f. Open the Parametric Analysis tool. In Add Variable box, select CT. As start point, type 1a. As End Point, type 10f. As Total Steps, type 6. Does the gain change when you change the parasitic capacitance value? Does the linearity of the photocurrent integration increase?

31 Timing & matrix readout Set iph1 to 10f. In ADE, tick all the outputs. Press Play in ADE window, to run the simulation.

32 Layout Here, some examples of a pixel layout. 64x64 matrix

33 High-density matrix

Cadence Schematic Tutorial. EEE5320/EEE4306 Fall 2015 University of Florida ECE

Cadence Schematic Tutorial. EEE5320/EEE4306 Fall 2015 University of Florida ECE Cadence Schematic Tutorial EEE5320/EEE4306 Fall 2015 University of Florida ECE 1 Remote access You may access the Linux server directly from the NEB Computer Lab using your GatorLink username and password.

More information

Using Cadence Virtuoso, a UNIX based OrCAD PSpice like program, Remotely on a Windows Machine

Using Cadence Virtuoso, a UNIX based OrCAD PSpice like program, Remotely on a Windows Machine Using Cadence Virtuoso, a UNIX based OrCAD PSpice like program, Remotely on a Windows Machine A. Launch PuTTY. 1. Load the Saved Session that has Enable X11 forwarding and the Host Name is cvl.ece.vt.edu.

More information

Revision Notes: July2004 Generate tutorial for single transistor analysis. Based on existing schematic entry tutorial developed for ECE410

Revision Notes: July2004 Generate tutorial for single transistor analysis. Based on existing schematic entry tutorial developed for ECE410 Cadence Analog Tutorial 1: Schematic Entry and Transistor Characterization Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revision Notes: July2004 Generate tutorial for

More information

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #2, Schematic Capture, DC Analysis, Transient Analysis (Inverter, NAND2)

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #2, Schematic Capture, DC Analysis, Transient Analysis (Inverter, NAND2) CPE/EE 427, CPE 527, VLSI Design I: Tutorial #2, Schematic Capture, DC Analysis, Transient Analysis (Inverter, NAND2) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville

More information

Experiment 0: Introduction to Cadence

Experiment 0: Introduction to Cadence UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE105 Lab Experiments Experiment 0: Introduction to Cadence Contents 1. Introduction...

More information

Cadence Tutorial: Schematic Entry and Circuit Simulation of a CMOS Inverter

Cadence Tutorial: Schematic Entry and Circuit Simulation of a CMOS Inverter Cadence Tutorial: Schematic Entry and Circuit Simulation of a CMOS Inverter Introduction This tutorial describes the steps involved in the design and simulation of a CMOS inverter using the Cadence Virtuoso

More information

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group.

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group. Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group. Revision Notes: Aug. 2003 update and edit A. Mason add intro/revision/contents

More information

S Exercise 1C Testing the Ring Oscillator

S Exercise 1C Testing the Ring Oscillator S-87.3148 Exercise 1C Testing the Ring Oscillator Aalto University School of Electrical Engineering Department of Micro- and Nanosciences (ECDL) 10.9.2014 1 1 Building the test bench In this exercise,

More information

Cadence Tutorial. Introduction to Cadence 0.18um, Implementation and Simulation of an inverter. A. Moradi, A. Miled et M. Sawan

Cadence Tutorial. Introduction to Cadence 0.18um, Implementation and Simulation of an inverter. A. Moradi, A. Miled et M. Sawan Cadence Tutorial Introduction to Cadence 0.18um, Implementation and Simulation of an inverter A. Moradi, A. Miled et M. Sawan Section 1: Introduction to Cadence You will see how to create a new library

More information

ECE 331: Electronics Principles I Fall 2014

ECE 331: Electronics Principles I Fall 2014 ECE 331: Electronics Principles I Fall 2014 Lab #0: Introduction to Computer Modeling and Laboratory Measurements Report due at your registered lab period on the week of Sept. 8-12 Week 1 Accessing Linux

More information

Cadence Virtuoso Schematic Design and Circuit Simulation Tutorial

Cadence Virtuoso Schematic Design and Circuit Simulation Tutorial Cadence Virtuoso Schematic Design and Circuit Simulation Tutorial Introduction This tutorial is an introduction to schematic capture and circuit simulation for ENGN1600 using Cadence Virtuoso. These courses

More information

Cadence IC Design Manual

Cadence IC Design Manual Cadence IC Design Manual For EE5518 ZHENG Huan Qun Lin Long Yang Revised on May 2017 Department of Electrical & Computer Engineering National University of Singapore 1 P age Contents 1 INTRODUCTION...

More information

Amplifier Simulation Tutorial. Design Kit: Cadence 0.18μm CMOS PDK (gpdk180) (Cadence Version 6.1.5)

Amplifier Simulation Tutorial. Design Kit: Cadence 0.18μm CMOS PDK (gpdk180) (Cadence Version 6.1.5) Amplifier Simulation Tutorial Design Kit: Cadence 0.18μm CMOS PDK (gpdk180) (Cadence Version 6.1.5) Yongsuk Choi, Marvin Onabajo This tutorial provides a quick introduction to the use of Cadence tools

More information

Intro to Cadence. Brady Salz. ECE483 Spring 17

Intro to Cadence. Brady Salz. ECE483 Spring 17 Intro to Cadence Brady Salz ECE483 Spring 17 What We re Doing Learn you a Cadence Learn simulation vocabulary Basic schematic guidelines Simulation results Init Before we begin, open a terminal: $ module

More information

EE 330 Spring 2018 Laboratory 2: Basic Boolean Circuits

EE 330 Spring 2018 Laboratory 2: Basic Boolean Circuits EE 330 Spring 2018 Laboratory 2: Basic Boolean Circuits Contents Objective:... 2 Part 1: Introduction... 2 Part 2 Simulation of a CMOS Inverter... 3 Part 2.1 Attaching technology information... 3 Part

More information

DC Circuit Simulation

DC Circuit Simulation Chapter 2 DC Circuit Simulation 2.1 Starting the Project Manager 1. Select Project Manager from the Start All Program Cadence Release 16.5 Project Manager. 2. Select Allegro PCB Designer (Schematic) from

More information

Tutorial on getting started in Cadence. Advanced Analog Circuits Spring 2015 Instructor: Prof. Harish Krishnaswamy TA: Jahnavi Sharma

Tutorial on getting started in Cadence. Advanced Analog Circuits Spring 2015 Instructor: Prof. Harish Krishnaswamy TA: Jahnavi Sharma Tutorial on getting started in Cadence Advanced Analog Circuits Spring 2015 Instructor: Prof. Harish Krishnaswamy TA: Jahnavi Sharma Getting Started Start Cadence from the terminal by using the command

More information

EE4111 Advanced Analog Electronics Design. Spring 2009 Experiment #4 April 6 ~ April 17

EE4111 Advanced Analog Electronics Design. Spring 2009 Experiment #4 April 6 ~ April 17 EE4111 Advanced Analog Electronics Design Spring 2009 Experiment #4 April 6 ~ April 17 Setup Cadence in VLSI Lab 1) Copy files $ cp r /home/grads/ee4111ta ~/ 2) Edit your.cshrc file -- Include the following

More information

Cadence Tutorial C: Simulating DC and Timing Characteristics 1

Cadence Tutorial C: Simulating DC and Timing Characteristics 1 Cadence Tutorial C: Simulating DC and Timing Characteristics Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group Last updated by Patrick O Hara SS15 Document Contents Introduction

More information

Process technology and introduction to physical

Process technology and introduction to physical Neuromorphic Engineering II Lab 3, Spring 2014 1 Lab 3 March 10, 2014 Process technology and introduction to physical layout Today you will start to learn to use the Virtuoso layout editor XL which is

More information

Figure 1: ADE Test Editor

Figure 1: ADE Test Editor Due to some issues that ADE GXL simulation environment has (probably because of inappropriate setup), we will run simulations in the ADE L design environment, which includes all the necessary tools that

More information

CS/EE 5720/6720 Analog IC Design Tutorial for Schematic Design and Analysis using Spectre

CS/EE 5720/6720 Analog IC Design Tutorial for Schematic Design and Analysis using Spectre CS/EE 5720/6720 Analog IC Design Tutorial for Schematic Design and Analysis using Spectre Introduction to Cadence EDA: The Cadence toolset is a complete microchip EDA (Electronic Design Automation) system,

More information

EE115C Digital Electronic Circuits. Tutorial 2: Hierarchical Schematic and Simulation

EE115C Digital Electronic Circuits. Tutorial 2: Hierarchical Schematic and Simulation EE115C Digital Electronic Circuits Tutorial 2: Hierarchical Schematic and Simulation The objectives are to become familiar with Virtuoso schematic editor, learn how to create the symbol view of basic primitives,

More information

Lab 2: Functional Simulation Using. Affirma Analog Simulator

Lab 2: Functional Simulation Using. Affirma Analog Simulator Lab 2: Functional Simulation Using Affirma Analog Simulator This Lab will go over: 1. Creating a test bench 2. Simulation in Spectre Spice using the Analog Design environment 1. Creating a test bench:

More information

Lab 1: An Introduction to Cadence

Lab 1: An Introduction to Cadence GIF-4201/GEL-7016 (Micro-électronique) Lab 1: An Introduction to Cadence Schematic, simulation and layout Gabriel Gagnon-Turcotte, Mehdi Noormohammadi Khiarak and Benoit Gosselin Department of Electrical

More information

Lab 1: Cadence Custom IC design tools- Setup, Schematic capture and simulation

Lab 1: Cadence Custom IC design tools- Setup, Schematic capture and simulation Lab 1: Cadence Custom IC design tools- Setup, Schematic capture and simulation Brittany Duffy EE 330- Integrated Electronics Lab Section B Professor Randy Geiger 1/24/13 Introduction The main goal of this

More information

Cadence Analog Circuit Tutorial

Cadence Analog Circuit Tutorial Cadence Analog Circuit Tutorial Schematic Entry for Analog Designs- Passive Circuits (RLC Circuit) In this tutorial, we will build the circuit shown in figure 1 below, using the Cadence Composer tool.

More information

VLSI Lab Tutorial 1. Cadence Virtuoso Schematic Composer Introduction

VLSI Lab Tutorial 1. Cadence Virtuoso Schematic Composer Introduction VLSI Lab Tutorial 1 Cadence Virtuoso Schematic Composer Introduction 1.0 Introduction The purpose of the first lab tutorial is to help you become familiar with the schematic editor, Virtuoso Schematic

More information

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group.

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revision Notes: Jan. 2006 Updated for use with spectre simulator

More information

Introduction to laboratory exercises in Digital IC Design.

Introduction to laboratory exercises in Digital IC Design. Introduction to laboratory exercises in Digital IC Design. A digital ASIC typically consists of four parts: Controller, datapath, memory, and I/O. The digital ASIC below, which is an FFT/IFFT co-processor,

More information

EECE 285 VLSI Design. Cadence Tutorial EECE 285 VLSI. By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski

EECE 285 VLSI Design. Cadence Tutorial EECE 285 VLSI. By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski Cadence Tutorial EECE 285 VLSI By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski 1 Table of Contents Purpose of Cadence 1) The Purpose of Cadence pg. 4 Linux 1) The Purpose of Linux

More information

ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS)

ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS) ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS) Objective Part A: To become acquainted with Spectre (or HSpice) by simulating an inverter,

More information

The original document link is

The original document link is Tutorial:Analog Artist with HSPICE The original document link is http://www.eda.ncsu.edu/wiki/tutorial:analog_artist_with_hspice This tutorial will introduce you to the Cadence Environment: specifically

More information

ECE471/571 Energy Efficient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30 am on Friday, February 2 nd, 2018

ECE471/571 Energy Efficient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30 am on Friday, February 2 nd, 2018 ECE471/571 Energy Efficient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30 am on Friday, February 2 nd, 2018 Introduction This project will first walk you through the setup

More information

CS755 CAD TOOL TUTORIAL

CS755 CAD TOOL TUTORIAL CS755 CAD TOOL TUTORIAL CREATING SCHEMATIC IN CADENCE Shi-Ting Zhou shi-ting@cs.wisc.edu After you have figured out what you want to design, and drafted some pictures and diagrams, it s time to input schematics

More information

Setting up an initial ".tcshrc" file

Setting up an initial .tcshrc file ECE445 Fall 2005 Introduction to SaberSketch The SABER simulator is a tool for computer simulation of analog systems, digital systems and mixed signal systems. SaberDesigner consists of the three tools,

More information

EE 330 Spring Laboratory 2: Basic Boolean Circuits

EE 330 Spring Laboratory 2: Basic Boolean Circuits EE 330 Spring 2013 Laboratory 2: Basic Boolean Circuits Objective: The objective of this experiment is to investigate methods for evaluating the performance of Boolean circuits. Emphasis will be placed

More information

Basic Analog Simulation in Cadence

Basic Analog Simulation in Cadence York University Department of Electrical Engineering and Computer Science EMIL Tutorial Series Tutorial #1 Basic Analog Simulation in Cadence In this tutorial we step through how to start Cadence (or at

More information

Virtuoso Schematic Composer

Virtuoso Schematic Composer is a schematic design tool from Cadence. In this tutorial you will learn how to put electrical components, make wire connections, insert pins and check for connection error. Start Cadence Custom IC Design

More information

Lesson 2: DC Bias Point Analysis

Lesson 2: DC Bias Point Analysis 2 Lesson 2: DC Bias Point Analysis Lesson Objectives After you complete this lesson you will be able to: Create a simulation profile for DC Bias analysis Netlist the design for simulation Run a DC Bias

More information

CADENCE SETUP. ECE4430-Analog IC Design

CADENCE SETUP. ECE4430-Analog IC Design CADENCE SETUP This short tutorial shows how to configure Cadence to use the NCSU Cadence Design Kit (CDK) with access to the ON Semiconductor C5 0.5-µm and the TSMC 0.35-µm CMOS processes libraries. In

More information

Microelectronica. Full-Custom Design with Cadence Tutorial

Microelectronica. Full-Custom Design with Cadence Tutorial Área Científica de Electrónica Microelectronica Full-Custom Design with Cadence Tutorial AustriaMicroSystems C35B3 (HIT-Kit 3.70) Marcelino Santos Table of contends 1. Starting Cadence... 3 Starting Cadence

More information

TUTORIAL II ECE 555 / 755 Updated on September 11 th 2006 CADENCE LAYOUT AND PARASITIC EXTRACTION

TUTORIAL II ECE 555 / 755 Updated on September 11 th 2006 CADENCE LAYOUT AND PARASITIC EXTRACTION TUTORIAL II ECE 555 / 755 Updated on September 11 th 2006 CADENCE LAYOUT AND PARASITIC EXTRACTION After finishing a schematic of your design (Tutorial-I), the next step is creating masks which are for

More information

Laboratory 3. EE 342 (VLSI Circuit Design) - Using Spectre netlist and Calculator for simulation

Laboratory 3. EE 342 (VLSI Circuit Design) - Using Spectre netlist and Calculator for simulation EE 342 (VLSI Circuit Design) Laboratory 3 - Using Spectre netlist and Calculator for simulation By Mulong Li, 2013 1 Background knowledge Spectre: is a SPICE-class circuit simulator. It provides the basic

More information

VLSI Lab Tutorial 3. Virtuoso Layout Editing Introduction

VLSI Lab Tutorial 3. Virtuoso Layout Editing Introduction VLSI Lab Tutorial 3 Virtuoso Layout Editing Introduction 1.0 Introduction The purpose of this lab tutorial is to guide you through the design process in creating a custom IC layout for your CMOS inverter

More information

EE 140/240A - Full IC Design Flow Tutorial

EE 140/240A - Full IC Design Flow Tutorial Original document by Filip Maksimovic & Mike Lorek, Spring 2015, derived from earlier EE141 lab manuals Revisions for IC6 by David Burnett & Thaibao Phan, Spring 2016 Revisions made by Nandish Mehta to

More information

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2019 HW5: Delay and Layout Sunday, February 17th Due: Friday,

More information

AMS 0.18 µm PDK Setup and Cadence Tutorial Contributors

AMS 0.18 µm PDK Setup and Cadence Tutorial Contributors AMS 0.18 µm PDK Setup and Cadence Tutorial Contributors Muhammad Ahmed, Sita Asar, and Ayman Fayed, Power Management Research Lab, https://pmrl.osu.edu, Department of Electrical and Computer Engineering,

More information

Click on the SwCAD III shortcut created by the software installation.

Click on the SwCAD III shortcut created by the software installation. LTSpice Guide Click on the SwCAD III shortcut created by the software installation. Select File and New Schematic. Add a component Add a resistor Press R or click the resistor button to insert a resistor.

More information

How To Plot Transconductance and Even More. By Ruida Yun

How To Plot Transconductance and Even More. By Ruida Yun How To Plot Transconductance and Even More By Ruida Yun g m /I d based methodology is preferred for short-channel length analog circuit design however there is no GUI support for this method in the current

More information

Professor Muller Fall 2016 Sameet Ramakrishnan Eric Chang Adapted from prior EE140 and EE141 labs. EE 140/240A Lab 0 Full IC Design Flow

Professor Muller Fall 2016 Sameet Ramakrishnan Eric Chang Adapted from prior EE140 and EE141 labs. EE 140/240A Lab 0 Full IC Design Flow Professor Muller Fall 2016 Sameet Ramakrishnan Eric Chang Adapted from prior EE140 and EE141 labs EE 140/240A Lab 0 Full IC Design Flow In this lab, you will walk through the full process an analog designer

More information

Introduction to CCV and Cadence Virtuoso for Electronic Circuit Simulation

Introduction to CCV and Cadence Virtuoso for Electronic Circuit Simulation Introduction to CCV and Cadence Virtuoso for Electronic Circuit Simulation Introduction ENGN1600 will be using the Cadence Virtuoso software suite for its circuit design and SPICE components. Part of the

More information

Logging in, starting a shell tool, and starting the Cadence Tool Suite

Logging in, starting a shell tool, and starting the Cadence Tool Suite EEE 4134 VLSI I Laboratory Lab 0 (Introductory Lab) Logging into Cadence Server, Tool Setup, Cell Library Creation, Introduction to Custom IC Design flow Objectives: To login, start a shell tool and start

More information

Virtuoso Layout Editor

Virtuoso Layout Editor This tutorial will cover the basic steps involved in using the Cadence layout editor called Virtuoso, extracting layout, and running simulation on the layout. The inverter layout is used as an example

More information

Design rule illustrations for the AMI C5N process can be found at:

Design rule illustrations for the AMI C5N process can be found at: Cadence Tutorial B: Layout, DRC, Extraction, and LVS Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revised by C Young & Waqar A Qureshi -FS08 Document Contents Introduction

More information

Lab 1: Analysis of DC and AC circuits using PSPICE

Lab 1: Analysis of DC and AC circuits using PSPICE Lab 1: Analysis of DC and AC circuits using PSPICE 1. Objectives. 1) Familiarize yourself with PSPICE simulation software environment. 2) Obtain confidence in performing DC and AC circuit simulation. 2.

More information

Using PSpice to Simulate Transmission Lines K. A. Connor Summer 2000 Fields and Waves I

Using PSpice to Simulate Transmission Lines K. A. Connor Summer 2000 Fields and Waves I Using PSpice to Simulate Transmission Lines K. A. Connor Summer 2000 Fields and Waves I We want to produce the image shown above as a screen capture or below as the schematic of this circuit. R1 V1 25

More information

Select the technology library: NCSU_TechLib_ami06, then press OK.

Select the technology library: NCSU_TechLib_ami06, then press OK. ECE 126 Inverter Tutorial: Schematic & Symbol Creation Created for GWU by Anis Nurashikin Nordin & Thomas Farmer Tutorial adapted from: http://www.ee.ttu.edu/ee/cadence/commondirectory/final%20tutorials/digitalcircuitsimulationusingvirtuoso.doc

More information

EE115C Digital Electronic Circuits. Tutorial 4: Schematic-driven Layout (Virtuoso XL)

EE115C Digital Electronic Circuits. Tutorial 4: Schematic-driven Layout (Virtuoso XL) EE115C Digital Electronic Circuits Tutorial 4: Schematic-driven Layout (Virtuoso XL) This tutorial will demonstrate schematic-driven layout on the example of a 2-input NAND gate. Simple Layout (that won

More information

There are three windows that are opened. The screen that you will probably spend the most time in is the SCHEMATIC page.

There are three windows that are opened. The screen that you will probably spend the most time in is the SCHEMATIC page. Pspice Tutorial Create a new project and select Analog or Mixed A/D. Choose an appropriate project name and a path. A new window pop up with the Pspice project type, select Create a blank project and click

More information

PSpice Tutorial. Physics 160 Spring 2006

PSpice Tutorial. Physics 160 Spring 2006 PSpice Tutorial This is a tutorial designed to guide you through the simulation assignment included in the first homework set. You may either use the program as installed in the lab, or you may install

More information

EE 330 Spring 2018 Lab 1: Cadence Custom IC design tools Setup, Schematic capture and simulation

EE 330 Spring 2018 Lab 1: Cadence Custom IC design tools Setup, Schematic capture and simulation EE 330 Spring 2018 Lab 1: Cadence Custom IC design tools Setup, Schematic capture and simulation Table of Contents Objective... 2 1. Setup... 2 Set Bash Shell for the account... 2 2. Starting Cadence Custom

More information

Cadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics

Cadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics Cadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics Introduction This tutorial describes how to generate a mask layout in the Cadence Virtuoso Layout Editor. Use of DIVA

More information

Simulation examples Chapter overview

Simulation examples Chapter overview Simulation examples 2 Chapter overview The examples in this chapter provide an introduction to the methods and tools for creating circuit designs, running simulations, and analyzing simulation results.

More information

EE434 ASIC & Digital Systems. From Layout to SPICE Simulation (Virtuoso, Calibre, HSpice) Spring 2017 Dae Hyun Kim

EE434 ASIC & Digital Systems. From Layout to SPICE Simulation (Virtuoso, Calibre, HSpice) Spring 2017 Dae Hyun Kim EE434 ASIC & Digital Systems From Layout to SPICE Simulation (Virtuoso, Calibre, HSpice) Spring 2017 Dae Hyun Kim daehyun@eecs.wsu.edu 1 Preparation for Lab2 Download the following file into your working

More information

LTSPICE MANUAL. For Teaching Module EE4415 ZHENG HAUN QUN. December 2016

LTSPICE MANUAL. For Teaching Module EE4415 ZHENG HAUN QUN. December 2016 LTSPICE MANUAL For Teaching Module EE4415 ZHENG HAUN QUN December 2016 DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINNERING NATIONAL UNIVERSITY OF SINGAPORE Contents 1. Introduction... 2 1.1 Installation...

More information

ECE471/571 Energy Ecient VLSI Design

ECE471/571 Energy Ecient VLSI Design ECE471/571 Energy Ecient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30pm on Friday, January 30 th 2015 Introduction This project will rst walk you through the setup for

More information

EE 330 Fall 2017 Lab 1: Cadence Custom IC design tools - Setup, Schematic capture and simulation

EE 330 Fall 2017 Lab 1: Cadence Custom IC design tools - Setup, Schematic capture and simulation EE 330 Fall 2017 Lab 1: Cadence Custom IC design tools - Setup, Schematic capture and simulation Table of Contents Objective... 2 1. Setup... 2 Set Bash Shell for the account... 2 2. Starting Cadence Custom

More information

Introduction to PSpice

Introduction to PSpice Introduction to PSpice Simulation Software 1 The Origins of SPICE In the 1960 s, simulation software begins CANCER Computer Analysis of Nonlinear Circuits, Excluding Radiation Developed at the University

More information

DOWNLOAD PDF CADENCE WAVEFORM CALCULATOR USER GUIDE

DOWNLOAD PDF CADENCE WAVEFORM CALCULATOR USER GUIDE Chapter 1 : CSE / Cadence Tutorial The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems

More information

EE 210 Lab Assignment #2: Intro to PSPICE

EE 210 Lab Assignment #2: Intro to PSPICE EE 210 Lab Assignment #2: Intro to PSPICE ITEMS REQUIRED None Non-formal Report due at the ASSIGNMENT beginning of the next lab no conclusion required Answers and results from all of the numbered, bolded

More information

Simulation with Verilog-XL

Simulation with Verilog-XL Simulation with Verilog-XL Adapted from Princeton Cadence Page (http://www.ee.princeton.edu/~cadence/usr/verilog.html) Until now, we have been using the Analog Environment to do simulations. This simulator

More information

EE 330 Laboratory 3 Layout, DRC, and LVS Fall 2015

EE 330 Laboratory 3 Layout, DRC, and LVS Fall 2015 EE 330 Laboratory 3 Layout, DRC, and LVS Fall 2015 Contents Objective:... 2 Part 1 Creating a layout... 2 1.1 Run DRC Early and Often... 2 1.2 Create N active and connect the transistors... 3 1.3 Vias...

More information

1. INTRODUCTION. PSpice with OrCAD Capture (release 16.6 edition)

1. INTRODUCTION. PSpice with OrCAD Capture (release 16.6 edition) 1. INTRODUCTION SPICE (Simulation Program for Integrated Circuits Emphasis.) is a powerful general purpose analog and mixed-mode circuit simulator that is used to verify circuit designs and to predict

More information

Tutorial 3: Using the Waveform Viewer Introduces the basics of using the waveform viewer. Read Tutorial SIMPLIS Tutorials SIMPLIS provide a range of t

Tutorial 3: Using the Waveform Viewer Introduces the basics of using the waveform viewer. Read Tutorial SIMPLIS Tutorials SIMPLIS provide a range of t Tutorials Introductory Tutorials These tutorials are designed to give new users a basic understanding of how to use SIMetrix and SIMetrix/SIMPLIS. Tutorial 1: Getting Started Guides you through getting

More information

TUTORIAL SESSION Technical Group Hoda Najafi & Sunita Bhide

TUTORIAL SESSION Technical Group Hoda Najafi & Sunita Bhide TUTORIAL SESSION 2014 Technical Group Hoda Najafi & Sunita Bhide SETUP PROCEDURE Start the Altium Designer Software. (Figure 1) Ensure that the Files and Projects tabs are located somewhere on the screen.

More information

PSpice with Orcad 10

PSpice with Orcad 10 PSpice with Orcad 10 1. Creating Circuits Using PSpice Tutorial 2. AC Analysis 3. Step Response 4. Dependent Sources 5. Variable Phase VSin Source Page 1 of 29 Creating Circuits using PSpice Start Orcad

More information

Getting started. Starting Capture. To start Capture. This chapter describes how to start OrCAD Capture.

Getting started. Starting Capture. To start Capture. This chapter describes how to start OrCAD Capture. Getting started 1 This chapter describes how to start OrCAD Capture. Starting Capture The OrCAD Release 9 installation process puts Capture in the \PROGRAM FILES\ORCAD\CAPTURE folder, and adds Pspice Student

More information

UNIVERSITY OF WATERLOO

UNIVERSITY OF WATERLOO UNIVERSITY OF WATERLOO UW ASIC DESIGN TEAM: Cadence Tutorial Description: Part I: Layout & DRC of a CMOS inverter. Part II: Extraction & LVS of a CMOS inverter. Part III: Post-Layout Simulation. The Cadence

More information

GETTING STARTED WITH ADS

GETTING STARTED WITH ADS ADS Startup Tutorial v2 Page 1 of 17 GETTING STARTED WITH ADS Advanced Design System (ADS) from Agilent Technologies is an extremely powerful design tool for many aspects of electrical and computer engineering

More information

1. Working with PSpice:

1. Working with PSpice: Applied Electronics, Southwest Texas State University, 1, 13 1. Working with PSpice: PSpice is a circuit simulator. It uses the Kirchhoff s laws and the iv-relation of the used components to calculate

More information

Lesson 14: Property Editor

Lesson 14: Property Editor Lesson 14: Property Editor Lesson Objectives After completing this lesson, you will be able to: Work with Property Filters in the Property Editor Add part and net properties using the Property Editor Using

More information

Start ADS and Create an Empty Project

Start ADS and Create an Empty Project Start ADS and Create an Empty Project Look for a desktop icon or start menu item entitled Advanced Design System 2011 ADS will start up and you will see ultimately: ADS Session 1 click for new project

More information

DataPro Quick Start Guide

DataPro Quick Start Guide DataPro Quick Start Guide Introduction The DataPro application provides the user with the ability to download and analyze data acquired using the ULTRA-LITE PRO range of Auto Meter products. Please see

More information

Schematics. Prof. Dr. P. Fischer. Lehrstuhl für Schaltungstechnik und Simulation Uni Heidelberg

Schematics. Prof. Dr. P. Fischer. Lehrstuhl für Schaltungstechnik und Simulation Uni Heidelberg Schematics Prof. Dr. P. Fischer Lehrstuhl für Schaltungstechnik und Simulation Uni Heidelberg VLSI Design: Schematics P. Fischer, ZITI, Uni Heidelberg Page1 What are Symbols? Very often, a circuit (schematic)

More information

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #1, Full Custom VLSI (inverter layout)

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #1, Full Custom VLSI (inverter layout) CPE/EE 427, CPE 527, VLSI Design I: Tutorial #1, Full Custom VLSI (inverter layout) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville Adapted from Virginia Tech, Dept.

More information

EE 330 Laboratory 3 Layout, DRC, and LVS

EE 330 Laboratory 3 Layout, DRC, and LVS EE 330 Laboratory 3 Layout, DRC, and LVS Spring 2018 Contents Objective:... 2 Part 1 creating a layout... 2 1.1 Run DRC... 2 1.2 Stick Diagram to Physical Layer... 3 1.3 Bulk Connections... 3 1.4 Pins...

More information

More information can be found in the Cadence manuals Virtuoso Layout Editor User Guide and Cadence Hierarchy Editor User Guide.

More information can be found in the Cadence manuals Virtuoso Layout Editor User Guide and Cadence Hierarchy Editor User Guide. Chapter 6 Building with Layout This chapter consists of two parts. The first describes the generation of layout views and the second deals with the various tools used for verifying the layout, both physical

More information

EET2141 Project 2: Binary Adder Using Xilinx 7.1i Due Friday April 25

EET2141 Project 2: Binary Adder Using Xilinx 7.1i Due Friday April 25 EET2141 Project 2: Binary Adder Using Xilinx 7.1i Due Friday April 25 Introduction This Xilinx project introduces the characteristics of the ripple carry adder. From the last project, you learned that

More information

Cadence Tutorial D: Using Design Variables and Parametric Analysis Document Contents Introduction Using Design Variables Apply Apply

Cadence Tutorial D: Using Design Variables and Parametric Analysis Document Contents Introduction Using Design Variables Apply Apply Cadence Tutorial D: Using Design Variables and Parametric Analysis Created for the MSU VLSI program by Casey Wallace Last Updated by: Patrick O Hara SS15 Document Contents Introduction Using Design Variables

More information

EXPERIMENT 1 INTRODUCTION TO MEMS Pro v5.1: DESIGNING a PIEZO- RESISTIVE PRESSURE SENSOR

EXPERIMENT 1 INTRODUCTION TO MEMS Pro v5.1: DESIGNING a PIEZO- RESISTIVE PRESSURE SENSOR EXPERIMENT 1 INTRODUCTION TO MEMS Pro v5.1: DESIGNING a PIEZO- RESISTIVE PRESSURE SENSOR 1. OBJECTIVE: 1.1 To learn and get familiar with the MEMS Pro environment and tools 1.2 To learn the basis of process

More information

EE 471: Transport Phenomena in Solid State Devices

EE 471: Transport Phenomena in Solid State Devices EE 471: Transport Phenomena in Solid State Devices HW7 Due: 4/17/18 For this homework, you will download a free PC version of the industry standard SPICE circuit simulator called LTspice, provided by Linear

More information

ELEC 301 Lab 2: Cadence Basic

ELEC 301 Lab 2: Cadence Basic ELEC 301 Lab 2: Cadence Basic Revision: 2.1 Last modified: Aug. 98 Introduction In this class, you will be introduced to the Cadence suit of IC design tools. These tools are a very powerful set of tools.

More information

Copyright 2008 Linear Technology. All rights reserved. Getting Started

Copyright 2008 Linear Technology. All rights reserved. Getting Started Copyright. All rights reserved. Getting Started Copyright. All rights reserved. Draft a Design Using the Schematic Editor 14 Start with a New Schematic New Schematic Left click on the New Schematic symbol

More information

FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT

FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT DIC1: Schematic Design Entry, Simulation & Verification DIC2: Schematic Driven Layout Drawing (SDL) Design Rule Check (DRC)

More information

Cadence Virtuoso Layout Connectivity Mark- Net Tutorial

Cadence Virtuoso Layout Connectivity Mark- Net Tutorial Cadence Virtuoso Layout Connectivity Mark- Net Tutorial Digital VLSI Chip Design CAD manual addendum When you re drawing layout, especially of a complex cell, it s sometimes hard to see exactly what your

More information

- create new schematic to the new project, PCB design begins with a schematic diagram, which present how components are connected

- create new schematic to the new project, PCB design begins with a schematic diagram, which present how components are connected Eagle 8.x tutorial - create a new project, Eagle designs are organized as projects - create new schematic to the new project, PCB design begins with a schematic diagram, which present how components are

More information

CMOS Design Lab Manual

CMOS Design Lab Manual CMOS Design Lab Manual Developed By University Program Team CoreEl Technologies (I) Pvt. Ltd. 1 Objective Objective of this lab is to learn the Mentor Graphics HEP2 tools as well learn the flow of the

More information

Laboratory 6. - Using Encounter for Automatic Place and Route. By Mulong Li, 2013

Laboratory 6. - Using Encounter for Automatic Place and Route. By Mulong Li, 2013 CME 342 (VLSI Circuit Design) Laboratory 6 - Using Encounter for Automatic Place and Route By Mulong Li, 2013 Reference: Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Erik Brunvand Background

More information

Getting Started with Orcad Lite, Release 9.2

Getting Started with Orcad Lite, Release 9.2 Getting Started with Orcad Lite, Release 9.2 Professor Robert Hofinger Purdue University - Columbus You start a new project (program) by going to the File menu in the upper left corner, then New, and then

More information