EE115C Digital Electronic Circuits. Tutorial 2: Hierarchical Schematic and Simulation

Transcription

1 EE115C Digital Electronic Circuits Tutorial 2: Hierarchical Schematic and Simulation The objectives are to become familiar with Virtuoso schematic editor, learn how to create the symbol view of basic primitives, compose symbols hierarchically, and verify the design through simulation. In order to achieve these objectives, CMOS inverter in a fanout-of-four (FO4) and ring oscillator configurations is considered. These configurations are widely used as formalism for technology characterization: to estimate the speed of technology in terms of gate delay. The numbers obtained here will thus become essential tool in estimating delays of complex circuits. Startup Cadence tool and open Library Manager window. If you don t remember all the steps, review Starting up Cadence and Entering Design Schematic from Tutorials 1.1 and 1.2. Entering Design Schematic We are going to create the inverter sized for unit drive strength (typically indicated as INVX1). In the Library Manager, click to select ee115c library and then click File > New > Cell view to create schematic view for the new cell. Type INVX1 in the Cell Name field as illustrated. Click OK. After you click OK, Virtouso Schematic Editing window will pop up. Note: If you are asked to check the license for Virtuoso_Schematic_Editor_XL, choose Yes or Always. (See Below). Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 1

2 Instantiate NMOS and PMOS transistors as described in Tutorial 1.2, Entering Design Schematic. The unit (INVX1) inverter has Wp/Wn ratio of around 2, where Wn is 2x the minimum width. In our technology, Wmin = 120nm, so the unit inverter is Wp/Wn = 480nm/240nm. Your schematic editor window should look like this: Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 2

3 Next, we are going to add input and output pins, which are needed to describe connectivity information for the symbol view. To instantiate a pin, type p in the schematic editor and following dialog will show up: Type A VDD GND under Pin Names to define input pins, click Hide and place the pins in the schematic (in the order you specified). Follow the same procedure to place output pin Z. Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 3

4 Wire up the schematic (reminder: press w to enter wiring mode / Esc to exit). The final schematic should look like this (type f to fit the drawing to page): Click Check and Save button ( ) or type Shift+X to check and save the design. Watch the CDS.log window for any potential warnings. In the log window, you should see following messages: Schematic check completed with no errors. ee115c INVX1 schematic saved. Creating Symbol View The symbol view can be created directly from the schematic view of the cell. In Virtuoso schematic editor, click on the Create menu and choose Cellview > From Cellview You should see the following window pop-up. Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 4

5 Choose schematic in From View Name field, and make sure symbol is typed in the To View Name. Also make sure your Library Name and Cell Name correspond to your current cell. (They should already) After you click OK, the following window will appear indicating that input pins A, GND and VDD will be placed on the left and that output pin Z will be placed on the right: Click OK and the default box-shaped symbol view is created as shown below: Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 5

6 Next, we are going to modify the shape of this symbol view in order to represent the inverter with the familiar shape (triangle + bubble) used by digital designers. In the Virtuoso Symbol Editing window, go to Create menu and select Shape > Line to add lines (you can also find a short-cut to this feature along the menu bar. For example to create a line you can use the button in the menu bar), or Shape > Circle to create the bubble at the output of the inverter. You can also drag the pins around to position VDD and GND to top and bottom, respectively, and move labels and lines around to modify the symbol. Your final symbol view should look something like this: Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 6

7 Edit properties (reminder: select the object and press q ) of the [@partname] label and specify justification to centerleft as shown in the dialog box below. This will ensure that the INVX1 label is nicely aligned within the shape (as you are going to see in the next section). When you save the final version, make sure it is bug-free. As in the sqchematic entry, check the CDS.log window. It should display following message for the correctly designed symbol view: Cross View Check completed with no errors. ee115c INVX1 symbol saved. Now we can instantiate this symbol to build other circuits such as ring oscillator and fanout-offour (FO4) test circuit. Hierarchical Design: Ring Oscillator By now you are already an expert in creating new cells, so let s make another one. Go to the Library Manager window and add Ring_OSC cell to your ee115c library. Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 7

8 We are going to create a 15-stage ring oscillator in order to measure the delay of the 1x inverter. In the Virtuoso Schematic Editor window, now instantiate INVX1 cell (symbol view) from your ee115c library. Furthermore, we are going to place the 15 inverters in three rows, 5 in each row, to make the schematic easily readable. To place the first row of cells, in the Array field specify 5 columns (meaning you want to place 5 instances in a column-like fashion). Click Hide (or press Enter) and place the first instance. Then move the mouse pointer over to the right to define the location for other instances. You should see yellow fly lines as follows: Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 8

9 The first row of instances should look something like this: For easy routing of global signals VDD and GND, we are going to flip and rotate the second row of cells. In the Add Instance menu, specify again 5 columns, but also click once on Sideways and Upside Down buttons. Finally, create the third row in the same way the first row was created and place the third row below the second row. The final placement should look like this: Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 9

10 Instantiate vdd and gnd cells from analoglib and wire up the schematic (reminder: press w to enter wiring mode / Esc to exit). Also label one of the points in the ring, this point will be used as a test point to measure the delay. You can either execute Create > Wire Name from the drop down menu or press l (small L ) to add the label. Add label named TP and place it at the output of the last inverter in the first row. The final schematic should look like this: Ring Oscillator Delay Simulation Invoke simulation environment by choosing Launch > ADE L from the Virtuoso schematic editor window. (review Spectre Simulation section of Tutorial 1.2 if needed). In addition to the setup in Tutorial 1.2, we also need to set up global source such as vdd!. In the Analog Design Environment, Click Setup > Stimuli... Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 10

11 Click on Global Sources Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 11

12 The following dialog window will pop up. Make sure vdd! is hightlighted. Click on Enabled. Set function to dc. Make sure Type is Voltage. Enter 1.0 in DC voltage. Then Click the Change botton. Click OK. Set up the models, select transient analysis with duration of 1.5ns and moderate accuracy. Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 12

13 Select TP as the output to be plotted. At this point you can simulate your design by netlisting and running the simulation. (by pressing or using Simulation > Netlist and Run). Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 13

14 You should get the following graph as the simulation result. Now, let s calculate the oscillation period. Click on calculator button as highlighted above. In the Calculator window (shown below), select vt under Selection choices. Then choose delay from the Function Panel. At this point you can select your signal (in this case TP by clicking on it from your graph (Virtuoso Visualization window), or your schematic (Schematic Editor window). Go back to the Calculator window. Under delay functions, choose buffer for Signal1 and Signal2 (this will input whatever is in the buffer in these fields; in this case our buffer is VT( /TP ) ). Both Signal1 and Signal2 fields should read VT( /TP ). Set Threshold Value 1 to 0.5 (VDD/2=0.5V) and Edge Number 1 to rising (falling is also OK). Set the remaining parameters so that your final calculator setup looks like the following: Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 14

15 Click OK, the following window will appear. Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 15

16 Click Eval button (as shown above) to evaluate the delay expression highlighted above. The expression evaluates to 400.4ps as shown below. This is the period of oscillation. In terms of gate delay, period T has a total of 15 low-to-high and 15 high-to-low transitions. Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 16

17 T = N (tplh + tphl), where N is the number of stages (N=15) Gate delay = tp = (tplh+tphl)/2 Therefore: tp = T/2N For N = 15: tp = 400.4/30 = 13.35ps This is the delay of an inverter which output is loaded with an identically sized inverter. This is also called the delay of a fanout-of-one (FO1) inverter. In circuits optimized for speed, typical fanout is about 4, so designers often times use fanout-of-four (FO4) inverter as normalization unit to compare the quality of their designs. It is therefore of interest to evaluate FO4 delay for our technology. Note: it is a good idea to save the simulation settings in a state file. (reference: check Spectre Simulation section of Tutorial 1.2 on how to do this) Save the state in file: state_ring_osc. Hierarchical Design: FO4 Inverter The FO4 test circuit example will use two levels of hierarchy: the circuit will be composed of three stages, each stage being composed of inverters and capacitors. To save time and also learn how to port over cells from other libraries, we are going to copy over FO4_inv_stage cell from ee115c public repository. Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 17

18 Position yourself in the following directory: <disk_path><user_name>/ee115c/ee115c (Example: /w/fac.01/ee/sinabk/ee115c/ee115c) (Note: in this folder you should have a directory for each of your cells in ee115c library. For example you should have directories named INVX1 and Ring_OSC for the cells you created earlier in this tutorial. You can check the content of any location by typing ls ) Create new folder for the new cell: > mkdir FO4_inv_stage Copy cell FO4_inv_stage from the directory link below into your local folder: > cp -R /w/class.1/ee/ee115v/ee115vta/ee115c_tutorial/fo4_inv_stage/* FO4_inv_stage/ (there is a space after *) In the Library Manager window, select View > Refresh. The following window will pop up: Click None because you don t want to contaminate your library with what someone else did. We are going to be cautious and fix the missing links later. Click OK and you will see that cell FO4_inv_stage is now part of your ee115c library. Let s now try to open schematic view. The following window will pop up: This tells us that the INVX1 cell used to create FO4_inv_stage cell was referenced from some other library, in this case this library was named ee115c_lab1. Click Close. The following schematic will appear (notice broken links for the INVX1 instances). Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 18

19 We are now to substitute INVX1 cells with the INVX1 cell that we designed earlier in this tutorial. Edit properties for all the invalid objects and change Library Name from ee115c_lab1 (as shown below) to ee115c. Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 19

20 After some touch-up re-positioning and re-wiring of objects, the schematics should look like this: (you can also open symbol view to see how it looks or wait until a bit later - we are going to use it soon anyway) Details of this circuit are explained in class. Now, let s create FO4_inv cell to simulate the delay of FO4 inverter for this technology. (reference: Entering Design Schematic of this tutorial explains how to create a new cell) Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 20

21 Instantiate three instances of FO4_inv_stage cell (you are already a master of hierarchical design, so remember to use Array property when adding instances) and connect them together. Also instantiate the following cells from the analoglib and specify their properties as follows: vdd: connect to VDD pins. vddd: connect to VDDLD pins (supply voltage for the loading gates). gnd: connect to GND pins. cap: output load, set value to 100f. vpulse: (input pulse voltage source) Voltage 1 = 0, Voltage 2 = VD, Delay time = 100p, Rise time = 10p, Fall time = 10p, Pulse width = 200ps, Period = 400ps. After placing and wiring components, labeling in and out, your schematic should look like this: FO4 Inverter Delay Simulation Invoke simulation environment by choosing Launch > ADE L from the Virtuoso schematic editor window. (review Spectre Simulation in Tutorial 1.2 if needed). Perform following steps to setup the simulation environment: set up the models define VD as variable with initial value of 1.0 set the value of global sources stimuli vdd and vddd to VD choose transient analysis with duration of 1ns and moderate accuracy choose in and out as the outputs to be plotted By now you have learned to save the state. Save this state in file: ~/ee115c/cadence-labs/.artist_states/state_fo4_inv Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 21

22 Netlist and run, the simulation will produce the following waveforms (review Tutorial 1.2 for instructions about adding labels): You can also save this graph using the menu bar... Now, we can measure the low-to-high and high-to-low delay values. Remember (as discussed in class) that, by convention, the low-to-high or high-to-low delays are defined with respect to the output transition. Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 22

23 Low-to-high transition (i.e. in falling, out rising) Invoke Calculator (refer to the Ring_OSC example in this tutorial on how to do this) and specify parameters as shown below: Click OK button, the delay expression will appear: Evaluate this expression: Therefore: tplh = 37.1ps Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 23

24 High-to-low transition (i.e. in rising, out falling) In the Calculator window, we can simply type in the expression for tphl (refer to the tplh calculator expression and swap rising and falling ). By evaluating this expression we get: tphl = 30.5ps Therefore: t p = (t plh + t phl )/2 = 33.8ps = FO4 delay Schematic Editor: Zooming In There are several methods for zooming found in the View menu. One easy way to zoom to the exact region you want is by using the zoom hot key. Type z. This puts you in zoom mode. Note that the cursor has changed. Next hold down the left mouse button and "drag" out a box which surrounds the region you wish to zoom to. When you release the mouse the screen will zoom to where your box was. If you mess up don't panic. Remember, f will always zoom to fit. The hotkey ] can be used to zoom out by a factor of two. The hotkey [ can be used to zoom in by a factor of two. Cadence 6 Tutorial 2: Hierarchical Schematic and Simulation 24