Step 1 in transitioning to behavioral modeling. But here 1-to-1 with our gate level model.

Transcription

1 Project Step 4 Step 1 in transitioning to behavioral modeling. But here 1-to-1 with our gate level model. Copyright Joanne DeGroat, ECE, OSU 1

2 Project Step 4 This is the start of the transition to behavioral modeling. Behavioral High At the gate level you are near 1-to-1 with the hardware that is implemented At the behavioral level you have a physical interface and then the function between. Level of Abstraction RTL Gate Level Low Copyright Joanne DeGroat, ECE, OSU 2

3 VHDL view of the world The VHDL view is one that starts with the interface. How do you connect to the world. After this, you have the ARCHITECTURE which tell you what actions, responses, operations and transformations happen within the interface. Many designers first think about what the function is, and, after the function is described what the interface is. In the VHDL world you must first define the format, timing, frequency, etc. of how the data arrives and/or is produced. Copyright Joanne DeGroat, ECE, OSU

4 Thus Far Have described the ALU architecture structurally using 2 basic components described at the gate level. Very close to a 1- to-1 representation of the gates. Now will start a transition to a behavioral description where we raise the level of abstraction each time. Copyright Joanne DeGroat, ECE, OSU 4

5 Straight algorithmic representation of the slice Will use a process with a loop. Each iteration of the loop will move to the next most significant slice. On the first iteration will compute the P operation, then the K operation, do the logic function of the carry block, and then finally the results block. Naturally fits into a loop. Copyright Joanne DeGroat, ECE, OSU 5

6 Iteration For I in 0 to 7 loop begin -- do the p operation -- do the k operation -- carry out the carry chain unit operations -- do an r operation -- will have inputs of a(i),b(i),icin, p,k,r to each slice -- produce sum(i) and icout Leftmost Unit Inner Units Rightmost Unit Copyright Joanne DeGroat, ECE, OSU 6

7 Other details Project Assignment #4 DUE: Wednesday, January 1 st. In this assignment you will be writing an alternative architecture for the 8 bit ALU. DO NOT Change the Entity Description for the 8 bit ALU. The testbench is in file ~degroat/ee762_assign/pr_step4.vhdl. Note that this is the same testbench as in step. Also note that you do not have to recompile the ENTITY as the ENTITY for the 8-bit ALU does not change for this assignment. The alternative architecture that you are to write will use a PROCESS statement to describe the operation of the ALU on a slice-by-slice basis. You will write a process that will iteratively (use a loop) compute the Cout, and Result for each slice of the 8 bits of the ALU. The Cin will be the Cout of the previous iteration. Your architecture should have a different name than the architectures of step. It will contain one and only one process and no other concurrent statements. You should use a process with a sensitivity list. The sensitivity list will contain all signals that are on the right hand side of statements within the process. Copyright Joanne DeGroat, ECE, OSU 7

8 Other Info You are to use a loop to iterate the function of the ALU slice from the LSB to the MSB. In each iteration use the value of A i, B i, Cin i, Pctl i, Kctl i, and Rctl i to compute the Cout i and Result i for that slice. In an iteration use A(i), B(i), Pctl, Kctl, Rctl and Cin to the slice to do the same computations that are done in the bit slice architecture, passing the Cout of iteration i as the Cin input to iteration i+1. Use variables as appropriate and remember the difference in variables and signals. Compile and simulate this description. You will need to simulate for 17 us. You can do this by using the command >run 17 us.do files will be created for both the waveform and the listing. Don t forget to put your COMPONENT declaration, configuration and instantiation in the testbench architecture. The configuration needs to specify this new architecture Copyright Joanne DeGroat, ECE, OSU 8

9 The test file Slide PS1 and PS2 results Copyright Joanne DeGroat, ECE, OSU 9