Part 6: VHDL simulation. Introduction to Modeling and Verification of Digital Systems. Elaboration and simulation. Elaboration and simulation

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1 M Informatique / MOIG Introduction to Modeling and Verification of Digital ystems Part 6: VHDL simulation Laurence PIERRE 27/28 37 Elaboration and simulation Elaboration and simulation! Compilation consists in the analysis of the source description and the generation of an intermediate code, stored in a design library. Elaboration is the process of building a complete and consistant simulation model from the various compiled units.! Compilation, elaboration, simulation:! The elaboration of a design hierarchy creates a model as a collection of processes.! Finally, simulation of this model proceeds. It consists in the repetitive execution of the simulation cycle

2 imulation loop imulation loop! The simulation process starts with the initialization phase, in which:! After initialization, the simulation loop is as follows (very simplified view) :! The current simulation time T c is ns! while T c < TIME'HIGH do! ignals are initialized, resolved and assigned values - each explicit (and implicit) signal is updated! Processes are executed until their suspension on an explicit or implicit wait statement! Note. A resolved type includes in its definition a resolution function. A resolution function defines how the values of multiple sources of a given signal are to be resolved into a single value for that signal. 4 - for each process P, if P is currently sensitive to a signal and if an event has occurred on in this simulation cycle, then P resumes - T c is computed as the earliest of TIME'HIGH and the next time at which a signal has to be updated end while! Reminder: When a signal value is updated (i.e., a transaction is scheduled), if the new value is different from the previous one, then an event is said to have occurred on the signal 4! Along the simulation, the projected output waveform of a signal is stored in a driver (each process that performs assignment(s) to a given signal implicitly contains a driver for that signal)! A driver is an ordered series of value/time pairs, called transactions! Example signal step: integer := ;... step <= after 5 ns, 2 after ns, after 5 ns, after 2 ns;! The value is the new value for the signal, associated with the time when this value will (might) be assigned! The time is determined by the current simulation time added to the value of the time expression in the corresponding assignment 2 5 ns ns 5 ns 2 ns 42 43

3 ! In a signal assignment statement, the waveform can be preceded by the keyword transport or inertial (default mode). We mainly study the inertial mode assignment here.! The inertial mode signal assignment allows an accurate description of gate behaviour, by delaying signals and filtering glitches (small pulses). It enables to model a component that reacts only if an input value remains stable long enough. The transport mode is mainly used for transmission lines modeling.! The effect of the inertial mode signal assignment on the signal driver is:! all transactions previously scheduled to occur after the new transaction are removed! the new transaction is appended! for all existing transactions scheduled to occur before the new transaction:! all transactions up to the last one with a different value from the new transaction are deleted! the remaining transactions with the same value as the new transaction are kept 44 45! Example: let us come back to the example of slide 62 A B 2! Example: let us come back to the example of slide 62 A B 2! Remember that a natural dataflow description is architecture RTL of Example is signal s,s2: Bit; end RTL; 46! but we choose the following one (silly, but more illustrative here) architecture silly of Example is signal X,Y: Bit; process(a,b,x,y) X <= not A after 2 ns; Y <= X nand B after 5 ns; <= X and Y after 4 ns; end process; end silly; 48

4 ! Example: suppose that, at ns, we have reached the following configuration (X='', Y='', ='') A B and that, at 2 ns, A becomes '' X Y! Example: at 2 ns A becomes ''! The process is activated and the drivers are updated as follows! T c =22 ns, X is updated (X <- ''), and the drivers are updated as follows process(a,b,x,y) X <= not A after 2 ns; Y <= X nand B after 5 ns; <= X and Y after 4 ns; end process; A B! T c =24 ns, a transaction occurs on X, but it is not an event (the process does not resume)! 49 5! Example:! T c =26 ns, is updated ( <- ''), the current status of the drivers is process(a,b,x,y) X <= not A after 2 ns; Y <= X nand B after 5 ns; <= X and Y after 4 ns; end process;! Example:! T c =3 ns, is updated ( <- ''), the current status of the drivers is process(a,b,x,y) X <= not A after 2 ns; Y <= X nand B after 5 ns; <= X and Y after 4 ns; end process;! 32!! T c =27 ns, Y is updated (Y <- ''), A B! T c =32 ns, a transaction occurs on Y, but it is not an event (the process does not resume) and the drivers are updated as follows! The final status is! T c =29 ns, a transaction occurs on X, but it is not an event (the process does not resume) A B 5 52

5 Delta delay Delta delay! But: if the assignments have no after clause? In that case, the notion of delta delay is used! Delta delays can be thought of as infinitesimal delays. A delta delay simply models a progress to the next simulation cycle (without modification of the physical time)! everal delta delays can succeed each other, up to stabilization of the values of the signals! Example: full-adder and its testbench entity full_adder is port(x,y,cin : in Bit; um,cout : out Bit); end full_adder; architecture Dataflow_view of full_adder is signal : Bit; <= X xor Y; um <= xor Cin; Cout <= (X and Y) or ( and Cin); end Dataflow_view; Delta delay Delta delay entity test is end test;! Example: full-adder and its testbench architecture truct of test is component full_adder entity full_adder is port(x,y,cin: in Bit; um,cout: out Bit); end component; port(x,y,cin : in signal Bit; A,B,C,,C2 : Bit; um,cout : out for F: Bit); full_adder use end full_adder; entity work.full_adder(dataflow_view); F: full_adder port map(a,b,c,,c2); architecture Dataflow_view A <= '' of after full_adder ns; is signal : Bit; B <= '' after ns; C <= '' after ns; end truct; <= X xor Y; um <= xor Cin; Cout <= (X and Y) or ( and Cin); end Dataflow_view;! Example: full-adder and its testbench! T c = ns! T c = ns <= X xor Y; um <= xor Cin; Cout <= (X and Y) or ( and Cin); 55 56

6 Delta delay! Example: full-adder and its testbench! T c = ns + Δ Part 7: VHDL and temporal assertions! T c = ns + 2Δ <= X xor Y; um <= xor Cin; Cout <= (X and Y) or ( and Cin); Boolean assertions Boolean assertions! The assert statement enables to monitor Boolean assertions assert condition report message severity level;! When this statement is executed, the condition is evaluated. If it is false, the message is printed and an action is associated with the severity level (it depends on the simulator)! The severity level can be note, warning, error (default), or failure. In general, error makes the simulation stop! But this construct does not allow to check properties that need to be evaluated along several simulation steps! The assert statement enables to monitor Boolean assertions assert condition report message severity level;! When this statement is executed, the condition is evaluated. If it is false, the message is printed and an action is associated with the severity level (it depends on the simulator)! The severity level can be note, warning, error (default), or failure. In general, error makes the simulation stop! But this construct does not allow to check properties that need to be evaluated along several simulation steps Temporal assertions 59 6

7 Temporal assertions Temporal assertions! Example : elevator controller! Everytime the elevator is called at a floor number k, it will eventually reach that floor! Example 2: parking gate controller! Everytime the system is in state "output gate closed" and a valid ticket is inserted, then the gate should open within clock cycles! The PL language (Property pecification Language, IEEE standard 85) enables to formalize temporal assertions and to associate them with HDL descriptions, in particular VHDL descriptions! These PL assertions express temporal properties that involve the signals of the description (primary inputs/ outputs or internal signals)! PL is mainly inspired by the temporal logics LTL (Linear-time Temporal Logic) and CTL (Computation Tree Logic) 6 62 Temporal assertions PL (IEEE std 85) CTL! A glance at LTL (Linear-time Temporal Logic) and CTL (Computation Tree Logic) LTL 63! The FL (Foundation Language) class of PL formulas proposes temporal operators that are similar to the ones of LTL. PL also enables the specification of properties in terms of sequences of events, thanks to EREs (equential Extended Regular Expressions)! Note that PL properties can be verified! By formal analysis (model checking), see for instance MV (Cadence), or RuleBase (IBM)! By dynamic verification (during simulation), studied here. In that case, the properties must conform to the PL simple subset (conforms to the notion of monotonic advancement of time) 64

8 PL semantics PL semantics! The semantics of PL properties is defined with respect to execution traces i.e., words over the alphabet 2 P, where P is a set of atomic propositions! Examples of atomic propositions: "the elevator is called at a floor number k", "a valid ticket is inserted",! These execution traces are built by sampling the simulation on specific events! If all the PL assertions require a sampling on the clock rising edges, it is sufficient to declare, before the assertions: default clock is (clk'event and clk='');! The satisfaction of a formula ϕ on a trace v, denoted as v = ϕ, is defined as follows, for Boolean expressions and for the basic temporal operators next! and until!! v = b v = or b holds on v! v = ϕ ψ v = ϕ and v = ψ! v = next! ϕ v > and v.. = ϕ! v = ϕ until! ψ k < v s.t. v k.. = ψ and j < k, v j.. = ϕ next! ϕ ϕ until! ψ PL semantics Back to the examples! ome derived operators! Eventually: eventually! ϕ = true until! ϕ! Always: always ϕ = eventually! ( ϕ) = (true until! ϕ)! Before: ϕ before! ψ = ψ until! (ϕ ψ)! Next_event: next_event!(b)(ϕ) = b until! (b ϕ)! Next_a: next_a! [i..j] ϕ = next! [i] ϕ next! [j] ϕ! Next_e: next_e! [i..j] ϕ = next! [i] ϕ next! [j] ϕ! And some ERE operators! { s ; s2 } is the concatenation of two EREs s and s2! s[*] means, or several times s, and s[+] means or several times s! s -> ϕ is the (overlapping) suffix implication! Example : elevator controller! Everytime the elevator is called at a floor number k, it will eventually reach that floor always(req k -> eventually!(at k ))! Example 2: parking gate controller! Everytime the system is in state "output gate closed" and a valid ticket is inserted, then the gate should open within clock cycles always(state = gate_closed and valid_ticket -> next_e![..]open) 67 68

9 Example with a VHDL description Example with a VHDL description! Let us consider the VHDL description of an elevator controller, in a 3 levels building! 3 buttons inside the elevator (e, e2, e3) and 3 buttons outside (req, req2, req3)! ignal r k means a request at level k! ignal go k means go to level k ATa AT --- B AT2a AT2 Arrow labelling : go go2 go3 up B AT3a AT Elevator leaving level 3 Elevator moving between levels 2 and 3 Elevator stopped at level 3 69! VHDL description entity Elevator is port(e,e2,e3,req,req2,req3,ck:in Bit); end Elevator; architecture Behav_RTL of Elevator is type TATE is (ATa,AT,B2,AT2,AT2a,B23,AT3,AT3a); signal TATE: TATE; signal GO, GO2, GO3, R, R2, R3, UP : Bit ; process wait until Ck'event and Ck = ''; case TATE is when ATa => if (GO='') then TATE <= AT; elsif ((GO2 or GO3) = '') then TATE <= B2; end if; when AT => TATE <= ATa; when B2 => if (GO = '') and (UP='') then TATE <= AT; elsif (GO2 = '') and (UP='') then TATE <= AT2; elsif (GO3 = '') and (UP='') then TATE <= B23; end if;... end case; 7 Example with a VHDL description Example with a ERE! VHDL description if (TATE /= AT) and ((Req or E) = '') then R <= ''; elsif (TATE = AT) then R <= ''; end if; if (TATE /= AT2) and ((Req2 or E2) = '') then R2 <= ''; elsif (TATE = AT2) then R2 <= ''; end if; if (TATE /= AT3) and ((Req3 or E3) = '') then R3 <= ''; elsif (TATE = AT3) then R3 <= ''; end if; case TATE is when AT => GO <= ''; when ATa => UP <= ''; if (R='') then GO <= ''; end if; if (R2='') then GO2 <= ''; end if; if (R3='') then GO3 <= ''; end if ; when AT2 => GO2 <= '';... end case; end process; end Behav_RTL; always(r -> eventually!(state = at)) always(r2 -> eventually!(state = at2)) always(r3 -> eventually!(state = at3))! HDLC (High-Level Data Link Control) network interface! When the abort sequence is recognized (seven consecutive ones), the AbortFound signal must be set before the arrival of a new frame (tartofframe) default clock is (RxDataEnOut'event and RxDataEnOut=''); property HDLC_ : always({ not RxData ; RxData[*7] } -> AbortFound before! tartofframe); HDLC_..! 7 72

10 What should I remember 73