Direct Mapped Cache Hardware. Direct Mapped Cache. Direct Mapped Cache Performance. Direct Mapped Cache Performance. Miss Rate = 3/15 = 20%

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1 Direct Mapped Cache Direct Mapped Cache Hardware mem[xff...fc] mem[xff...f8] mem[xff...f4] mem[xff...f] mem[xff...ec] mem[xff...e8] mem[xff...e4] mem[xff...e] 27 8-entry x (+27+)-bit SRAM mem[x...24] mem[x..2] mem[x..c] mem[x...8] mem[x...4] mem[x...] mem[x...c] mem[x...8] mem[x...4] mem[x...] 2 Word Main 2 Word Cache Set Number 7 () 6 () 5 () 4 () () 2 () () () Copyright 27 Elsevier 8-<2> 27 Copyright 27 Elsevier 8-<2> Direct Mapped Cache Performance Direct Mapped Cache Performance... addi $t, $, 5 loop: beq $t, $, done lw $t, x4($) lw $t2, xc($) lw $t, x8($) addi $t, $t, - Miss Rate /5 2% Set 7 () Set 6 () Set 5 () Set 4 () Set () Set 2 () Set () Set ()... addi $t, $, 5 loop: beq $t, $, done lw $t, x4($) lw $t2, xc($) lw $t, x8($) addi $t, $t, -... mem[x...c]... mem[x...8]... mem[x...4] Miss Rate /5 2% Set 7 () Set 6 () Set 5 () Set 4 () Set () Set 2 () Set () Set () Copyright 27 Elsevier 8-<22> Copyright 27 Elsevier 8-<2>

2 Direct Mapped Cache: Conflict Direct Mapped Cache: Conflict... addi $t, $, 5 loop: beq $t, $, done lw $t, x4($) lw $t2, x24($) addi $t, $t, - Set 7 () Set 6 () Set 5 () Set 4 () Set () Set 2 () Set () Set ()... addi $t, $, 5 loop: beq $t, $, done lw $t, x4($) lw $t2, x24($) addi $t, $t, -... mem[x...4] Miss Rate % Set 7 () Set 6 () Set 5 () Set 4 () Set () Set 2 () Set () Set () Copyright 27 Elsevier 8-<24> Copyright 27 Elsevier 8-<25> N-Way Set Associative Cache N-Way Set Associative Performance Way Way addi $t, $, 5 loop: beq $t, $, done lw $t, x4($) lw $t2, x24($) addi $t, $t, - Way Way Copyright 27 Elsevier 8-<26> Copyright 27 Elsevier 8-<27> 2

3 N-way Set Associative Performance Fully Associative Cache addi $t, $, 5 loop: beq $t, $, done lw $t, x4($) lw $t2, x24($) addi $t, $t, - Way Way Miss Rate 2/ 2%... mem[x...24]... mem[x...4] Set Set 2 Set Set Copyright 27 Elsevier 8-<28> Copyright 27 Elsevier 8-<29> Spatial Locality? Cache with Larger Block Size Increase block size: Block size, b 4 words C 8 words Direct mapped ( block per set) Number of blocks, B C/b 8/4 2 Block Offset Set Set Block Offset Set Set Copyright 27 Elsevier 8-<> Copyright 27 Elsevier 8-<>

4 Direct Mapped Cache Performance Direct Mapped Cache Performance loop: addi $t, $, 5 beq $t, $, done lw $t, x4($) lw $t2, xc($) lw $t, x8($) addi $t, $t, - Block Offset loop: addi $t, $, 5 beq $t, $, done lw $t, x4($) lw $t2, xc($) lw $t, x8($) addi $t, $t, - Block Offset mem[x...c] 27 Miss Rate /5 6.67% mem[x...8] mem[x...4] mem[x...] Set Set Copyright 27 Elsevier 8-<> Copyright 27 Elsevier 8-<> Cache Organization Recap Capacity: C (in bytes) Block size: b (in bytes) Number of blocks in a set: N LRU Replacement # MIPS assembly lw $t, x4($) lw $t, x24($) lw $t2, x54($) Organization Direct Mapped Number of Ways (N) Number of Sets (S) B (a) U Set Number () 2 () () () N-Way Set Associative Fully Associative < N < B B B / N (b) U Set Number () 2 () () () Copyright 27 Elsevier 8-<4> Copyright 27 Elsevier 8-<6> 4

5 LRU Replacement Intel Pentium III Die # MIPS assembly lw $t, x4($) lw $t, x24($) lw $t2, x54($) Way Way (a) U... mem[x...24]... mem[x...4] Way Way Set () Set 2 () Set () Set () (b) U... mem[x...24]... mem[x...54] Set () Set 2 () Set () Set () Copyright 27 Elsevier 8-<7> Copyright 27 Elsevier 8-<9> The Hierarchy The Hard Disk Technology cost / GB Access time Speed Cache Main SRAM ~ $, ~ ns DRAM ~ $ ~ ns Magnetic Disks Capacity Hard Disk ~ $ ~,, ns Read/Write Head : DRAM : Hard disk Slow, Large, Cheap Copyright 27 Elsevier 8-<4> Takes milliseconds to seek correct location on disk Copyright 27 Elsevier 8-<4> 5

and es Translation Most accesses hit in physical memory, but benefit of large capacity of virtual memory Copyright 27 Elsevier 8-<44> Copyright 27 Elsevier 8-<46> Example

6 and es Translation Most accesses hit in physical memory, but benefit of large capacity of virtual memory Copyright 27 Elsevier 8-<44> Copyright 27 Elsevier 8-<46> Example 9-bit virtual page numbers 5-bit physical page numbers Example What is the physical address of virtual address x2? Copyright 27 Elsevier 8-<48> Copyright 27 Elsevier 8-<49> 6

7 Example Example What is the physical address of virtual address x2? PN x2 PN x2 maps to PPN x7fff The lower 2 bits (page offset) is the same for virtual and physical addresses (x) address x7fff Copyright 27 Elsevier 8-<5> PN is index into page table Page Number x2 9 Page Offset Page Number x x7ffe x x7fff x7fff Copyright 27 Elsevier 8-<52> Translation Example Copyright 27 Elsevier 8-<5> What is the physical address of virtual address x5f2? Page Number x x7ffe x x7fff Copyright 27 Elsevier 8-<54> 5 7

8 Example Example 2 What is the physical address of virtual address x5f2? PN 5 Entry 5 in page table indicates PN 5 is in physical page address is xf2 Page Number x2 9 Page Offset Page Number x x7ffe x x7fff Copyright 27 Elsevier 8-<55> 2 x7fff 5 2 What is the physical address of virtual address x7e? Page Number x x7ffe x x7fff 5 Copyright 27 Elsevier 8-<56> Example 2 Example Two-Entry TLB What is the physical address of virtual address x7e? PN 7 Entry 7 in page table is invalid, so the page is not in physical memory The virtual page must be swapped into physical memory from disk Page Number x7 Page Offset E Page Number x x7ffe x x7fff Copyright 27 Elsevier 8-<57> 9 5 Page Number x2 9 Page Offset Page Number Page Number Page Number Page Number x7fffd x x2 x7fff TLB 2 Entry Copyright 27 Elsevier 8-<6> 5 x7fff Entry 2 8

9 Protection Multiple programs (processes) run at once Each process has its own page table Each process can use entire virtual address space without worrying about where other programs are A process can only access physical pages mapped in its page table can t overwrite memory from another process Summary memory increases capacity A subset of virtual pages are located in physical memory A page table maps virtual pages to physical pages this is called address translation A TLB speeds up address translation Copyright 27 Elsevier 8-<62> Copyright 27 Elsevier 8-<6> 9

Chapter 8 :: Topics. Chapter 8 :: Memory Systems. Introduction Memory System Performance Analysis Caches Virtual Memory Memory-Mapped I/O Summary

Chapter 8 :: Topics. Chapter 8 :: Memory Systems. Introduction Memory System Performance Analysis Caches Virtual Memory Memory-Mapped I/O Summary Chapter 8 :: Systems Chapter 8 :: Topics Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Introduction System Performance Analysis Caches Virtual -Mapped I/O Summary Copyright