Chapter 8 Virtual Memory

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1 Chapter 8 Virtual Memory Digital Design and Computer Architecture: ARM Edi*on Sarah L. Harris and David Money Harris Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <1>

2 Chapter 8 :: Topics Introduc*on Memory System Performance Analysis Caches Virtual Memory Memory-Mapped I/O Summary Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <2>

3 Virtual Memory Gives the illusion of bigger memory Main memory (DRAM) acts as cache for hard disk Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <3>

4 Memory Hierarchy Technology Price / GB Access Time (ns) Bandwidth (GB/s) Cache SRAM $1, Speed Main Memory DRAM $ SSD $1 1,.5 Virtual Memory HDD $.1 1,,.1 Capacity Physical Memory: DRAM (Main Memory) Virtual Memory: Hard drive Slow, Large, Cheap Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <4>

5 Virtual Memory Concept Basic idea: Allow a large virtual address space that can be mapped onto physical memory, as needed Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <6>

6 Virtual Memory Virtual addresses Programs use virtual addresses CPU translates virtual addresses into physical addresses (DRAM addresses) Subset of virtual address data in DRAM Data not in DRAM fetched from hard drive (if exists) Memory Protec*on Each program has own virtual to physical mapping Two programs can use same virtual address for different data One program (or virus) can t corrupt memory used by another Programs can use the same program memory organiza>on Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <7>

7 Virtual Memory Defini>ons Page size: amount of memory transferred from hard disk to DRAM at once Address transla*on: determining physical address from virtual address Page table: lookup table used to translate virtual addresses to physical addresses Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <8>

8 Virtual & Physical Addresses Most accesses hit in physical memory But programs have the large capacity of virtual memory Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <1>

9 Address Transla>on Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <11>

10 Virtual Memory Example System: Virtual memory size: 2 GB = 2 31 bytes Physical memory size: 128 MB = 2 27 bytes Page size: 4 KB = 2 12 bytes Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <12>

11 Virtual Memory Example System: Virtual memory size: 2 GB = 2 31 bytes Physical memory size: 128 MB = 2 27 bytes Page size: 4 KB = 2 12 bytes Organiza*on: Virtual address: 31 bits Physical address: 27 bits Page offset: 12 bits # Virtual pages = 2 31 /2 12 = 2 19 (VPN = 19 bits) # Physical pages = 2 27 /2 12 = 2 15 (PPN = 15 bits) Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <13>

12 Virtual Memory Example 19-bit virtual page numbers 15-bit physical page numbers Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <14>

13 Virtual Memory Example What is the physical address of virtual address x247c? Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <15>

14 Virtual Memory Example What is the physical address of virtual address x247c? VPN = x2 VPN x2 maps to PPN x7fff 12-bit page offset: x47c Physical address = x7fff47c Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <16>

15 How to perform transla>on? Page table Entry for each virtual page Entry fields: Valid bit: 1 if page in physical memory Physical page number: where the page is located Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <17>

16 Page Table Example Virtual Address Virtual Page Number x2 19 Page Offset 47C 12 VPN is index into page table V 1 x 1 x7ffe 1 x1 1 x7fff Hit Physical Address Physical Page Number x7fff Page Table C Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <18>

17 Page Table Example 1 What is the physical address of virtual address x5f2? V Physical Page Number 1 x 1 x7ffe 1 x1 1 x7fff Page Table Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <19>

18 Page Table Example 1 What is the physical address of virtual address x5f2? Virtual Address VPN = 5 Entry 5 in page table VPN 5 => physical page 1 Physical address: x1f2 Virtual Page Number x5 19 Page Offset F2 12 V 1 x 1 x7ffe 1 x1 1 x7fff Hit Physical Address Physical Page Number Page Table x1 F2 Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <2>

19 Page Table Example 2 Virtual Address What is the physical address of virtual address x73e? Virtual Page Number x7 19 Page Offset 3E V Physical Page Number 1 x 1 x7ffe 1 x1 1 x7fff Page Table Hit 15 Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <21>

20 Page Table Example 2 What is the physical address of virtual address x73e? VPN = 7 Entry 7 is invalid Virtual Address Virtual page must be paged into physical memory from disk Virtual Page Number x7 19 Page Offset 3E V Physical Page Number 1 x 1 x7ffe 1 x1 1 x7fff Page Table Hit 15 Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <22>

21 Page Table Challenges Page table is large usually located in physical memory Load/store requires 2 main memory accesses: one for transla>on (page table read) one to access data (amer transla>on) Cuts memory performance in half Unless we get clever Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <23>

22 Transla>on Lookaside Buffer (TLB) Small cache of most recent transla>ons Reduces # of memory accesses for most loads/stores from 2 to 1 Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <24>

23 TLB Page table accesses: high temporal locality Large page size, so consecu>ve loads/stores likely to access same page TLB Small: accessed in < 1 cycle Typically entries Fully associa>ve > 99 % hit rates typical Reduces # of memory accesses for most loads/stores from 2 to 1 Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <25>

24 Example 2-Entry TLB Virtual Address Virtual Page Number x2 19 Page Offset 47C 12 Entry 1 Entry V Virtual Page Number Physical Page Number 1 x7fffd x 1 x2 x7fff V Virtual Page Number Physical Page Number TLB = = Hit 1 Hit 1 Hit 1 Hit 15 Physical Address x7fff 47C 12 Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <26>

25 Memory Protec>on Mul>ple processes (programs) run at once Each process has its own page table Each process can use en>re virtual address space A process can only access physical pages mapped in its own page table Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <27>

26 Program Memory Map Each program has its own virtual to physical mapping Therefore, each program can use the same (virtual) program memory organiza*on Different areas devoted to different types of data Dynamic data à Heap Local variables à Stack Global variables à Global Program code à Text Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <28>

27 Mapping Different Memory Types kernel page table program page table Basic idea: Allow a large virtual address space that can be mapped onto physical memory, as needed Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <29>

28 Virtual Memory Summary Virtual memory increases capacity A subset of virtual pages in physical memory Page table maps virtual pages to physical pages address transla>on A TLB speeds up address transla>on Different page tables for different programs provides memory protec*on Digital Design and Computer Architecture: ARM Edi>on 215 Chapter 8 <3>

Sarah L. Harris and David Money Harris. Digital Design and Computer Architecture: ARM Edition Chapter 8 <1>

Chapter 8 Digital Design and Computer Architecture: ARM Edition Sarah L. Harris and David Money Harris Digital Design and Computer Architecture: ARM Edition 215 Chapter 8 Chapter 8 :: Topics Introduction