--DRAFT-- Data Transmission Receiver

Transcription

1 ALMA Atacama Large Millimeter Array Hardware Definition "ALMA06006NDnnnnR" " " C. Langley, Z. Barnes --DRAFT-- Data Transmission Receiver Chris Langley Zach Barnes NRAO - Socorro, NM NRAO Socorro, NM Keywords: Author Signature: Date: Author Signature: Date: Approved by: Institute: NRAO Signature: Date: Released by: Institute: NRAO Signature: Date:

2 Revision Record 1. Revision: Initial draft Date: Revised by: Reason for / items changed: Revision: Page 2 of 12

3 Table of Contents LIST OF ILLUSTRATIONS OVERVIEW GENERAL DESCRIPTION OF ASSEMBLY/MODULE SUB-ASSEMBLY A (OPTIONAL) SUB-ASSEMBLY B (OPTIONAL) INTERFACES SPECIFICATIONS PERFORMANCE SPECIFICATIONS General description Inputs Outputs Sub-assembly A (optional) Inputs Outputs Sub-assembly B (optional) Inputs Outputs MONITOR/CONTROL INTERFACE General Summary of Monitor Points Summary of Control Points Monitor Points in Detail Control Points in Detail PHYSICAL SPECIFICATIONS Packaging General Connectors Back panel (optional) Front panel (optional) Sub-assembly A (optional) Sub-assembly B (optional) Power Dissipation and Thermal Interface Weight FUNCTIONAL DESCRIPTION AND BLOCK DIAGRAMS GENERAL SUB-ASSEMBLY A (OPTIONAL) SUB-ASSEMBLY B (OPTIONAL) SETUP AND MAINTENANCE REFERENCES ALMA DOCUMENTS ALMA DRAWINGS OTHER REFERENCES DRAWINGS PHOTOS Revision: Page 3 of 12

4 9 DATA SHEETS FOR KEY COMPONENTS Revision: Page 4 of 12

5 LIST OF ILLUSTRATIONS Figures: Figure 1 "title" "page" Tables: Table 1 "title "page" Revision: Page 5 of 12

6 1 OVERVIEW 1.1 General Description of the Data Transmission Receiver (DTR) Module The data path from the output of the Optical Switch (OS) to the Correlator inputs is described in this document. Each antenna utilizes four identical data transmission assemblies. Four Fiber Optic Receiver (FOR) cards, each receiving three optical inputs modulated at 10 Gb/s, receive the optical signals input to this module. These signals are then converted into 10Gb/s digital signals, are amplified, and then are sent to twelve Demultiplexer cards (DMX), which convert each into 16 parallel LVDS streams at 625 Mb/s. Each set of 16 bits are then sent to separate FPGAs on four Deformatter (DFR) cards, where the data is further demultiplexed and ordered into twelve 64-bit LVCMOS streams at 125 Mb/s. This 125Mb/s data then is passed along to the Correlator. For the purpose of this document, only one of an antenna s four DTR assemblies will be covered. 1.2 Sub-assembly FOR Module The first portion of the DTR includes the fiber optic receiver/digital converter. It sits as a mezzanine card 15.24mm above the DFR. 1.3 Sub-assembly DMX Module The second portion of the DTR includes three PCBs that contain the 1:16 digital demultiplexers. These cards reside about 6.3 mm above the DFR. 1.4 Sub-assembly DFR Module The DFR sub-assembly, which the FOR and DMX Modules sit on top of, is the primary PCB for the DTR system. It measures 6U high X 280mm (Euro card). Altogether, these first three assemblies slide into a triple wide station bin space (60mm). 2 INTERFACES The assemblies/modules that interface to the DTR, and their document numbers, are: 48V DC-DC Power Supply 0X00XNDnnnR Optical Switch 06005NDnnnn ALMA Correlator??? Revision: Page 6 of 12

7 3 SPECIFICATIONS 3.1 Performance Specifications General description Each DTS Receiver assembly, of which there are four associated with any one antenna, receives three 10GB/s optical data transmissions from the FO assembly Inputs DTS Deformatter Module Signal # lines Signal Type Voltage I/O/PWR Source Description INPUTS - Receiver Main CLK125 1 Analog/Sine? I LO/REF System 125 MHz Clock +10dBm CLK - 48ms 2 LVDS 350mV diff I LO/REF System 48ms Timing Signal CAN 2* RS422 5 I/O CM Control and FPGA Config RESET 2 RS422 5 I CM Control and FPGA Config POWER +48VDC 1 POWER 48 PWR Power Supply 48VDC, XXXA DC power Outputs DTS Deformatter Module Signal # lines Signal Type Voltage I/O/PWR Source Description OUTPUTS - Receiver Main "B" BIT DATA OUT - BB0 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr "B" BIT DATA OUT - BB1 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr "C" BIT DATA OUT - BB0 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr "C" BIT DATA OUT - BB1 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr "D" BIT DATA OUT - BB0 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr "D" BIT DATA OUT - BB1 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr EDFA_SAFE 2 RS422 5 O EDFA Rack Safety line for EDFA shutoff CAN/RESET 4* RS422 5 I/O CM Control and FPGA Config POWER +48VDC_RET 1 POWER 0 PWR Power Supply Ret Sub-assembly A DTR Fiber Optic Receiver Assembly Inputs Signal # lines Signal Type Voltage I/O/PWR Source Description INPUTS - Optical Receiver Sub-assembly CH1 DATA IN 1 FIBER na I FO Optical Input CH2 DATA IN 1 FIBER na I FO Optical Input CH3 DATA IN 1 FIBER na I FO Optical Input SPI_IN 1 I DFR SPI_CLK 1 I DFR OPTO_CS 1 I DFR Revision: Page 7 of 12

8 48VDC 2 POWER 48 PWR DFR 48VDC, XXXA DC power 5.0VDC 1 POWER 5 PWR DFR 5.0VDC, XXXA DC power 12VDC 2 POWER 12 PWR DFR 12VDC, XXXA DC power Outputs Signal # lines Signal Type Voltage I/O/PWR Destination Description OUTPUTS - Optical Receiver Sub-assembly EDFA_SAFE 2 RS422 5 O EDFA Rack Safety line for EDFA shutoff "B" BIT DATA OUT 1 CML -5.2 O FOR DEMUX 10GB/s LSB "C" BIT DATA OUT 1 CML -5.2 O FOR DEMUX 10GB/s "D" BIT DATA OUT 1 CML -5.2 O FOR DEMUX 10GB/s MSB SPI 3 RS422 DFR 48VDC RETURN 2 POWER 0 PWR DFR GND 18 POWER 0 PWR DFR Sub-assembly B - DTR Demultiplexer Assembly (3 per assembly) Inputs Signal # lines Signal Type Voltage I/O/PWR Source Description INPUTS - Digital Demultiplexer Sub-assembly "B" BIT DATA IN 1 (3) CML -5.2 I FOR DEMUX 10GB/s LSB "C" BIT DATA IN 1 (3) CML -5.2 I FOR DEMUX 10GB/s "D" BIT DATA IN 1 (3) CML -5.2 I FOR DEMUX 10GB/s MSB Demux reset 1 ECL -5.2 I DFR 3.3VDC 3 POWER 3.3 PWR DFR -5.2VDC 3 POWER -5.2 PWR DFR MHz 1 (3) Analog/Sine? I DFR Demux reference clock Outputs IDA_1, _2 2 (6) LVTTL 3.3 O DFR Demux identifier NLDET_1, _2, _3 1 (3) LVTTL 3.3 O DFR demux out of lock detect HSCLK 2 (6) LVDS 350mV diff O DFR 625 MHz data clock HSDATA 32 (96) LVDS 350mV diff O DFR 625 MHz LVDS data GND 18 (54) POWER PWR DFR Sub-assembly C - DTR Deformatter Inputs Signal # lines Signal Type Voltage I/O/PWR Source Description INPUTS - Receiver Main Sub-assembly CLK125 1 Analog/Sine? I/O LO/REF System 125 MHz Clock CLK - 48ms 2 LVDS 350mV diff I LO/REF System 48ms Timing Signal CAN 2* RS422 5 I/O CM Control and FPGA Config Revision: Page 8 of 12

9 RESET 2 RS422 5 I CM Control and FPGA Config POWER +48VDC 1 POWER 48 PWR Power Supply 48VDC, XXXA DC power HSCLK 6 LVDS 3.3 I DMX 625 MHz data clock HSDATA 96 LVDS 3.3 I DMX 625 MHz LVDS data NLDET_1, _2, _3 3 LVTTL 3.3 I DMX Demultiplexer out of lock IDA_1,_2 6 LVTTL 3.3 I DMX Demultiplexer identifiers EDFA_SAFE 2 RS422 5 I FOR Outputs Signal # lines Signal Type Voltage I/O/PWR Destination Description OUTPUTS - Receiver Main Sub-assembly "B" BIT DATA OUT - BB0 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr "B" BIT DATA OUT - BB1 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr "C" BIT DATA OUT - BB0 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr "C" BIT DATA OUT - BB1 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr "D" BIT DATA OUT - BB0 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr "D" BIT DATA OUT - BB1 32 LVCMOS 3.3 O RRCM 125 MHz Data to Corr EDFA_SAFE 2 RS422 5 O EDFA Rack Safety line for EDFA shutoff CAN 2* RS422 5 I/O CM,FOR Control and FPGA Config POWER +48VDC_RET 1 POWER 0 PWR Power Supply Power Supply Ret 3.3VDC 3 POWER 3.3 PWR DMX -5.2VDC 3 POWER -5.2 PWR DMX 12VDC 1 POWER 12 PWR FOR SPI 3 RS422 I/O FOR OPTO_CS 1 O FOR DEMUX RESET 3 LVTTL 3.3 O DMX MHz 3 Analog/Sine? O DMX Demux reference clock 3.2 Monitor/Control Interface General Specify interface type(s) (CAN, RS232, GPIB, ). List interfaces to sub-assemblies. Revision: Page 9 of 12

10 3.2.2 Summary of Monitor Points Name Relative CAN Address (hex) Data Size (Bytes) Source Update Interval Timing Event Related Data Content AMBSI2_SN AMBSI2 10 sec No 64 bit serial # ERROR PIC 10 sec No 1 bit +1.5VDC DFR 10 sec No 10 bits +3.3VDC DFR 10 sec No 10 bits +5.0VDC DFR 10 sec No 10 bits +12VDC DFR 10 sec No 10 bits -5.2VDC DFR 10 sec No 10 bits Re-Sync Count DFR 10 sec No 8 bits Sync-Error Count DFR 10 sec No 8 bits Parity-Error Count A 1 DFR 10 sec No 8 bits Start/Stop Count B 1 DFR 10 sec No 5 bits FIFO Size Buffer C 1 DFR 10 sec No 5 bits Metaframe Delay D 2 DFR 10 sec No 16 bits Sequence Count E 1 DFR 10 sec No 6 bits Scrambling Pat F 8 DFR 10 sec No 64 bits Scrambling Pat DFR 10 sec No 64 bits Scrambling Pat DFR 10 sec No 22 bits Sync Status? DFR 10 sec No? NLDET_ DMX 10 sec No 1 bit NLDET_ DMX 10 sec No 1 bit NLDET_ DMX 10 sec No 1 bit SPI_ACK FOR 10 sec No 1 bit CG_VTUNE Clk Gen 10 sec No 1 bit CG_LOCK Clk Gen 10 sec No 1 bit Name Summary of Control Points Relative CAN Address (hex) Data Size (Bytes) Source Update Interval Timing Event Related Data Content PIC Error Code Reset 1 AMBSI2 As needed No 1 bit FPGA Reset A 1 AMBSI2 As needed No 1 bit Demux Reset B 1 AMBSI2 As needed No 1 bit Revision: Page 10 of 12

11 3.2.4 Monitor Points in Detail. Name: Relative Address: Description: Suggested Interval: Timing Event Related: Units: Conversion Factor: Range: Data: yes or no Control Points in Detail Name: Relative Address: Description: Suggested Interval: Timing Event Related: Units: Conversion Factor: Range: Data: yes or no 3.3 Physical Specifications Packaging 6U high X 280mm Euro card, slides into triple wide (60mm) slot in ALMA Correlator station bin General Connectors Back panel (optional) Front panel (optional) Sub-assembly A (optional) Revision: Page 11 of 12

12 Sub-assembly B (optional) Power Dissipation and Thermal Interface Weight 4 FUNCTIONAL DESCRIPTION AND BLOCK DIAGRAMS 4.1 General Define hot swap requirements, if any. 4.2 Sub-assembly A (optional) 4.3 Sub-assembly B (optional) 5 SETUP AND MAINTENANCE 6 REFERENCES 6.1 ALMA Documents 6.2 ALMA Drawings 6.3 Other References 7 DRAWINGS 8 PHOTOS 9 DATA SHEETS FOR KEY COMPONENTS Revision: Page 12 of 12