Application Note: Optical data transmission with the Avocet Image Sensor

Transcription

1 : Optical data transmission with the Avocet Image Sensor This application note presents a reference design for using optical data transmissions with the MLX75411 Avocet image sensor. The MLX75605 optical transceiver is used to create the optical link. JHU Page 1 of

2 1 Introduction This application note shows how you can use the MLX75605 optical transceiver to convert the data from the Avocet to the optical domain by using a POF cable. The goal is to have a strict optical connection between the MLX75411 and the receiving end. For this reference design, we will re-use the camera head of the evaluation kit EVB This camera head features an LVDS output. In this reference design we will interrupt the LVDS connection between camera head and main board and insert an optical cable. In Figure1, the FPGA on top takes the LVDS input (double serial stream) and converts it into a single serial stream. The FPGA at the bottom takes the serial output from the optical transceiver and converts it back to the original LVDS stream. Figure 1: Overview of the system In a production environment, the LVDS would not be used at all. The parallel output of the Avocet imager will be directly taken by the FPGA and converted into a serial stream as input for the optical transceiver. JHU Page 2 of

3 2 Component overview In the EVB75411 evaluation kit, LVDS is used to transfer data from camerahead to main board. The parallel data is serialized into 2 serial pairs, requiring 2 cable pairs. To transfer the data from the electrical to the optical domain we use the MLX75605 MOST Transceiver as a pure optical transceiver without the MOST protocol to avoid overhead on the optical link. Figure 1 gives a graphical overview of the system. 2.1 MLX75605 The MLX75605 is a 150Mbps MOST transceiver. The MLX75605 embeds a 650nm light source and driver IC. The driver IC includes on chip calibration circuitry to achieve optimal performance by compensating each transceivers LED and process variations. The receiver part consists of monolithic photo-receivers, enabling best in class EMI immunity. The MOST protocol is not used for sending and receiving the imager data. We use the hardware of the MOST transceiver to send the data in a serial way. More info about the MLX75605 can be found in the MLX75605 datasheet. The MLX75605 features a serial data input. This data should be DC balanced. For this, we use the 8b10b protocol used in Ethernet. 2.2 MLX75411 The MLX75411 imager, named Avocet imager, is a CMOS rolling shutter imager. It has a resolution of 1024x512 pixels and a 154dB high dynamic range (HDR). This imager uses a 2 wire serial protocol as a control interface (I 2 C). The video interface is LVTTL. It transmits 12 bits of parallel data, hsync, vsync and a clock. More info about the MLX75411 can be found in the MLX75411 datasheet. 2.3 FPGA board In this reference design we use 2 Spartan3E development boards to do the data conversions. A link to these boards can be found in the appendix at the end of the document. 2.4 Interface PCB The interface PCB to connect to the spartan3e development board contains the MLX75605, the deserializer and serializer used in the Melexis camerahead and a voltage regulator. A single board was designed that can serve a dual purpose: receiving interface or transmitting interface. JHU Page 3 of

4 3 FPGA code The FPGA code consists of 2 parts: the code for the transmitting FPGA and the code for the receiving FPGA. The transmitting FPGA takes the data coming from the camerahead, encodes and serializes this data and sends it to the MLX The receiving FPGA takes the serial data from the MLX75605, deserializes and decodes this data and sends it to the LVDS serializer. After the LVDS serializer, the data is sent to the MLX75411 evaluation kit. 3.1 Transmitter The transmitter code has 4 main blocks: a line buffer, a controller for the buffer, the 8b/10b encoder and a LVDS serializer. Figure 2 shows the main block diagram of the receiving transmitter. Input Line buffer Line buffer control Encoder 8b/10b Serializer output Inputs The inputs for the Receiver FPGA are: PIXD: 12 bit output data from the Avocet PIXCLK: pixel clock from the Avocet VSYNC: vertical blanking signal HSYNC: horizontal blanking signal Figure 2: FPGA transmitter block diagram JHU Page 4 of

5 3.1.2 Line_buffer_control This module generates read and write addresses for the line buffer. It also writes a special code in the line buffer when Hsync or Vsync are low. This code is interpreted by the 8b10b encoder so we can reconstruct the Hsync and Vsync signal out of the serial data stream Line_buffer For the line buffer a module from the core generator is used: Block Memory Generator v3.1. The block memory is configured as a dual port ram. This allows reading and writing with 2 different clocks. We use 2 clocks: one for storing the pixel data in the line buffer, and one for reading back data from the buffer. Figure 3: Avocet line clocks As you can see in Figure 3 there are = 1322 clocks in one line. The first 1024 clocks are used to bring out the data of the 1024 pixels. The last 298 pixels are horizontal blanking. During these clocks no pixel data is sent. It is not required and even inefficient to send the hsync clocks over the optical link. This would be a waste of bandwidth. We recommend to store the 1322 clocks in a line buffer and read them back with a slower clock. This clock will be called: clk_readbuffer. This clock is 4/5 the speed of the pixel clock. With this clock we read the 1024 pixels in the same time as we write the 1322 clocks with the pixel clock of the Avocet. So we can reduce the bandwidth with 1/ Encoder 8b10b The 8b10b encoder encodes 8 bits of data into 10 bits of DC balanced code. Information about how the encoding exactly works can be found on the internet (see wikipedia link in the appendix). The MLX75605 needs the data in a DC balanced format. The 8b/10b protocol takes care of this. It also ensures sufficient bit transitions to recover the clock on the receiving end. The control symbols used for reconstruction the Hsync and Vsync signal are: K28.7, K28.2 and K28.3. The data coming from the Avocet is 12 bits. In this example the lower 4 bits are ignored so it is easier to use the 8b10b encoder. This can be changed so all 12 bits are encoded Serializer The serializer takes the 10 bits coming from the encoder and puts them in a serial stream. The serial clock is 10 times faster then the readbuffer clock. The value of the encoder is hold for one clock of clk_readbuffer. Then each bit is send at a time with the 10 times faster clock Output The serialized data is outputted in LVDS format. These 2 output pins go directly to the MLX Receiver The receiver consists of 5 big blocks: deserializer, decoder 10b/8b, line buffer, line buffer control and recover control signals. The clock can be recovered from the serial datastream. This is not implemented. For now the serial clock is transferred from the transmitting development kit to the receiving kit by using a coax cable. Figure 4 shows the block diagram of the receiver. JHU Page 5 of

6 Input Deserializer Decoder 10b/8b Line buffer decoder Line buffer decoder control Recover control signals Output Figure 4: FPGA receiver block diagram Input The MLX75605 sends out the data in LVDS format. The receiving FPGA gets the data in a serial form Deserializer The deserializer takes the serial stream and converts it into a 10bit parallel stream. The clock from the parallel stream is 10 times lower then the serial clock. To sync the deserializer with the serial datastream we look for the comma signal (K28.7) in the serial datastream. At the start of every hsync, we encoded the K28.7 symbol in the serial datastream. This bitorder is unique in the encoded data so we use this code to lock the deserializer with the serial stream Decoder The decoder converts the encoded data back into the original 8bit data. The decoder outputs the 8 bit of decoded data. It also outputs one extra bit: is_kcode. This bit is turned high by the decoder when a control symbol is detected. When this bit is high, we have to look at the data to know if we have a Hsync or Vsync signal. JHU Page 6 of

7 3.2.4 Line buffer control This module generates read and write addresses for the line buffer Line buffer Just like the transmitter, the line buffer is a dual port ram block. We can read and write at the same time and do this with different clocks Recover control signals This block looks at the is_kchar bit and reconstructs the hsync and vsync signal. When a hsync signal is detected we add the 298 clocks of Hsync which we removed from the serial stream (see 3.1.3) JHU Page 7 of

8 MLX75411/MLX System Figure 5 shows the setup of the optical link. You have the camerahead which is connected to the transmitting FPGA by using an HDMI cable. The left development board is the transmitting FPGA. The right development kit is the receiver. The thin cable is the POF cable connecting the 2 MLX75605 s. Figure 5: Avocet optical link setup Note: the MOST transceivers support only one-way communication on a single fibre. In this setup, the Avocet imager runs in fully automatic mode, including automatic exposure control and automatic high dynamic range control. If imager control is required over optical fibre as well, then a second fibre is needed for upstream communication of the I2C commands. The MLX75605 MOST transceiver already supports 2 fibers: one for downstream and one for upstream communications Figure 6 shows the pcb connected to the transmitting FPGA. The pcb is not completely soldered. All the parts that are needed for the receiving FPGA are left out. Figure 7 shows the pcb connected to the receiving FPGA. The HDMI connector to the bottom should be connected to the Rapidview kit. JHU Page 8 of

9 MLX75411/MLX75605 Figure 6: pcb connected to the transmitting development board Figure 7: pcb connected to the receiving development board JHU Page 9 of

10 5 Appendix A Information about the Spartan3E development kit can be found on the link below. Information about the 8b10b encoding algorithm can be found on the link below. JHU Page 10 of