Basic Concepts. Task One: The Basic Latch. Laboratory Nine Latches, RAM & Android Architecture

Transcription

1 Laboratory Nine Latches, RAM & Android Architecture Basic Concepts 1. The most basic element of binary storage is the latch, consisting of 2 cross-coupled NAND (or NOR) gates. 2. The D-latch with Enable input is a rudimentary "clocked" storage element employing a latch. The Enable serves to enable or inhibit the operation of the latch. 3. The D-Latch is employed in some form in most static random access memory SRAM. 4. An Android Galaxy architecture can be assembled from several sophisticated system components, such as an application processor, SDRAM, NAND flash memory, USB transceiver, and an audio codec. Note: This prelab is worth 10 points Task One: The Basic Latch 1. (Pre) Draw the cross-coupled NAND latch in your notebook, with pin numbers. See the SSI gate data sheet. 2. (Pre) Also draw the timing diagram shown below in your lab notebook, showing input waveforms reset R (notr), set S (nots). Draw dashed vertical lines where NA, Reset, Set and NC modes of operation start on the waveforms. Determine output waveforms and not. (See lecture notes for solutions.) 3. Build the latch circuit in the lab using a input NAND chip, connecting inputs S and R to switches and outputs, not to LEDs. Experiment with your latch and draw a truth table with inputs S and R and outputs and not, identifying the Not allowed (NA), Set, Reset and No Change (NC) modes of operation. 4. Finally, exercise the S and R inputs of your latch according to the waveforms and record the resulting output waveforms. (Mark each operation above the waveforms.)

2 Task Two: D-Latch with Enable 1. (Pre) Draw the D-latch with Enable input circuit depicted at right (with pin numbers). D stands for data. 2. (Pre) Also draw the timing diagram shown below, showing waveforms E (Enable), D (Data). Find outputs & not. Also, mark the mode of operation (NC, Set, Reset) on top of E wave. 3. Build the D-latch using the earlier latch circuit and a 7404 hex inverter chip. Derive a truth table for the D- latch with inputs E and D, outputs and _. Derive a truth table for the D-latch, showing where the NC, Reset, and Set modes of operation take place. 4. Exercise the E and D inputs of your D-latch according to the waveforms and record the resulting output waveforms. (Mark each operation above the waveforms.) Task Three: SRAM D-Latch Register We are going to build a single 8-bit word location for a SRAM memory, using the D-latch design above. This word can be both read and written to (the diagram is not perfect). Build this register byte from 8 Jade D-latch blocks, shown below. Download and test the operation of your register, for example alternating (AA)16 and (55)16 as data input bytes. Ask your TA what they want to see.

3 Task Four: Android Galaxy Assembly We will now build a partial Galaxy phone mobile phone architecture using Xilinx, based on the, capable of receiving and playing a music stream like Pandora using a Codec with a SRAM buffer. (This architecture was designed by Lalith N ) 1. Open the Xilinx Project Navigator (64-bit) on the lab computer. 2. Go to File -> Open Project, and open the GalaxyArch_v2.xise project. Ask your TA for the location of this project. 3. Open the Top.sch schematic file. This block diagram reflects the Galaxy Architecture discussed in class. 4. To stream audio to the board, say what you might see coming from Pandora or even from the NAND memory storage, we will use the Digilent Adept software. 5. Program the BASYS 2 board from the Config tab via the FPGA. 6. Draw a single line (with arrows) through the block diagram showing the path needed to stream the audio file from the USB transceiver, to the SDRAM, and then to the Audio Codec (circles). 7. Examine the contents of one of the sample 16-bit stereo.wav audio files, using the HxD hex viewer.

4 8. Go to the File I/O tab. In the Upload section, browse to the location of the sample audio files and select one. Then tick the Upload entire file checkbox, and enter the Register Address as Click File>>Device. We will transfer the file to a bit word (n =12, m =16) SRAM in place of the SDRAM in the Galaxy block diagram. A progress bar indicates the file being transferred to. Format conversion (such as MP3 to.wav) and format packaging (alternating 16 bits to the left and right channels) is done by the Audio Codec. Plug your headset (or earphones) into the stereo jack and listen to the streaming audio. 10. Viewing I 2 S signals on the PmodI2s module: a. Get the Analog Discovery scope and header pins from your TA. Connect the header pins in place of the PmodI2S module. Use digital probes labeled 0,1,2,3 on the Analog Discovery Scope and, connect them to the signals SDATA, SCLK, LRCLK and MCLK. b. Open the Analyzer window and add DIO 0,1,2,3 signal to the scope. Press the Run button and stream audio to the BASYS2 board. c. You will now see 16-bit stereo music playing here. Use the Audio Codec schematic, describe the purpose of each of the waveforms shown below.

5 50 MHz Crystal USB CHIPSET ADEPT PC BOARD CLOCK CLOCK IN USB TRANSCEIVER WRITE CLOCK SRAM ADDR (A12-A0) DIN (D7-D0) READ CLOCK DOUT (D15-D0) ADDR (A11-A0) CLOCK IN ADDR GEN OE DATA LEFT OE DATA RIGHT MSB LSB D CLK SHIFT REGISTER PL SERIAL DATA D SET WSD D SET WSP CLR CLR LRCLK CLOCK GEN AUDIO CODEC SCLK MCLK PMOD LAB 9 ARCHITECTURE & Codec Created By: Lalith Narasimhan Write Rate: Write Clock x Nbits = 266 KHz x 8 = Mbps Read Rate: Read Clock x Nbits = 88.2 KHz x 16 = Mbps

6 Minimum Flash Size = /