#RRNKECVKQP0QVG. A Two s-complement Fractional Multiplier
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1 #RRNKECVKQP0QVG A Two s-complement Fractional Multiplier
2 TABLE OF CONTENTS ABSTRACT... 3 I. General Overview... 3 DISCUSSION... 3 I. Theory of Operation... 3 II. Results of Operation... 3 SUMMARY... 3 I. Reaffirmation of Results... 3 Information Integrity... 5 Document Disclaimer... 5 Acknowledgements Project Lead Engineer: Application and Support Engineer: System and Code Development:
3 ABSTRACT I. General Overview ZiLOG stwo s-complement Fractional Multiplier is an easy-to-use application that is indispensable in DSP software development. It runs on Windows 95 and Windows NT and allows customers to perform rapid fractional multiplication tests with no coding effort. The software is free and can be downloaded from the DSP area of the ZiLOG website at DISCUSSION II. Theory of Operation DSP operates on two s-complement binary fractional numbers. Though there are other methods of numerical presentation, fractional representation provides advantages for signal processing algorithms. Multiplication of two fractions produces a fractional result, eliminating the possibility of overflows. With algorithms that require use of multiplication and addition, a convenient numerical representation provides efficiency. Various representations include signed, unsigned, integer, fractional, two s-complement, or a combination of these. The following example shows the results obtained using the ZiLOG Z893XX family of 16-bit fixed-point DSP microprocessors. III. Results of Operation The user supplies 2 two s-complement hex operands as input. When the user tabs or clicks on the CALC button, the two s-complement fractional result is returned with both the format and the fractional decimal. SUMMARY I. Reaffirmation of Results The following example multiplies two negative hex numbers: Operands: Action: 9DABh and AEAFh 9DABh x AEAFh Processor: X = 9DABh Y = AEAFh P = 3E7803h Use a calculator to complete the following: 1) Take the two s-complement of both negative numbers (XOR with FFFFh then add 1). 2) Multiply the results. 3) Shift left 1 bit (multiply by 2). 4) Use the most significant 24 bits.
4 6255 (Two s-complement of 9DABh. That is, XOR (9DABh, FFFFh) + 1) x 5151h (Two s -complement of AEAFh. That is, XOR (AEAFh, FFFFh) + 1) 1F3C0IE5h x 2 (Multiply x 2, equivalent to shift left 1 bit) 3E7803CAh 3E7803h (Save the top 24 bits. This value appears in the P register) Fractional: 9DABh conversion d AEAFh conversion d 3E78h conversion d Verification: d x d = d
5 Information Integrity The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Any applicable source code illustrated in the document was either written by an authorized ZiLOG employee or licensed consultant. Permission to use these codes in any form besides the intended application must be approved through a license agreement between both parties. ZiLOG will not be responsible for any code(s) used beyond the intended application. Contact your local ZiLOG Sales Office to obtain necessary license agreements. Document Disclaimer 1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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