Product Change Notification (PCN)
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1 Product Change Notification (PCN) Alliance Memory Inc. 511 Taylor Way, Suite 1, San Carlos, CA Main +1(650) FAX +1(650) Date: June 1, 2017 PCN TRACKING NO:PCN Subject: Product Change Notification (PCN) for Alliance LPSRAM s (64K LPSRAM) Description of Change: Reason for Change Traceability, Guidelines (lot, date code, markings, shipment date) Updated Datasheet Summary of Changes between New and Old part numbers Product will only be offered in a new Die Revision Product revision to provide continuous support to Alliance s customers Traceable through marketing part # Part # has been changed and updated datasheets are posted on our website See table 1 Below Table 1 Density Organization Alliance Part Number Alliance New Part Number 64K 8K x 8 U6264BDC07LLG1 AS6C PCN 64K 8K x 8 U6264BDK07LLG1 AS6C PIN 64K 8K x 8 U6264BS2C07LLG1 AS6C SCN 64K 8K x 8 U6264BS2C07LLG1TR AS6C SCNTR 64K 8K x 8 U6264BS2K07LLG1 AS6C SIN 64K 8K x 8 U6264BS2K07LLG1TR AS6C SINTR 64K 8K x 8 AS6C6264A-70PIN AS6C PIN 64K 8K x 8 AS6C6264A-70PCN AS6C PCN 64K 8K x 8 AS6C6264A-70SIN AS6C SIN 64K 8K x 8 AS6C6264A-70SINTR AS6C SINTR 64K 8K x 8 AS6C6264A-70SCN AS6C SCN 64K 8K x 8 AS6C6264A-70SCNTR AS6C SCNTR Last Time Buy Date: December 31 st 2017 Last Time Ship Date: March 31 st 2018 Sample and Production available NOW Sample Available Date: New Die Rev. has been in production for 10 years PCN Effective Date: June 1 st 2017 *Any orders after July 1 st, 2017 are Non-cancelable / Non-Returnable and cannot be changed. Products cannot be returned in stock rotations after this date. PRODUCTCHANGENOTICE SLS-0009 REVISION*A 1 st June 2017
2 Alliance Memory Inc. 511 Taylor Way, Suite 1, San Carlos, CA Main +1(650) FAX +1(650) Dear Valued Customer: This letter provides End of Life (EOL) notice of ZMD 64K Low Power SRAM products with a 64k density. These ZMD wafer will move from the original ZMD design to the Alliance design in Q Please note that the ZMD design and the Alliance design are both fabricated from Global Foundries in Singapore. The assembly ( Greatek in Taiwan ) and testing (ChipMos in Taiwan) will remain the same. The delivery deadline is March 31st, 2018 with last time buy (LTB) deadline on December 31st, Please note that the standard shipment dates will apply in general and extended delivery dates must be pre-arranged and accepted in writing by Alliance Memory Management. Please see the below comparison between the ZMD design vs. the Alliance design. Samples are available now. Please contact your local Alliance Memory representative if you have any questions regarding this information. Yours sincerely, David Bagby President Alliance Memory Inc. PRODUCTCHANGENOTICE SLS-0009 REVISION*A 1 st June 2017
3 Comparison between AS6C XXN and AS6C6264A-70XXN 64Kb LP-SRAM Part Number&result AS6C PCN AS6C6264A-70PCN AS6C PIN AS6C6264A-70PIN AS6C SCN AS6C6264A-70SCN Comparison Result AS6C SCNTR AS6C6264A-70SCNTR AS6C SIN AS6C6264A-70SIN AS6C SINTR AS6C6264A-70SINTR Wafer Process Power Supply 2.7V~5.5V 4.5V ~ 5.5V Difference Speed:55ns Speed:70ns Typical Power Dissipation of Normal Operation Operating Temperature Max Operating Speed (Input/Output) Capacitance Definition Material s Diagram & Command Icc=45mA(Max.) Icc=55 ma (Max.) Icc1=10mA(Max.) Icc1=3mA(Max.) Standby Power 1μA Standby Power 1μA Difference ISB1= 50μA(Max.), C Temp ISB1= 80μA(Max.), I Temp ISB1= 2μA(Max.),C Temp ISB1= 5μA(Max.), I Temp Industrial:-40 to +85 Industrial:-40 to +85 Commercial:0 to +70 Commercial:0 to ns 70ns Input Capacitance CIN: <6pF. Input Capacitance CIN: <8pF. Input/Output Capacitance CI/ Output Capacitance CO: Difference O: <8pF. <10pF. Omit.(See datasheet) Omit.(See datasheet). They are pin to pin. Pb and Halogen Free Pb and Halogen Free Refer to Table 1 Refer to Table 1 Difference Omit.(See datasheet) Omit.(See datasheet) Capacity 64Kb 64Kb Package 28pin 330mil SOP 28pin 330 mil SOP Truth Table Omit.(See datasheet) Omit.(See datasheet) same Supply Time AS6C6264 will replace AS6C6264A
4 Table 1 AS6C6264 & AS6C6264A AC ELECTRICAL CHARACTERISTICS comparison READ CYCLE AS6C6264 AS6C6264A Read Cycle Time trc ns Address Access Time taa ns Chip Enable Access Time tace ns Output Enable Access Time toe ns Chip Enable to Output in Low-Z tclz* 10 - ns Output Enable to Output in Low-Z tolz* ns Chip Disable to Output in High-Z tchz* ns Output Disable to Output in High-Z tohz* ns Output Hold from Address Change toh ns WRITE CYCLE AS6C6264 AS6C6264A Write Cycle Time twc ns Address Valid to End of Write taw ns Chip Enable to End of Write tcw ns Address Set-up Time tas ns Write Pulse Width twp ns Write Recovery Time twr ns Data to Write Time Overlap tdw ns Data Hold from End of Write Time tdh ns Output Active from End of Write tow* 5 - ns Write to Output in High-Z twhz* ns
5 Comparison between AS6C XXN and U6264BXXX07LLG1 64Kb LP-SRAM Part Number&result AS6C PCN U6264BDC07LLG1 AS6C PIN U6264BDK07LLG1 AS6C SCN U6264BS2C07LLG1 Comparison Result AS6C SCNTR U6264BS2C07LLG1TR AS6C SIN U6264BS2K07LLG1 AS6C SINTR U6264BS2K07LLG1TR Wafer Process Power Supply 2.7V~5.5V 4.5V ~ 5.5V Difference Typical Power Dissipation of Normal Operation Operating Temperature Max Operating Speed (Input/Output) Capacitance Definition Material s Diagram & Command Speed:55ns Icc=45mA(Max.) peed:70ns Icc=55 ma (Max.) Icc1=10mA(Max.) Icc1=3mA(Max.) Standby Power μa Standby Power μa Difference ISB1= 50μA(Max.), C Temp ISB1= 80μA(Max.), I Temp ISB1= 2μA(Max.),C Temp ISB1= 5μA(Max.), I Temp Industrial:-40 to +85 Industrial:-40 to +85 Commercial:0 to +70 Commercial:0 to ns 70ns Input Capacitance CIN: <6pF. Input Capacitance CIN: <8pF. Input/Output Capacitance Output Capacitance CO: Difference CI/O: <8pF. <10pF. Omit.(See datasheet) Omit.(See datasheet). They are pin to pin. Pb and Halogen Free Pb and Halogen Free Refer to Table 1 Refer to Table 1 Difference Omit.(See datasheet) Omit.(See datasheet) Capacity 64Kb 64Kb Package 28pin 330mil SOP 28pin 330 mil SOP Truth Table Omit.(See datasheet) Omit.(See datasheet) same Supply Time AS6C6264 will replace U6264B
6 Table 1 AS6C6264 & U6264B AC ELECTRICAL CHARACTERISTICS comparison READ CYCLE AS6C6264 U6264B Read Cycle Time trc ns Address Access Time taa ns Chip Enable Access Time tace ns Output Enable Access Time toe ns Chip Enable to Output in Low-Z tclz* 10 - ns Output Enable to Output in Low-Z tolz* ns Chip Disable to Output in High-Z tchz* ns Output Disable to Output in High-Z tohz* ns Output Hold from Address Change toh ns WRITE CYCLE AS6C6264 U6264B Write Cycle Time twc ns Address Valid to End of Write taw ns Chip Enable to End of Write tcw ns Address Set-up Time tas ns Write Pulse Width twp ns Write Recovery Time twr ns Data to Write Time Overlap tdw ns Data Hold from End of Write Time tdh ns Output Active from End of Write tow* 5 - ns Write to Output in High-Z twhz* ns
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IS62WV12816DALL/DBLL IS65WV12816DALL/DBLL
IS62WV12816DALL/DBLL IS65WV12816DALL/DBLL 128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JUNE 2013 FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation 36 mw (typical) operating
1Mx16 16Mb DRAM WITH FAST PAGE MODE SEPTEMBER 2018
1Mx16 16Mb DRAM WITH FAST PAGE MODE SEPTEMBER 2018 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms Refresh Mode: -Only, CAS-before- (CBR), and Hidden JEDEC
MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION
![MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION](/thumbs/78/78720826.jpg "MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION")
FEATURES 32K x 8 organization Single +5V power supply +125V programming voltage Fast access time: 45/55/70/90/100/120/150 ns Totally static operation Completely TTL compatible 256K-BIT [32K x 8] CMOS EPROM
CAT22C Bit Nonvolatile CMOS Static RAM
256-Bit Nonvolatile CMOS Static RAM FEATURES Single 5V Supply Fast RAM Access Times: 200ns 300ns Infinite E 2 PROM to RAM Recall CMOS and TTL Compatible I/O Power Up/Down Protection 100,000 Program/Erase
16Mbit, 512KX32 CMOS S-RAM MODULE
16Mbit, 512KX32 CMOS S-RAM MODULE Features Access Times: 25, 35 and 45ns Package Options: 66-Pin Ceramic PGA 1.385" SQ 66-Pin Ceramic PGA 1.173" SQ 68-Lead Ceramic QFP 0.88" SQ Fit & Function JEDEC 68-CQFP
White Electronic Designs
12Kx32 EEPROM MODULE, SMD 5962-9455 FEATURES Access Times of 120**, 140, 150, 200, 250, 300ns Packaging: 66-pin, PGA Type, 27.3mm (1.075") square, Hermetic Ceramic HIP (Package 400) 6 lead, 22.4mm sq.
M Rev: /10
www.centon.com MEMORY SPECIFICATIONS 16,777,216 words x 64Bit Synchronous Dynamic RAM Memory Module (Unbuffered DIMM) Centon's 128MB Memory Module is 16,777,216 words by 64Bit Synchronous Dynamic RAM Memory
HIGH SPEED 4K X 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
HIGH SPEED 4K X 8 DUAL-PORT STATIC RAM WITH SEMAPHORE IDT7142/ Features High-speed access Commercial: 2//5/45//7 (max.) Industrial: (max.) Low-power operation IDT7142 Active: 7mW (typ.) Standby: 5mW (typ.)
MB85R1002A. 1 M Bit (64 K 16) Memory FRAM CMOS. DS v01-E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET
FUJITSU SEMICONDUCTOR DATA SHEET DS501-00004-0v01-E Memory FRAM CMOS 1 M Bit (64 K 16) MB85R1002A DESCRIPTIONS The MB85R1002A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 65,536 words
64K x 32 Static RAM Module
31 CYM1831 Features High-density 2-Mbit SRAM module 32-bit standard footprint supports densities from 16K x 32 through 1M x 32 High-speed CMOS SRAMs Access time of 15 ns Low active power 5.3W (max.) SMD
IS41C16256C IS41LV16256C
256Kx16 4Mb DRAM WITH EDO PAGE MODE JANUARY 2013 FEATURES TTL compatible inputs and outputs; tri-state I/O Refresh Interval: 512 cycles/8 ms Refresh Mode : -Only, CAS-before- (CBR), and Hidden JEDEC standard
D0 - D8 INPUT REGISTER. RAM ARRAY 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 OUTPUT REGISTER RESET LOGIC RCLK REN1
CMOS SyncFIFO 64 x 9, 256 x 9, 512 x 9, 1,24 x 9, 2,48 x 9, 4,96 x 9 and 8,192 x 9 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 218 FEATURES: 64 x 9-bit organization (IDT72421)
HIGH SPEED 64K (4K X 16 BIT) IDT70824S/L SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM )
HIGH PEED 64K (4K X 16 BIT) IDT784/ EQUENTIA ACCE RANDOM ACCE MEMORY (ARAM ) Features High-speed access : /4 (max.) Commercial: ///4 (max.) ow-power operation IDT784 Active: 77mW (typ.) tandby: mw (typ.)
IS41C16100C IS41LV16100C
1Mx16 16Mb DRAM WITH EDO PAGE MODE FEBRUARY 2012 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: Auto refresh Mode: 1,024 cycles /16 ms -Only, CAS-before- (CBR), and Hidden Self
16Mbit, 512KX32 CMOS S-RAM MODULE
16Mbit, 512KX32 CMOS S-RAM MODULE Features Access Times: 17 and 20ns Package Options: 66-Pin Ceramic PGA 1.080" SQ 66-Pin Ceramic PGA 1.173" SQ 68-Lead Ceramic QFP 0.88" SQ Fit & Function JEDEC 68-CQFJ
FM Kb Bytewide FRAM Memory
64Kb Bytewide FRAM Memory Features 64K bit Ferroelectric Nonvolatile RAM Organized as 8,192 x 8 bits High endurance 10 Billion (10 10 ) read/writes 10 year data retention at 85 C NoDelay write Advanced
512KX8 CMOS S-RAM (Monolithic)
512KX8 CMOS S-RAM (Monolithic) Features Access Times: 55, 70, 85 and 100ns Package Option: 32-Pin Ceramic DIP, JEDEC Approved Pinout 36-Lead Ceramic SOJ JEDEC Approved Revolutionary Pinout 32-Lead Ceramic
4Mbit, 512KX8 5V Flash Memory (Monolithic)
4Mbit, 512KX8 5V Flash Memory (Monolithic) Features 5V Programming, 5V±10% Supply TTL Compatible Inputs and CMOS Outputs Access Times: 90, 120 and 150ns Low Vcc Write Inhibit 3.2v 8 Equal Size Sectors
AT24C01A/02/04/08/16. 2-Wire Serial CMOS E 2 PROM. Features. Description. Pin Configurations. 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8)
AT24C01A/02/04/08/16 Features Low Voltage and Standard Voltage Operation 5.0 (V CC = 4.5V to 5.5V) 2.7 (V CC = 2.7V to 5.5V) 2.5 (V CC = 2.5V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Internally Organized 128
WINTEC I. DESCRIPTION: III. TIMING
ISIONS ZONE DESCRIPTION APPVD 1/26/01 NR I. DESCRIPTION: III. TIMING is a 8Mx64 industry standard 8-pin PC-100 DIMM Manufactured with 4 8Mx 400-mil TSOPII-54 100MHz Synchronous DRAM devices Requires 3.3V+/-0.3V
4-Mbit (512K x 8) Static RAM
4-Mbit (512K x 8) Static RAM Features Temperature Ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive: 40 C to 125 C High speed t AA = 10 ns Low active power 324 mw (max.) 2.0V data retention
MB85R1001A. 1 M Bit (128 K 8) Memory FRAM CMOS. DS v01-E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET
FUJITSU SEMICONDUCTOR DATA SHEET DS501-00003-0v01-E Memory FRAM CMOS 1 M Bit (128 K 8) MB85R1001A DESCRIPTIONS The MB85R1001A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 131,072
GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND
1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE DECEMBER 2006 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: Auto refresh Mode: 1,024 cycles /16 ms -Only, CAS-before- (CBR),
CAT28C17A 16K-Bit CMOS PARALLEL EEPROM
16K-Bit CMOS PARALLEL EEPROM HALOGENFREE LEAD TM FREE FEATURES Fast Read Access Times: 200 ns Low Power CMOS Dissipation: Active: 25 ma Max. Standby: 100 µa Max. Simple Write Operation: On-Chip Address
K1C6416B2D Document Title 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory 2 Revision History Revision No. History Draft Date Remark 0.
64Mb (4M x 16 bit) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,024 X 9, 2,048 X 9, 4,096 x 9 and 8,192 x 9
Integrated Device Technology, Inc. CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,24 X 9, 2,48 X 9, 4,96 x 9 and 8,192 x 9 IDT72421 IDT7221 IDT72211 IDT72221 IDT72231 IDT72241 IDT72251 FEATURES: 64 x 9-bit
AL422 Data Sheets (Revision V1.1)
Data Sheets (Revision V1.1) Amendments (Since April 2, 1999) 05-13-99 DC/AC characteristics (including current consumption) updated. 07-02-99 Pinout diagram (5.0) and DC external load (7.4) modified. 08-03-99
IS62/65WVS1288FALL IS62/65WVS1288FBLL. 128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE DESCRIPTION
128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE JANUARY 2018 KEY FEATURES SPI-Compatible Bus Interface: - 16/20 MHz Clock rate - SPI/SDI/SQI mode Low-Power CMOS Technology: - Read Current:
M0360. Rev: /08
www.centon.com MEMORY SPECIFICATIONS 32MX8 BASED 33,554,432words x 72Bit Synchronous Dynamic RAM Memory Module (Unbuffered DIMM) Centon's 256MB ECC UNBUFFERED Memory Module is 33,554,432 words by 72Bit
PRODUCT/PROCESS CHANGE NOTICE (PCN)
PCN #: Integrated Device Technology, Inc. MEANS OF DISTINGUISHING CHANGED DEVICES: Product Affected: 7132, 7133 and 7134 Families Product Mark Back Mark Manufacturing Location Affected: Salinas, California