Version PA 6.4 December 11, 2009

Transcription

1 1(32) Receiver: Info: M. Carstens Behrens mycable GmbH Manual MB 91F467 / MB Evaluation Board Version December 11,

2 2(32)

3 3(32) Developer s Manual for the MB 91F467 / MB Evaluation Board Summary This manual provides detailed technical information for system architects, hardware and software developers, who work with the MB 91F467 / MB Evaluation board version PA6 for evaluation and development purpose. Enclosures None. Product Information The MB 91F467 / MB Evaluation board is populated with the 32 bit CPU MB91F467, graphic display controller MB also called LIME, Flash memory, SDRAM, SRAM, interfaces as UART, Ethernet, CAN, GPIOs, video inputs and outputs.

4 4(32) History Version Sign PA mo Create this document PA mo First preliminary version PA mo Correction X800 and X801 in picture mo Little writing corrections, 2.2.6, , Pic 2 1, 2 14 Contact Information mycable GmbH Michael Carstens Behrens ( hardware and commercial ) mcb@mycable.de Tel Description

5 5(32) Table of Contents 1 OVERVIEW Manual Scope Putting into Operation MB 91F467 / MB EVALUATION BOARD System Architecture Function Units Power Supply Reset CPU MB91F467DA Graphic Display Controller MB86276 LIME Buttons LEDs Serial Ports Ethernet CAN Interfaces Video Inputs Video Outputs GPIOs Hardware Variants Placement of Components Mechanical Dimensions...29

6 6(32) 1 Overview 1.1 Manual Scope This manual provides detailed technical information about the MB 91F467 / MB Evaluation board for system architects, hardware and software developers covering: System architecture description and users manual Hardware architecture Mechanical information It is the engineer s reference for evaluation, system development and prototyping based on the module. This document covers all available hardware versions regarding their configuration options and revision state. 1.2 Putting into Operation

7 7(32) 2 MB 91F467 / MB Evaluation Board 2.1 System Architecture The system architecture of the MB 91F467 / MB Evaluation board is shown in picture 2 1. Pic. 2 1: MB 91F467 / MB Evaluation board block diagram

8 8(32) Picture 2 2: MB 91F467 / MB Evaluation Board top side Picture 2 3: MB 91F467 / MB Evaluation Board bottom side

9 9(32) 2.2 Function Units Overview in the available interfaces: 10/100 Ethernet 2x serial ports 2x CAN DVI I Power supply Video Inputs GPIOs Video Outputs

10 10(32) Power Supply Picture 2 4: Power supply connector Connect the MB 91F467 / MB Evaluation board with a power supply between 5 and 34 V DC and approximate 10 Watt at connector X100. Be aware to use the correct polarity as shown in picture 2 5. Pic. 2 5: Polarity of the power supply connector A protection against wrong polarity ( D109 ) and overcurrent ( F100 ) is implemented but a too high current can damage the power supply or can produce great heat! U101 LT V The required voltages V and V will be regulated from the dual switching power regulator LT1940EFE PBF from Linear Technologies ( U100 ) on the board.

11 11(32) Reset The triple processor supervisor TPS DGN from Texas Instruments ( U102 ) generates a power on reset and monitors the 1.8 V, 3.3 V and 5.0 V power supplies. Also if the reset button SW100 will be pressed the supervisor circuit generates a reset CPU MB91F467DA Pic. 2 6: CPU MB91F467DA The CPU MB91F467DA from Fujitsu ( U500 ) is used. External 2x 1 Gbit Flash Memory ( U580, U581 ), 2x 128Mx16 SDRAM ( U590, U591 ) and 512kx16 SRAM ( U592 ) are connected. The mode pins of the CPU MD_2 and MD_1 are set fixed to logical '0'. The logical level of mode pin MD_0 can be set with switch SW500. If the switch is open the MD_0 pin is logical '1'. If the switch is closed the MD_0 pin is logical '0'.

12 12(32) MD[2:0] = '000' : Internal ROM Vector mode, Reset vector access: internal Flash. This is the standard setting where the internal Flash memory of the device is available. ( see Hardware Manual MB91460 Serie Chapter 9 Reset 4.3 MD: Mode Pins ) MD[2:0] = '001' : External ROM Vector mode, Reset vector access: external.

13 13(32) The CPU MB91F467DA has following features Core frequency 96 MHz Resource frequency 48 MHz Watchdog Bit Search Reset Input Clock Modulator DMA 5 ch MPU/EDSU 16 BP (8 MPU ch) Flash external 1024 kb + 64 kb Flash Protection D bus RAM 32 kb GP RAM 32 kb Direct mapped cache 8 kb Boot ROM 4 kb RTC 1 ch Free Running Timer 8 ch ICU 8 ch OCU 8 ch Reload Timer 8 ch PPG 12 ch PFM 1 ch Sound Generator 1 ch UpDown Counter 3 ch C_CAN 3 ch (32 msg buffer) LIN USART 5 ch (4 ch FIFO) I2C 3 ch FR external bus 32 bit address / 32 bit data 26 bit address / 32 bit data External Interrupts 14 ch SMC 6 ch ADC (10 bit) 24 ch Alarm Comparator 1 ch Low voltage detection and Clock Supervisor

14 14(32) Following picture shows the block diagram of the CPU. More details see data sheet. Pic. 2 7: Block diagram of CPU MB91F467DA

15 15(32) Graphic Display Controller MB86276 LIME Pic. 2 8: Graphic display controller MB86276 The graphic display controller MB86276 ( U300 ) also called LIME from Fujitsu is connected to the CPU. The MB86276 has following features: CMOS 0.18µm technology Internal and memory frequency : 133MHz ( generated by on chip PLL ) Base clock for display clocks : 400.9MHz ( generated by on chip PLL ) Display resolutions typically from 320x240 up to 1280x768 6 layers of overlay display ( windows ) Alpha Plane and constant alpha value for each layer Digital Video input ( various formats including YUV, RGB ) Video Scaler ( up/down scaling ) Brightness, Contrast, Saturation control for video input

16 16(32) RGB digital output ( 8bit x 3 ) Built in alpha blending, anti aliasing and chroma keying Rendering Engine for various kinds of 2D graphic acceleration functions Texture Mapping Unit for 2D polygon support up to 4096x4096 textures Bit Blt Unit for transfers up to 4096x4096 areas Alpha Bit Blt and ROP2 functions External 32 bit SDRAM interface for up to 32MB graphic memory Parallel host interface ( FR, SH3, SH4, V850, SparcLite etc ) New additional serial control interface as host interface ( I2C based ) Internal and external DMA support I2C interface and GPIO inputs/outputs Supply voltage 3.3V ( I/O ), 1.8V ( Internal ) BGA 256 Package ( 1.27mm pitch ) Typical power consumption < 1.0 W ( estimated ) Temperature range C Further details see data sheet.

17 17(32) Buttons Pic. 2 9: Buttons If the button SW100 which is not labeled will be pressed a reset will be generated. If the button SW501 which is labeled with ABORT will be pressed the interrupt 0 ( P24_0 ) will be generated. If the button SW502 which is labeled with TEST1 will be pressed the interrupt 4 ( P24_4 ) will be generated. If the button SW503 which is labeled with TEST2 will be pressed the interrupt 5 ( P24_5 ) will be generated. If the button SW504 which is labeled with TEST3 will be pressed the interrupt 6 ( P24_6 ) will be generated LEDs Pic. 2 10: LEDs The LED D104 which is labeled with RES is on if the reset is active. The LED D105 which is labeled with 1.8V is on if the 1.8 V power supply is on independent of the limits. The LED D106 which is labeled with 3.3V is on if the 3.3 V power supply is on independent of the limits. The LED D107 which is labeled with 5.0V is on if the 5.0 V power supply is on independent of the limits. D500 ( DIAG1 ), D501 ( DIAG2 ), D502 ( DIAG3 ) and D503 ( DIAG4 ) are free usable LEDs. A logical '0' port signal switches the LED on. A logical '1' port signal switches the LED off.

18 18(32) Following table shows the assignment of LED, label and GPIO. LED Label GPIO D500 DIAG1 P25_0 D501 DIAG2 P25_1 D502 DIAG3 P25_2 D503 DIAG4 P25_3 Table 2 9: LED GPIO assignment Serial Ports Pic. 2 11: Serial port connectors UART 0 is available at the 9 pin Sub D female connector X800 with RS 232 inputs and outputs. UART 1 is available at the 9 pin Sub D female connector X801 with RS 232 inputs and outputs. As transceiver with enhanced electrostatic discharge ( ESD ) protection the MAX3243EIPW ( U800, U801 ) are used. Following table shows the assignment of pins, signals and function from the UART connector X800. Connector X801 is identical. For X801 the index 0 has to be changed to 1.

19 19(32) Pin Signal Function 1 RS232_0_CD Data carrier detect 2 RS232_0_TXD Transmit data 3 RS232_0_RXD Receive data 4 RS232_0_DSR Data set ready 5 GND 6 RS232_0_DTR Data terminal ready 7 RS232_0_CTS Clear to send 8 RS232_0_RTS Request to send 9 RS232_0_RI Ground Ring indicator Table 2 4: Pin assignment X800 and X Ethernet Pic. 2 12: Ethernet connector

20 20(32) At the RJ45 connector X600 the Ethernet interface is available. The Ethernet interface is implemented with the 10/100 Ethernet controller LAN9218 ( U600 ) from SMSC. The LAN9218 is connected to the 32 Bit processor interface of the CPU. The LAN9218 is fully IEEE BASE T and 802.3u 100BASE TX compliant and supports HP Auto MDIX. The LAN9218 includes an integrated Ethernet MAC and PHY, large transmit and receive data FIFOs with a high speed host bus interface to accommodate high bandwidth and high latency applications.the LAN9218 also supports features which reduce or eliminate packet loss. Its internal 16 kbyte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9218 can automatically generate flow control packets to the remote node or assert back pressure on the remote node by generating network collision. The default ethernet setting by pin strapping at the SPD_SEL pin of U600 is speed 100 Mbps, half duplex and auto negotation enabled because this pin will be strapped to VCC by the 10k Ohm resistor R609. It is possible to strap this pin to ground by a 0 Ohm resistor R612 then the settings would be speed 10 Mbps, half duplex and auto negotiation disabled. The FIFO_SEL pin of U600 can be strapped by 0 Ohm resistor R613 to ground. If this resistor is not populated the FIFO_SEL pin is strapped by the 10k Ohm resistor R610 to VCC then all accesses to U600 are to the RX or TX data FIFO and the upper addresses A[7:3] are ignored. As default the AMDIX_EN pin of U600 is strapped by the 10k Ohm resistor R611 to VCC so Auto MDIX is enabled. That means if the user plugs in either a direct connect LAN cable or a cross over patch cable U600 is capable of configuring the TPO and TPI twisted pair pins for correct transceiver operation. It is possible to strap this pin to ground by a 0 Ohm resistor R614 then Auto MDIX is disabled.

21 21(32) CAN Interfaces Pic. 2 13: CAN connector At the 9 pin SubD female connector X700 are two CAN interfaces CAN0 and CAN1 available. The CAN transceiver SN65HVD234D from Texas Instruments ( U700 and U701 ) provides transmit and receive capability between the differential CAN bus and the LIME with its implemented CAN controllers. The RS pin 8 of the SN65HVD234 provides for three modes of operation: high speed, slope control or low power standby mode. The high speed mode of operation is selected by connecting pin 8 directly to ground, allowing the driver output transistors to switch on and off as fast as possible with no limitation on the rise and fall slope. The rise and fall slope can be adjusted by connecting a resistor to ground at pin 8, since the slope is proportional to the pin s output current. Slope control is implemented with a resistor value of 10 k to achieve a slew rate of 15 V/us and a value of 100 k to achieve 2.0 V/ s slew rate. The SN65HVD234 enter a low current standby mode during which the driver is switched off and the receiver remains active if a high logic level is applied to pin 8. The local protocol controller reverses this low current standby mode when it needs to transmit to the bus. The SN65HVD234 enters an ultralow current sleep mode in which both the driver and receiver circuits are deactivated if a low logic level is applied to EN pin 5. The device remains in this sleep mode until the circuit is reactivated by applying a high logic level to pin 5.

22 22(32) 120 Ohm termination is configurable per line via switches on board: SW700: 120 Ohm Termination for CAN 0 SW701: 120 Ohm Termination for CAN 1 Pic. 2 14: Switches for termination resistors Following table shows the assignment of pins, signals and function from the CAN connector X700: Pin Signal Function 1 VCC33 3,3V switchable via R702 2 EXT_CAN0L CAN 0 Low 3 GND Ground 4 EXT_CAN1L CAN 1 Low 5 GND Ground 6 GND Ground 7 EXT_CAN0H CAN 0 High 8 EXT_CAN1H CAN 1 High 9 VCC50 5V swichable via R701 Table 2 6: Pin assignment X800

23 23(32) Video Inputs Pic. 2 15: Video input connectors The Cinch video connectors X480 ( AVIN0 ) and X481 ( AVIN1 ) are connected directly to GDC module interface connector X301 pin 35 and 37 ( Ground pin 33 and 34 ). Two video inputs are available. The Cinch connector X500 for a colour video baseband signal ( CVBS ) and X501 ( FTSH DV from Samtec ) for digital video inputs with ITU 656 format. The analog input signals will be decoded to digital video signals with ITU 656 format from the 9 bit video input processor SAA7113H ( U500 ) from Philips Semiconductors. The outputs from the SAA7113H are connected to the video capture interface from the LIME. The SAA7113H will be controlled by I2C interface 0. The RTS0 pin from SAA7113H is strapped to ground so the slave address for readings is 0x49 and the slave address for writings is 0x48.

24 24(32) Video Outputs Pic. 2 16: Video output connectors The digital RGB video output 0 from the LIME is connected to connector X402, transmitter SiI164CT64 ( U400 ) and triple 8 Bit high speed video digital to analog converter ( DAC ) ADV7125JSTZ240 ( U402 ). The digital RGB video output 1 from the LIME is connected to connector X403, transmitter SiI164CT64 ( U401 ) and triple 8 Bit high speed video digital to analog converter ( DAC ) ADV7125JSTZ240 ( U403 ). The type from X402 and X403 is FTSH L DV EJ P from Samtec, mate with Samtec types FFSD, CLP, FLE, SFMC, SFMH, TFMDL. The transmitter SiI164CT64 ( U400 and U401 ) from Silicon Image uses PanelLink Digital technology to support displays ranging from VGA to UXGA resolutions ( Mpps ) in a single link interface. The link interface of U400 is connected to DVI I connector X400. The link interface of U401 is connected to DVI connector X401.The SiI164 transmitter has a highly flexible interface with either a 12 bit mode ( ½ pixel per clock edge ) or 24 bit mode 1 pixel / clock input for true color ( 16.7 million ) support. In 24 bit mode, the SiI164 supports single or dual edge clocking. In 12 bit mode, the SiI164 supports dual edge single clocking or single edge dual clocking.

25 25(32) The SiI164 can be programmed though the I2C interface. The multi function address inputs A1, A2 and A3 of U400 are strapped to ground by resistors R409, R410 and R412 so the slave address for readings is 0x71 and the slave address for writings is 0x70. The multi function address inputs of U401 A2 and A3 are strapped to ground by resistor R423 and R424 and A1 is strapped to VCC by resistor RN402 so the slave address for readings is 0x73 and the slave address for writings is 0x72. The SiI164 support receiver and hot plug detection. The triple 8 Bit high speed video digital to analog converter ( DAC ) ADV7125JSTZ240 ( U402 and U403 ) from Analog Devices convert the digital RGB666 video output signals from the LIME to an analog video signals. Outputs from U402 are connected to DVI I connector X400. Outputs from U403 are connected to DVI I connector X401. Following table shows the assignment of pins, signals and function from the connectors X402 and X403. For X403 the index 0 has to be changed to 1. Pin Signal Function 1 GND Ground 2 GND Ground 3 VO0_B0 Digital RGB output 0 Data blue 4 VO0_B1 Digital RGB output 1 Data blue 5 VO0_B2 Digital RGB output 2 Data blue 6 VO0_B3 Digital RGB output 3 Data blue 7 VO0_B4 Digital RGB output 4 Data blue 8 VO0_B5 Digital RGB output 5 Data blue 9 VO0_B6 Digital RGB output 6 Data blue 10 VO0_B7 Digital RGB output 7 Data blue 11 VO0_G0 Digital RGB output 0 Data green 12 VO0_G1 Digital RGB output 1 Data green 13 VO0_G2 Digital RGB output 2 Data green 14 VO0_G3 Digital RGB output 3 Data green 15 VO0_G4 Digital RGB output 4 Data green 16 VO0_G5 Digital RGB output 5 Data green 17 VO0_G6 Digital RGB output 6 Data green 18 VO0_G7 Digital RGB output 7 Data green 19 VCC V 20 VCC V 21 VCC V

26 26(32) Pin Signal Function 22 VCC V 23 VO0_R0 Digital RGB output 0 Data red 24 VO0_R1 Digital RGB output 1 Data red 25 VO0_R2 Digital RGB output 2 Data red 26 VO0_R3 Digital RGB output 3 Data red 27 VO0_R4 Digital RGB output 4 Data red 28 VO0_R5 Digital RGB output 5 Data red 29 VO0_R6 Digital RGB output 6 Data red 30 VO0_R7 Digital RGB output 7 Data red 31 VO0_HSYNC Video output interface horizontal sync output 32 VO0_VSYNC Video output interface vertical sync output 33 VO0_DE DE / CSYNC 34 VO0_CSYNC DE / CSYNC 35 VO0_GV 36 VO0_CLK_RGBD Video output interface dot clock output 37 I2C_SCL I2C interface 0 SCL 38 I2C_SDA I2C interface 0 SDA 39 GND Ground 40 GND Ground Table 2 7: Pin assignment X402 and X403

27 27(32) GPIOs Pic. 2 17: GPIO connector Some GPIOs from the CPU are available at connected X900 FTSH L DV K A P from Samtec. Following table shows the assignment of pins, signals and function from the connector X900: Pin Signal Function 1 VCC V 2 GPIO0 P14_0 3 GPIO1 P14_1 4 GPIO2 P16_4 5 GPIO3 P16_5 6 GPIO4 P16_6 7 GPIO5 P16_7 8 GPIO6 P27_0 9 GPIO7 P27_1 10 GPIO8 P27_2 11 GPIO9 P27_3 12 GPIO10 P27_4

28 28(32) Pin Signal Function 13 GPIO11 P27_5 14 GPIO12 P27_6 15 GPIO13 P27_7 16 GPIO14 P26_0 17 GPIO15 P26_1 18 GPIO16 P26_2 19 GPIO17 P26_3 20 GND Ground

29 29(32) 2.3 Hardware Variants Up to now only PCB version PA6 without variants is available.

30 30(32) 2.4 Placement of Components

31 31(32)

32 32(32) 2.5 Mechanical Dimensions The MB 91F467 / MB Evaluation board has a size of x mm.