32-bit FR81S Microcontroller

Transcription

1 32-bit FR81S Microcontroller The MB91520 series is a Cypress 32-bit microcontroller designed for automotive devices. This series contains the FR81S CPU which is compatible with the FR family. Note:This series is a composition of the end of the above-mentioned each name of articles of presence, According to Presence of sub-clock, CSV initial value and LVD initial value. Please see "Ordering Information" for details. Features FR81S CPU Core 32-bit RISC, load/store architecture, pipeline 5-stage structure Maximum operating frequency: 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied (PLL clock multiplication system)) General-purpose register : 32 bits 16 sets 16-bit fixed length instructions (basic instruction), 1 instruction per cycle Instructions appropriate to embedded applications Memory-to-memory transfer instruction Bit processing instruction Barrel shift order etc. High-level language support instructions Function entry/exit instructions Register content multi-load and store instructions Bit search instructions Logical 1 detection, 0 detection, and change-point detection Branch instructions with delay slot Overhead reduction during branch process Register interlock function Easy assembler writing The support at the built-in / instruction level of the multiplier Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles Interrupt (PC/PS saving) 6 cycles (16 priority levels) The Harvard architecture allows simultaneous execution of program and data access. Instruction compatibility with the FR Family Built-in memory protection function (MPU) Eight protection areas can be specified commonly for instructions and the data. Control access privilege in both privilege mode and user mode. Built-in FPU (floating point arithmetic) IEEE754 compliant Floating-point register 32-bit 16 sets Peripheral Functions Clock generation (equipped with SSCG function) Main oscillation (4 MHz to 16 MHz) Sub oscillation (32 khz) or none sub oscillation PLL multiplication rate : 1 to 20 times Equipped with a 100 khz CR oscillator Built-in program flash memory capacity MB91F522: KB MB91F523: KB MB91F524: KB MB91F525: KB MB91F526: KB Flash memory for built-in data (WorkFlash) 64 KB Built-in RAM capacity Main RAM MB91F522: 48 KB MB91F523: 48 KB MB91F524: 64 KB MB91F525: 96 KB MB91F526: 128 KB Backup RAM 8 KB General-purpose ports: MB91F52xB 44 sets (No sub oscillation), 42 sets (sub oscillation) MB91F52xD 56 sets (No sub oscillation), 54 sets (sub oscillation) MB91F52xF 76 sets (No sub oscillation), 74 sets (sub oscillation) MB91F52xJ 96 sets (No sub oscillation), 94 sets (sub oscillation) MB91F52xK 120 sets (No sub oscillation), 118 sets (sub oscillation) MB91F52xL 152 sets (No sub oscillation), 150 sets (sub oscillation) Included I 2 C open drain corresponding ports:16 sets External bus interface 22-bit address, 16-bit data DMA Controller Up to 16 channels can be started simultaneously. 2 transfer factors (Internal peripheral request and software) A/D converter (successive approximation type) 12-bit resolution : Max. 48 ch (32 ch + 16 ch) Conversion time : 1.4 μs Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number: Rev. *F Revised December 5, 2017

2 D/A converter (R-2R type) 8-bit resolution : 2 ch External interrupt input: 8 channels 2 units total 16 channels Level ("H" / "L"), or edge detection (rising or falling) enabled Multi-function serial communication (built-in transmission/reception FIFO memory) : Max.12 channels 5 V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 CMOS hysteresis input < UART (Asynchronous serial interface) > Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO memory Parity or no parity is selectable. Built-in dedicated baud rate generator An external clock can be used as the transfer clock Parity, frame, and overrun error detection functions provided DMA transfer support <CSIO (Synchronous serial interface) > Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO memory SPI supported; master and slave systems supported; 5 to 16, 20, 24, 32-bit data length can be set. Built-in dedicated baud rate generator (Master operation) An external clock can be entered. (Slave operation) Overrun error detection function is provided DMA transfer support Serial chip select SPI function <LIN (Asynchronous Serial Interface for LIN) > Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO memory LIN protocol revision 2.1 supported Master and slave systems supported Framing error and overrun error detection LIN synch break generation and detection; LIN synch delimiter generation Built-in dedicated baud rate generator An external clock can be adjusted by the reload counter DMA transfer support Hard assist function < I 2 C > 2 channels ch.3, ch.4 Standard mode/fast mode supported. 6 channels ch.5 to ch.8, ch.10, ch.11 Standard mode supported. Full-duplex double buffering system, 64-step transmission FIFO memory, 64-step reception FIFO memory Standard mode (Max. 100 kbps) / fast mode (Max. 400 kbps) supported DMA transfer supported (for transmission only) CAN Controller (CAN) : 3 channels Transfer speed : Up to 1 Mbps 128-transmission/reception message buffering : 1 channel (ch.0), 64-transmission/reception message buffering : 2 channels (ch.1 and ch.2) PPG: 16-bit Max. 48 channels LED drive output 4 channels 11 ch to 14 ch Reload timer : 16-bit Max.8 channels Free-run timer : 16-bit 3 channels 32-bit Max 3 channels Input capture : 16-bit 4 channels (linked to the free-run timer) 32-bit Max 6 channels (linked to the free-run timer) Output compare : 16-bit 6 channels (linked to the free-run timer) 32-bit Max 6 channels (linked to the free-run timer) Waveform generator : 6 channels Up/Down counter 8-/16-bit Up/Down counter 2 channels Real-time clock (RTC) (for day, hours, minutes, seconds) Main or sub oscillation frequency can be selected for the operation clock Calibration: Real-time clock (RTC) of the subclock drive The main clock to sub clock ratio can be corrected by setting the real-time clock prescaler Clock Supervisor Monitoring abnormality (by damaged quartz, etc.) of suboscillation (32 khz) (dual clock products) of the outside and main oscillation (4 MHz) When abnormality is detected, it switches to the CR clock. Initial value ON/ can be selected by the part number. Base timer : Max.2 channels 16-bit timer Any of four PWM/PPG/PWC/reload timer functions can be selected and used As for the PWC function and the reload timer function, a pair of 16-bit timers can be used as one 32-bit timer in the cascade mode CRC generation Watchdog timer Hardware watchdog Software watchdog (possible to set the valid range for counter clearing) NMI (non-maskable interrupt) Interrupt controller Interrupt request batch read The interrupt existence from two or more peripherals can be read by a series of register. I/O relocation Peripheral function pins can be reassigned. Low-power consumption mode Sleep / Stop / Watch / Sub RUN mode Stop (power shutdown) / Watch (power shutdown) mode Document Number: Rev. *F Page 2 of 280

3 Power-on reset Low-voltage detection reset (independently monitor the external power supply and the internal power supply) The external power supply can select initial value ON/ by the part number. Device Package : 176/144/120/100/80/64 CMOS 90 nm Technology Power supplies 5 V Power supply The internal 1.2 V is generated from 5 V with the voltage step-down circuit Document Number: Rev. *F Page 3 of 280

4 Contents 1. Product Lineup Pin Assignment Pin Description I/O Circuit Type Handling Precautions Handling Devices Block Diagram Memory Map I/O Map Interrupt Vector Table Electrical Characteristics Example Characteristics Ordering Information MB91F52xxxB * Ordering Information MB91F52xxxC * Ordering Information MB91F52xxxD Ordering Information MB91F52xxxE Package Dimensions Errata Major Changes Document Number: Rev. *F Page 4 of 280

5 1. Product Lineup Product Lineup Comparison 64 Pins MB91F522B MB91F523B MB91F524B MB91F525B MB91F526B System Clock On chip PLL Clock multiple method Minimum instruction execution time 12.5 ns (80 MHz) Flash Capacity (Program) (256+64) KB (384+64) KB (512+64) KB (768+64) KB ( ) KB Flash Capacity (Data) 64 KB RAM Capacity (48+8) KB (64+8) KB (96+8) KB (128+8) KB External BUS I/F (22 address/16 data/4 cs) None DMA Transfer 16 ch 16-bit Base Timer None Free-run Timer 16 bit 3 ch, 32 bit 1 ch Input capture 16 bit 4 ch, 32 bit 5 ch Output Compare 16 bit 6 ch, 32 bit 4 ch 16-bit Reload Timer 7 ch PPG 16 bit 21 ch Up/down Counter 2 ch Clock Supervisor Yes External Interrupt 8 ch 2 units A/D converter 12 bit 13 ch (1 unit), 12 bit 13 ch (1 unit) D/A converter (8 bit) 1 ch Multi-Function Serial Interface 8 ch *1 CAN 64 msg 2 ch/128 msg 1 ch Hardware Watchdog Timer Yes CRC Formation Yes Low-voltage detection reset Yes Flash Security Yes ECC Flash/WorkFlash Yes ECC RAM Yes Memory Protection Function (MPU) Yes Floating point arithmetic (FPU) Yes Real Time Clock (RTC) Yes General-purpose port (#GPIOs) 44 ports SSCG Yes Sub clock Yes CR oscillator Yes OCD (On Chip Debug) Yes TPU (Timing Protection Unit) Yes Key code register Yes Waveform generator 6 ch NMI request function Yes Operation guaranteed temperature (TA) -40 C to +125 C Power supply 2.7 V to 5.5 V *2 Package LQD064 *1: Only channel 5, channel 6 and channel 11 support the I 2 C (standard mode). *2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to V). This LVD setting and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD. Document Number: Rev. *F Page 5 of 280

6 Product Lineup Comparison 80 Pins MB91F522D MB91F523D MB91F524D MB91F525D MB91F526D System Clock On chip PLL Clock multiple method Minimum instruction execution time 12.5 ns (80 MHz) Flash Capacity (Program) (256+64) KB (384+64) KB (512+64) KB (768+64) KB ( ) KB Flash Capacity (Data) 64 KB RAM Capacity (48+8) KB (64+8) KB (96+8) KB (128+8) KB External BUS I/F (22 address/16 data/4 cs) None DMA Transfer 16 ch 16-bit Base Timer 1 ch Free-run Timer 16 bit 3 ch, 32 bit 2 ch Input capture Output Compare 16-bit Reload Timer PPG Up/down Counter Clock Supervisor External Interrupt A/D converter 16 bit 4 ch, 32 bit 5 ch 16 bit 6 ch, 32 bit 4 ch 7 ch 16 bit 27 ch 2 ch Yes 8 ch 2 units 12 bit 16 ch (1 unit), 12 bit 16 ch (1 unit) D/A converter (8 bit) 1 ch Multi-Function Serial Interface 9 ch *1 CAN 64 msg 2 ch/128 msg 1 ch Hardware Watchdog Timer Yes CRC Formation Yes Low-voltage detection reset Yes Flash Security Yes ECC Flash/WorkFlash Yes ECC RAM Yes Memory Protection Function (MPU) Yes Floating point arithmetic (FPU) Yes Real Time Clock (RTC) Yes General-purpose port (#GPIOs) 56 ports SSCG Yes Sub clock Yes CR oscillator Yes NMI request function Yes OCD (On Chip Debug) Yes TPU (Timing Protection Unit) Yes Key code register Yes Waveform generator 6 ch Operation guaranteed temperature (TA) -40 C to +125 C Power supply 2.7 V to 5.5 V *2 Package LQH080 *1: Only channel 5, channel 6 and channel 11 support the I 2 C (standard mode). *2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to V). This LVD setting and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD. Document Number: Rev. *F Page 6 of 280

7 Product Lineup Comparison 100 Pins MB91F522F MB91F523F MB91F524F MB91F525F MB91F526F System Clock On chip PLL Clock multiple method Minimum instruction execution time 12.5 ns (80 MHz) Flash Capacity (Program) (256+64) KB (384+64) KB (512+64) KB (768+64) KB ( ) KB Flash Capacity (Data) 64 KB RAM Capacity (48+8) KB (64+8) KB (96+8) KB (128+8) KB External BUS I/F (22 address/16 data/4 cs) None DMA Transfer 16 ch 16-bit Base Timer 1 ch Free-run Timer 16 bit 3 ch, 32 bit 3 ch Input capture 16 bit 4 ch, 32 bit 6 ch Output Compare 16-bit Reload Timer PPG Up/down Counter Clock Supervisor External Interrupt A/D converter 16 bit 6 ch, 32 bit 6 ch 8 ch 16 bit 34 ch 2 ch Yes 8 ch 2 units 12 bit 21 ch (1 unit), 12 bit 16 ch (1 unit) D/A converter (8 bit) 2 ch Multi-Function Serial Interface 12 ch *1 CAN 64 msg 2 ch/128 msg 1 ch Hardware Watchdog Timer Yes CRC Formation Yes Low-voltage detection reset Yes Flash Security Yes ECC Flash/WorkFlash Yes ECC RAM Yes Memory Protection Function (MPU) Yes Floating point arithmetic (FPU) Yes Real Time Clock (RTC) Yes General-purpose port (#GPIOs) 76 ports SSCG Yes Sub clock Yes CR oscillator Yes NMI request function Yes OCD (On Chip Debug) Yes TPU (Timing Protection Unit) Yes Key code register Yes Waveform generator 6 ch Operation guaranteed temperature (TA) -40 C to +125 C Power supply 2.7 V to 5.5 V *2 Package LQI100 *1: Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I2C (standard mode). *2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to V). This LVD setting and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD. Document Number: Rev. *F Page 7 of 280

8 Product Lineup Comparison 120 Pins MB91F522J MB91F523J MB91F524J MB91F525J MB91F526J System Clock On chip PLL Clock multiple method Minimum instruction execution time 12.5 ns (80 MHz) Flash Capacity (Program) (256+64) KB (384+64) KB (512+64) KB (768+64) KB ( ) KB Flash Capacity (Data) 64 KB RAM Capacity (48+8) KB (64+8) KB (96+8) KB (128+8) KB External BUS I/F (22 address/16 data/4 cs) None DMA Transfer 16 ch 16-bit Base Timer 2 ch Free-run Timer 16 bit 3 ch, 32 bit 3 ch Input capture 16 bit 4 ch, 32 bit 6 ch Output Compare 16-bit Reload Timer PPG Up/down Counter Clock Supervisor External Interrupt A/D converter 16 bit 6 ch, 32 bit 6 ch 8 ch 16 bit 38 ch 2 ch Yes 8 ch 2 units 12 bit 26 ch (1 unit), 12 bit 16 ch (1 unit) D/A converter (8 bit) 2 ch Multi-Function Serial Interface 12 ch *1 CAN 64 msg 2 ch/128 msg 1 ch Hardware Watchdog Timer Yes CRC Formation Yes Low-voltage detection reset Yes Flash Security Yes ECC Flash/WorkFlash Yes ECC RAM Yes Memory Protection Function (MPU) Yes Floating point arithmetic (FPU) Yes Real Time Clock (RTC) Yes General-purpose port (#GPIOs) 96 ports SSCG Yes Sub clock Yes CR oscillator Yes NMI request function Yes OCD (On Chip Debug) Yes TPU (Timing Protection Unit) Yes Key code register Yes Waveform generator 6 ch Operation guaranteed temperature (TA) -40 C to +125 C Power supply 2.7 V to 5.5 V *2 Package LQM120 *1: Only channel 3 and channel 4 support the I 2 C (fast mode/standard mode). Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I 2 C (standard mode). *2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to V). This LVD setting and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD. Document Number: Rev. *F Page 8 of 280

9 Product Lineup Comparison 144 Pins MB91F522K MB91F523K MB91F524K MB91F525K MB91F526K System Clock On chip PLL Clock multiple method Minimum instruction execution time 12.5 ns (80 MHz) Flash Capacity (Program) (256+64) KB (384+64) KB (512+64) KB (768+64) KB ( ) KB Flash Capacity (Data) 64 KB RAM Capacity (48+8) KB (64+8) KB (96+8) KB (128+8) KB External BUS I/F (22 address/16 data/4 cs) Yes DMA Transfer 16 ch 16-bit Base Timer 2 ch Free-run Timer 16 bit 3 ch, 32 bit 3 ch Input capture 16 bit 4 ch, 32 bit 6 ch Output Compare 16-bit Reload Timer PPG Up/down Counter Clock Supervisor External Interrupt A/D converter 16 bit 6 ch, 32 bit 6 ch 8 ch 16 bit 44 ch 2 ch Yes 8 ch 2 units 12 bit 32 ch (1 unit), 12 bit 16 ch (1 unit) D/A converter (8 bit) 2 ch Multi-Function Serial Interface 12 ch *1 CAN 64 msg 2 ch/128 msg 1 ch Hardware Watchdog Timer Yes CRC Formation Yes Low-voltage detection reset Yes Flash Security Yes ECC Flash/WorkFlash Yes ECC RAM Yes Memory Protection Function (MPU) Yes Floating point arithmetic (FPU) Yes Real Time Clock (RTC) Yes General-purpose port (#GPIOs) 120 ports SSCG Yes Sub clock Yes CR oscillator Yes NMI request function Yes OCD (On Chip Debug) Yes TPU (Timing Protection Unit) Yes Key code register Yes Waveform generator 6 ch Operation guaranteed temperature (TA) -40 C to +125 C Power supply 2.7 V to 5.5 V *2 Package LQS144, LQN144 *1: Only channel 3 and channel 4 support the I 2 C (fast mode/standard mode). Only channel 5, channel 6, channel 7, channel 8, channel 10 and channel 11 support the I 2 C (standard mode). *2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to V). This LVD setting and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD. Document Number: Rev. *F Page 9 of 280

10 Product Lineup Comparison 176 Pins MB91F522L MB91F523L MB91F524L MB91F525L MB91F526L System Clock On chip PLL Clock multiple method Minimum instruction execution time 12.5 ns (80 MHz) Flash Capacity (Program) (256+64) KB (384+64) KB (512+64) KB (768+64) KB ( ) KB Flash Capacity (Data) 64 KB RAM Capacity (48+8) KB (64+8) KB (96+8) KB (128+8) KB External BUS I/F (22 address/16 data/4 cs) Yes DMA Transfer 16 ch 16-bit Base Timer 2 ch Free-run Timer 16 bit 3 ch, 32 bit 3 ch Input capture 16 bit 4 ch, 32 bit 6 ch Output Compare 16 bit 6 ch, 32 bit 6 ch 16-bit Reload Timer 8 ch PPG 16 bit 48 ch Up/down Counter 2 ch Clock Supervisor Yes External Interrupt 8 ch 2 units A/D converter 12 bit 32 ch (1 unit), 12 bit 16 ch (1 unit) D/A converter (8 bit) 2 ch Multi-Function Serial Interface 12 ch *1 CAN 64 msg 2 ch/128 msg 1 ch Hardware Watchdog Timer Yes CRC Formation Yes Low-voltage detection reset Yes Flash Security Yes ECC Flash/WorkFlash Yes ECC RAM Yes Memory Protection Function (MPU) Yes Floating point arithmetic (FPU) Yes Real Time Clock (RTC) Yes General-purpose port (#GPIOs) 152 ports SSCG Yes Sub clock Yes CR oscillator Yes NMI request function Yes OCD (On Chip Debug) Yes TPU (Timing Protection Unit) Yes Key code register Yes Waveform generator 6 ch Operation guaranteed temperature (TA) -40 C to +125 C Power supply 2.7 V to 5.5 V *2 Package LQP176 *1: Only channel 3 and channel 4 support the I 2 C (fast mode/standard mode). Only channel 5, channel 6, channel 7, channel 8, channel 10 and channel 11 support the I 2 C (standard mode). *2: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to V). This LVD setting and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD. Document Number: Rev. *F Page 10 of 280

11 Table for Clock Supervisor and External Low Voltage Detection Reset Initial Value ON/ Clock CSV Initial Value LVD Initial Value Function single Dual ON ON MB91F52X Revision:B, C, D, E Function:See the table for clock supervisor and external low voltage detection reset initial value ON/. PKG Type:B 64pin D 80 pin F 100 pin J 120 pin K 144 pin L 176 pin Memory Size:2 256KB 3 384KB 4 512KB 5 768KB 6 1MB ON ON ON ON S U H K W Y J L Document Number: Rev. *F Page 11 of 280

12 2. Pin Assignment MB91F52xB MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B (TOP VIEW) VCC P011/WOT/INT3_1 P006/ADTG1_1/INT2_1/TX2(64) P005/ADTG0_1/INT7_1/RX2(64) C VSS RSTX X0A/P136 X1A/P135/DTTI_0 VSS X1 X0 MD1 MD0 P126/SIN0_0/INT6_0 DEBUGIF VSS 1 48 P122/SIN6_0/AN31/OCU8_0/INT9_1 P020/SIN3_1/TRG3_0/TIN0_2/RTO5_ P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0 TOP VIEW P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_ P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1 P027/SCS40_1/PPG27_0/TOT0_0/RTO3_ P110/TX1(64)/SCS63_0/AN22 P032/SCS43_1/PPG30_0/TOT3_0/RTO2_ NMIX MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_ P105/AN17/PPG13_0 P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_ P104/AN16/PPG12_0 P151/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_ P103/AN15/PPG11_0 P035/OCU8_1/TOT4_0/AIN0_0/INT11_ P102/AN14/PPG10_0/INT10_0 P036/OCU7_1/TOT5_0/BIN0_ AVCC0 P040/PPG23_1/TOT7_0/AIN1_0/SIN0_ AVRH0 P041/SIN9_0/ICU9_1/BIN1_0/INT12_ AVSS0/AVRL0 P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_ P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1 LQD064 LQFP-64 P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_ P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0 P047/AN45/TRG8_0/TIN3_2/SOT0_ P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0 P053/AN44/PPG35_0/INT14_1/SCK0_ VSS VCC P087/DAO0/PPG7_0/INT8_0 P082/SIN5_0/AN1/PPG2_0 P081/SOT5_0/SDA5/AN0/PPG1_0 P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1 P072/SIN4_0/AN34/ICU2_2/INT5_0 P071/SCK4_2/AN35/ICU1_2/MONCLK P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1 P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1 P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1 P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1 AVSS1/AVRL1 AVRH1 P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1 AVCC1 P055/SIN10_0/AN43/PPG37_0/TIN4_1 * In a single clock product, pin 56 and pin 57 are the general-purpose ports. Document Number: Rev. *F Page 12 of 280

13 VCC P011/WOT/SOT2_1/INT3_1 P006/SCS2_0/ADTG1_1/INT2_1/TX2(64) P005/SCK2_0/ADTG0_1/INT7_1/RX2(64) P003/SIN2_0/TIOB1_1/INT3_0 P001/TIOA1_1 C VSS RSTX X0A/P136 X1A/P135/DTTI_0 VSS X1 X0 MD1 MD0 P127/SOT0_0 P126/SIN0_0/INT6_0 DEBUGIF VCC MB91520 Series MB91F52xD MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D (TOP VIEW) VSS 1 60 VSS P020/SIN3_1/TRG3_0/TIN0_2/RTO5_ P122/SIN6_0/AN31/OCU8_0/INT9_1 P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_ P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0 TOP VIEW P026/SCK4_1/PPG26_0/TIN3_ P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1 P027/SCS40_1/PPG27_0/TOT0_0/RTO3_ P114/SCS61_0/AN26/PPG18_0/RTO2_0 P031/SCS42_1/PPG29_ P110/TX1(64)/SCS63_0/AN22 MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D P032/SCS43_1/PPG30_0/TOT3_0/RTO2_ NMIX P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_ P107/AN19/PPG15_0 P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_ P105/AN17/PPG13_0 P151/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_ P104/AN16/PPG12_0 P035/OCU8_1/TOT4_0/AIN0_0/INT11_ P103/AN15/PPG11_0 P036/OCU7_1/TOT5_0/BIN0_ P102/AN14/PPG10_0/INT10_0 P040/PPG23_1/TOT7_0/AIN1_0/SIN0_ P100/AN12/PPG8_0 P041/SIN9_0/ICU9_1/BIN1_0/INT12_ AVCC0 P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_ AVRH0 P044/SCS9_0/ICU6_1/TRG2_ AVSS0/AVRL0 LQFP-80 LQH080 P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_ P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1 P047/AN45/TRG8_0/TIN3_2/SOT0_ P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0 P053/AN44/PPG35_0/INT14_1/SCK0_ P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0 VCC VSS VCC P087/DAO0/PPG7_0/INT8_0 P082/SIN5_0/AN1/PPG2_0 P081/SOT5_0/SDA5/AN0/PPG1_0 P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1 P073/AN33/ICU3_2 P072/SIN4_0/AN34/ICU2_2/INT5_0 P071/SCK4_2/AN35/ICU1_2/MONCLK P067/AN36/FRCK5_0/AIN0_1 P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1 P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1 P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1 P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1 P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1 AVSS1/AVRL1 AVRH1 P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1 AVCC1 P055/SIN10_0/AN43/PPG37_0/TIN4_1 VSS * In a single clock product, pin 70 and pin 71 are the general-purpose ports. Document Number: Rev. *F Page 13 of 280

14 MB91F52xF MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F (TOP VIEW) VCC P011/WOT/SOT2_1/INT3_1 P006/SCS2_0/ADTG1_1/INT2_1 P005/SCK2_0/ADTG0_1/INT7_1 P003/SIN2_0/TIOB1_1/INT3_0 P001/SOT1_0/TIOA1_1 P000/SIN1_0/INT2_0 C VSS P144/SCK1_1 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0 P133/TX2(64) RSTX X0A/P136 X1A/P135/DTTI_0 VSS X1 X0 MD1 MD0 P130/SCK0_0 P127/SOT0_0 P126/SIN0_0/INT6_0 DEBUGIF VCC VSS 1 75 VSS P020/SIN3_1/TRG3_0/TIN0_2/RTO5_ P122/SIN6_0/AN31/OCU8_0/INT9_1 P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_ P117/SCS60_0/AN29/PPG21_0/RTO5_0 P025/SOT4_1/PPG25_0/TIN2_ P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0 TOP VIEW P026/SCK4_1/PPG26_0/TIN3_ P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1 P027/SCS40_1/PPG27_0/TOT0_0/RTO3_ P114/SCS61_0/AN26/PPG18_0/RTO2_0 P030/SCS41_1/PPG28_0/TOT1_ P111/RX1(64)/SCS62_0/AN23/INT1_0 P031/SCS42_1/PPG29_0/TOT2_ P110/TX1(64)/SCS63_0/AN22 MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F P032/SCS43_1/PPG30_0/TOT3_0/RTO2_ NMIX P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_ P107/AN19/PPG15_0 P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_ P106/SCS70_0/AN18/PPG14_0 P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_ P105/SCS71_0/AN17/PPG13_0 P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_ P104/SCS72_0/AN16/PPG12_0 P035/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_ P103/SCS73_0/AN15/PPG11_0 P036/SCS8_0/OCU7_1/TOT5_0/BIN0_ P102/SIN7_0/AN14/PPG10_0/INT10_0 P037/OCU6_1/TOT6_0/ZIN0_ P101/SOT7_0/SDA7/AN13/PPG9_0 P040/PPG23_1/TOT7_0/AIN1_0/SIN0_ P100/SCK7_0/SCL7/AN12/PPG8_0 P041/SIN9_0/ICU9_1/BIN1_0/INT12_ AVCC0 P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_ AVRH0 P043/ICU7_1/TRG1_ AVSS0/AVRL0 LQFP-100 LQI100 P044/SCS9_0/ICU6_1/TRG2_ P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1 P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_ P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0 P047/AN45/TRG8_0/TIN3_2/SOT0_ P095/TX0(128)/SCS11_0/AN9 P053/AN44/PPG35_0/INT14_1/SCK0_ P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1 VCC VSS 50 VCC 49 P087/DAO0/PPG7_0/INT8_0 48 P086/DAO1/PPG6_0 47 P082/SIN5_0/AN1/PPG2_0 46 P081/SOT5_0/SDA5/AN0/PPG1_0 45 P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1 44 P152/SCS53_0 43 P073/AN33/ICU3_2 42 P072/SIN4_0/AN34/ICU2_2/INT5_0 41 P071/SCK4_2/AN35/ICU1_2/MONCLK 40 P070/ICU0_2 39 P067/AN36/FRCK5_0/AIN0_1 38 P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1 37 P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1 36 P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1 35 P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1 34 P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1 33 P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1 32 P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0 31 AVSS1/AVRL1 30 AVRH1 29 P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1 28 AVCC1 27 P055/SIN10_0/AN43/PPG37_0/TIN4_1 26 VSS * In a single clock product, pin 86 and pin 87 are the general-purpose ports. Document Number: Rev. *F Page 14 of 280

15 VCC P011/WOT/SOT2_1/TIOA0_0/INT3_1 P010 P007 P006/SCS2_0/ADTG1_1/INT2_1 P005/SCK2_0/ADTG0_1/INT7_1 P003/SIN2_0/TIOB1_1/INT3_0 P002/SCK1_0/TIOB0_1 P001/SOT1_0/TIOA1_1 P000/SIN1_0/TIOA0_1/INT2_0 C VSS P144/SCK1_1 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0 P133/TX2(64) P132/SCS1_0/ADTG1_0 RSTX X0A/P136 X1A/P135/DTTI_0 VSS X1 X0 MD1 MD0 P130/SCK0_0 P127/SOT0_0 P126/SIN0_0/INT6_0 P125/OCU11_0 DEBUGIF VCC VCC P087/DAO0/PPG7_0/INT8_0 P086/DAO1/PPG6_0 P082/SIN5_0/AN1/PPG2_0 P081/SOT5_0/SDA5/AN0/PPG1_0 P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1 P152/SCS53_0 P077/SCK3_0/SCL3 P076/SOT3_0/SDA3 P075/SIN3_0/INT4_0 P074/SCK4_0/SCL4 P073/SOT4_0/SDA4/AN33/ICU3_2 P072/SIN4_0/AN34/ICU2_2/INT5_0 P071/SCK4_2/AN35/ICU1_2/MONCLK P070/ICU0_2 P067/AN36/FRCK5_0/AIN0_1 P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1 P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1 P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1 P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1 P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1 P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1 P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0 AVSS1/AVRL1 AVRH1 P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1 AVCC1 P056/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2 P055/SIN10_0/AN43/PPG37_0/TIN4_1 VSS MB91520 Series MB91F52xJ MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J (TOP VIEW) VSS 1 90 VSS P020/SIN3_1/TRG3_0/TIN0_2/RTO5_ P122/SIN6_0/AN31/OCU8_0/INT9_1 P021/SOT3_1/TRG6_1/TRG4_ P120/AN30/OCU6_0/PPG22_0/INT9_0 P022/SCK3_1/TRG7_1/TRG5_ P117/SCS60_0/AN29/PPG21_0/RTO5_0 P023/SCS3_1/PPG32_0/TIN0_ P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0 P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_ P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1 TOP VIEW P025/SOT4_1/PPG25_0/TIN2_ P114/SCS61_0/AN26/PPG18_0/RTO2_0 P026/SCK4_1/PPG26_0/TIN3_ P113/AN25/PPG17_0/RTO1_0 P027/SCS40_1/PPG27_0/TOT0_0/RTO3_ P112/AN24/PPG16_0/RTO0_0 P030/SCS41_1/PPG28_0/TOT1_ P111/RX1(64)/SCS62_0/AN23/INT1_0 MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J P031/SCS42_1/PPG29_0/TOT2_ P110/TX1(64)/SCS63_0/AN22 P032/SCS43_1/PPG30_0/TOT3_0/RTO2_ NMIX P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_ P155/AN21 P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_ P154/AN20 P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_ P107/AN19/PPG15_0 P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_ P106/SCS70_0/AN18/PPG14_0 P035/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_ P105/SCS71_0/AN17/PPG13_0 P036/SCS8_0/OCU7_1/TOT5_0/BIN0_ P104/SCS72_0/AN16/PPG12_0 P037/OCU6_1/TOT6_0/ZIN0_ P103/SCS73_0/AN15/PPG11_0 P040/PPG23_1/TOT7_0/AIN1_0/SIN0_ P102/SIN7_0/AN14/PPG10_0/INT10_0 P041/SIN9_0/ICU9_1/BIN1_0/INT12_ P101/SOT7_0/SDA7/AN13/PPG9_0 P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_ P100/SCK7_0/SCL7/AN12/PPG8_0 LQFP-120 LQM120 P043/ICU7_1/TRG1_ AVCC0 P044/SCS9_0/ICU6_1/TRG2_ AVRH0 P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_ AVSS0/AVRL0 P046/ICU4_1/TRG4_ P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1 P047/AN45/TRG8_0/TIN3_2/SOT0_ P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0 P050/TRG5_1/PPG33_ P095/TX0(128)/SCS11_0/AN9 P053/AN44/PPG35_0/INT14_1/SCK0_ P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1 VCC VSS * In a single clock product, pin 102 and pin 103 are the general-purpose ports. Document Number: Rev. *F Page 15 of 280

16 144 VCC VCC P087/DAO0/PPG7_0/INT8_0 P086/DAO1/PPG6_0 P085/PPG5_0 P084/SCS51_0/AN3/PPG4_0 P083/SCS50_0/AN2/PPG3_0 P082/SIN5_0/AN1/PPG2_0 P081/SOT5_0/SDA5/AN0/PPG1_0 P080/SCS52_0/PPG0_0 P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1 P152/SCS53_0 P077/SCK3_0/SCL3 P076/SOT3_0/SDA3 P075/SIN3_0/INT4_0 P074/SCK4_0/SCL4 P073/SOT4_0/SDA4/AN33/ICU3_2 P072/SIN4_0/AN34/ICU2_2/INT5_0 P071/SCK4_2/AN35/ICU1_2/MONCLK P070/ICU0_2 P067/AN36/FRCK5_0/AIN0_1 P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1 P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1 P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1 P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1 P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1 P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1 P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0 P143/SOT10_0/SDA10/PPG39_0/TOT4_1 P142/SCK10_0/SCL10/PPG38_0/TIN7_1 AVSS1/AVRL1 AVRH1 P057/RDY/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1 AVCC1 P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2 P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1 VSS P014/D28/TIOB1_0 P013/D27/TIOA1_0 P012/D26/TIOB0_0 P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1 P010/D24 P007/D23 P006/D22/SCS2_0/ADTG1_1/INT2_1 P005/D21/SCK2_0/ADTG0_1/INT7_1 P004/D20/SOT2_0 P003/D19/SIN2_0/TIOB1_1/INT3_0 P002/D18/SCK1_0/TIOB0_1 P001/D17/SOT1_0/TIOA1_1 P000/D16/SIN1_0/TIOA0_1/INT2_0 C VSS P144/SCK1_1 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0 P133/TX2(64) P132/SCS1_0/ADTG1_0 P131/ADTG0_0 RSTX X0A/P136 X1A/P135/DTTI_0 VSS X1 X0 MD1 MD0 P130/SCK0_0 P127/SOT0_0 P126/SIN0_0/INT6_0 P125/OCU11_0 P124/OCU10_0 DEBUGIF VCC MB91520 Series MB91F52xK MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K (TOP VIEW) VSS VSS P015/D29/TRG0_ P123/OCU9_0 P016/D30/TRG1_ P122/SIN6_0/AN31/OCU8_0/INT9_1 P017/D31/TRG2_ P121/OCU7_0/PPG23_0 P020/ASX/SIN3_1/TRG3_0/TIN0_2/RTO5_ P120/AN30/OCU6_0/PPG22_0/INT9_0 P021/CS0X/SOT3_1/TRG6_1/TRG4_ P117/SCS60_0/AN29/PPG21_0/RTO5_0 P022/CS1X/SCK3_1/TRG7_1/TRG5_ P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0 P023/RDX/SCS3_1/PPG32_0/TIN0_ P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1 P024/WR0X/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_ P114/SCS61_0/AN26/PPG18_0/RTO2_0 TOP VIEW P025/WR1X/SOT4_1/PPG25_0/TIN2_ P113/AN25/PPG17_0/RTO1_0 P026/A00/SCK4_1/PPG26_0/TIN3_ P112/AN24/PPG16_0/RTO0_0 P027/A01/SCS40_1/PPG27_0/TOT0_0/RTO3_ P111/RX1(64)/SCS62_0/AN23/INT1_0 P030/A02/SCS41_1/PPG28_0/TOT1_ P110/TX1(64)/SCS63_0/AN22 MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K P031/A03/SCS42_1/PPG29_0/TOT2_ NMIX P032/A04/SCS43_1/PPG30_0/TOT3_0/RTO2_ P155/AN21 P033/A05/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_ P154/AN20 P034/A06/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_ P107/AN19/PPG15_0 P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_ P106/SCS70_0/AN18/PPG14_0 P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_ P105/SCS71_0/AN17/PPG13_0 P035/A07/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_ P104/SCS72_0/AN16/PPG12_0 P036/A08/SCS8_0/OCU7_1/TOT5_0/BIN0_ P103/SCS73_0/AN15/PPG11_0 P037/A09/OCU6_1/TOT6_0/ZIN0_ P102/SIN7_0/AN14/PPG10_0/INT10_0 P040/A10/PPG23_1/TOT7_0/AIN1_0/SIN0_ P101/SOT7_0/SDA7/AN13/PPG9_0 P041/A11/SIN9_0/ICU9_1/BIN1_0/INT12_ P100/SCK7_0/SCL7/AN12/PPG8_0 P042/A12/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_ AVCC0 LQS144/LQN144 LQFP-144 P043/A13/ICU7_1/TRG1_ AVRH0 P044/A14/SCS9_0/ICU6_1/TRG2_ AVSS0/AVRL0 P045/A15/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_ P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1 P046/A16/ICU4_1/TRG4_ P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0 P047/A17/AN45/TRG8_0/TIN3_2/SOT0_ P095/TX0(128)/SCS11_0/AN9 P050/A18/TRG5_1/PPG33_ P094/AN8/ICU4_0/TOT3_1 P051/A19/TRG9_ P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1 P052/A20/PPG34_0/INT14_ P092/AN6/PPG40_1/ICU2_0/TOT0_1 P053/A21/AN44/PPG35_0/INT14_1/SCK0_ P091/AN5/PPG41_1/ICU1_0/TIN3_1 P054/SYSCLK/PPG36_ P090/AN4/ICU0_0/TIN2_1 VCC VSS * In a single clock product, pin 121 and pin 122 are the general-purpose ports. Document Number: Rev. *F Page 16 of 280

17 176 VCC VCC P087/DAO0/PPG7_0/INT8_0 P086/DAO1/PPG6_0 P085/PPG5_0 P084/SCS51_0/AN3/PPG4_0 P083/SCS50_0/AN2/PPG3_0 P082/SIN5_0/AN1/PPG2_0 P081/SOT5_0/SDA5/AN0/PPG1_0 P080/SCS52_0/PPG0_0 P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1 P152/SCS53_0 P077/SCK3_0/SCL3 P076/SOT3_0/SDA3 P075/SIN3_0/INT4_0 P074/SCK4_0/SCL4 P187/PPG47_0 P186/PPG46_0 P073/SOT4_0/SDA4/AN33/ICU3_2 P072/SIN4_0/AN34/ICU2_2/INT5_0 P071/SCK4_2/AN35/ICU1_2/MONCLK P070/ICU0_2 P067/AN36/FRCK5_0/AIN0_1 P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1 P185/PPG45_0 P184/PPG44_0 P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1 P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1 P183/PPG43_0 P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1 P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1 P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1 P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0 P182/PPG42_0 P143/SOT10_0/SDA10/PPG39_0/TOT4_1 P142/SCK10_0/SCL10/PPG38_0/TIN7_1 AVSS1/AVRL1 AVRH1 P057/RDY/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1 AVCC1 P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2 P181/PPG41_0 P180/PPG40_0 P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1 VSS P014/D28/TIOB1_0 P013/D27/TIOA1_0 P167/PPG35_1 P012/D26/TIOB0_0 P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1 P010/D24 P166/PPG34_1 P007/D23 P006/D22/SCS2_0/ADTG1_1/INT2_1 P165/PPG33_1 P005/D21/SCK2_0/ADTG0_1/INT7_1 P164/PPG32_1 P004/D20/SOT2_0 P003/D19/SIN2_0/TIOB1_1/INT3_0 P002/D18/SCK1_0/TIOB0_1 P001/D17/SOT1_0/TIOA1_1 P000/D16/SIN1_0/TIOA0_1/INT2_0 C VSS P144/SCK1_1 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0 P133/TX2(64) P132/SCS1_0/ADTG1_0 P131/ADTG0_0 RSTX X0A/P136 X1A/P135/DTTI_0 VSS X1 X0 MD1 MD0 P163/TRG6_2 P162/TRG5_2 P130/SCK0_0 P127/SOT0_0 P126/SIN0_0/INT6_0 P125/OCU11_0 P124/OCU10_0 P161/PPG31_1 P160/PPG30_1 DEBUGIF VCC MB91520 Series MB91F52xL MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L (TOP VIEW) VSS VSS P015/D29/TRG0_ P123/OCU9_0 P016/D30/TRG1_ P197/PPG29_1 P170/PPG36_ P122/SIN6_0/AN31/OCU8_0/INT9_1 P017/D31/TRG2_ P121/OCU7_0/PPG23_0 P171/PPG37_ P120/AN30/OCU6_0/PPG22_0/INT9_0 P020/ASX/SIN3_1/TRG3_0/TIN0_2/RTO5_ P196/FRCK3_1/PPG28_1 P021/CS0X/SOT3_1/TRG6_1/TRG4_ P117/SCS60_0/AN29/PPG21_0/RTO5_0 P022/CS1X/SCK3_1/TRG7_1/TRG5_ P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0 P023/RDX/SCS3_1/PPG32_0/TIN0_ P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1 P024/WR0X/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_ P114/SCS61_0/AN26/PPG18_0/RTO2_0 P025/WR1X/SOT4_1/PPG25_0/TIN2_ P195/FRCK4_1/PPG27_1 P172/PPG38_ P194/FRCK5_1/PPG26_1 TOP VIEW P026/A00/SCK4_1/PPG26_0/TIN3_ P113/AN25/PPG17_0/RTO1_0 P027/A01/SCS40_1/PPG27_0/TOT0_0/RTO3_ P112/AN24/PPG16_0/RTO0_0 P173/PPG39_ P111/RX1(64)/SCS62_0/AN23/INT1_0 P030/A02/SCS41_1/PPG28_0/TOT1_ P110/TX1(64)/SCS63_0/AN22 MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L P031/A03/SCS42_1/PPG29_0/TOT2_ NMIX P032/A04/SCS43_1/PPG30_0/TOT3_0/RTO2_ P155/AN21 P033/A05/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_ P154/AN20 P034/A06/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_ P193/PPG25_1 P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_ P107/AN19/PPG15_0 P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_ P106/SCS70_0/AN18/PPG14_0 P035/A07/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_ P105/SCS71_0/AN17/PPG13_0 P036/A08/SCS8_0/OCU7_1/TOT5_0/BIN0_ P104/SCS72_0/AN16/PPG12_0 P037/A09/OCU6_1/TOT6_0/ZIN0_ P103/SCS73_0/AN15/PPG11_0 P174/TRG8_ P102/SIN7_0/AN14/PPG10_0/INT10_0 P175/TRG9_ P101/SOT7_0/SDA7/AN13/PPG9_0 P040/A10/PPG23_1/TOT7_0/AIN1_0/SIN0_ P100/SCK7_0/SCL7/AN12/PPG8_0 LQP176 LQFP-176 P041/A11/SIN9_0/ICU9_1/BIN1_0/INT12_ AVCC0 P042/A12/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_ AVRH0 P043/A13/ICU7_1/TRG1_ AVSS0/AVRL0 P044/A14/SCS9_0/ICU6_1/TRG2_ P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1 P045/A15/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_ P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0 P046/A16/ICU4_1/TRG4_ P095/TX0(128)/SCS11_0/AN9 P176/TRG10_ P094/AN8/ICU4_0/TOT3_1 P047/A17/AN45/TRG8_0/TIN3_2/SOT0_ P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0/TOT2_1 P177/TRG11_ P192/PPG24_1/TOT1_1 P050/A18/TRG5_1/PPG33_ P092/AN6/PPG40_1/ICU2_0/TOT0_1 P051/A19/TRG9_ P091/AN5/PPG41_1/ICU1_0/TIN3_1 P052/A20/PPG34_0/INT14_ P090/AN4/ICU0_0/TIN2_1 P053/A21/AN44/PPG35_0/INT14_1/SCK0_ P191/TIN1_1 P054/SYSCLK/PPG36_ P190/TIN0_1 VCC VSS * In a single clock product, pin 149 and pin 150 are the general-purpose ports. Document Number: Rev. *F Page 17 of 280

18 3. Pin Description Pin No *1 2 *1 2 *1 2 * * * * Pin Name Polarity P015 - I/O Circuit types* 8 Function* 9 D29 - A External bus data bit29 I/O (0) TRG0_0 - PPG trigger 0 input (0) P016 - D30 - A External bus data bit30 I/O (0) TRG1_0 - PPG trigger 1 input (0) P170 - A PPG36_1 - PPG ch.36 output (1) P017 - D31 - A External bus data bit31 I/O (0) TRG2_0 - PPG trigger 2 input (0) P171 - A PPG37_1 - PPG ch.37 output (1) P020 - ASX *2, *3, *4, *5 - External bus/address strobe output SIN3_1 - Multi-function serial ch.3 serial data input (1) F TRG3_0 - PPG trigger 3 input (0) TIN0_2 - Reload timer ch.0 event input (2) RTO5_1 - Waveform generator ch.5 output pin (1) P021 - A CS0X *5 - External bus chip select 0 output SOT3_1 - Multi-function serial ch.3 serial data output (1) TRG6_1 - PPG trigger 6 input (1) TRG4_0 - PPG trigger 4 input (0) P022 - CS1X *5 - External bus chip select 1 output SCK3_1 - F Multi-function serial ch.3 clock I/O (1) TRG7_1 - PPG trigger 7 input (1) TRG5_0 - PPG trigger 5 input (0) P023 - RDX *5 - External bus/read strobe output SCS3_1 - A Serial chip select 3 output (1) PPG32_0 - PPG ch.32 output (0) TIN0_0 - Reload timer ch.0 event input (0) Document Number: Rev. *F Page 18 of 280

19 Pin No *1 3 *1 3 *1 6 * *1 7 * *1 5 *1 8 * *1 5 *1 6 *1 9 * *1 10 * *1 8 *1 11 * Pin Name Polarity P024 - I/O Circuit types* 8 PPG24_0 - F PPG ch.24 output (0) Function* 9 WR0X *2, *3, *4, *5 - External bus/write strobe 0 output SIN4_1 - Multi-function serial ch.4 serial data input (1) TIN1_0 - Reload timer ch.1 event input (0) RTO4_1 - Waveform generator ch.4 output pin (1) INT15_0 - INT15 External interrupt input (0) P025 - A WR1X *4, *5 - External bus/write strobe 1 output SOT4_1 - Multi-function serial ch.4 serial data output (1) PPG25_0 - PPG ch.25 output (0) TIN2_0 - Reload timer ch.2 event input (0) P172 - A PPG38_1 - PPG ch.38 output (1) P026 - A00 *3, *4, *5 - External bus/address bit0 output (0) SCK4_1 - F Multi-function serial ch.4 clock I/O (1) PPG26_0 - PPG ch.26 output (0) TIN3_0 - Reload timer ch.3 event input (0) P027 - A01 *2, *3, *4, *5 - External bus/address bit1 output (0) SCS40_1 - Serial chip select 40 I/O (1) A PPG27_0 - PPG ch.27 output (0) TOT0_0 - Reload timer ch.0 output (0) RTO3_1 - Waveform generator ch.3 output pin (1) P173 - A PPG39_1 - PPG ch.39 output (1) P030 - A02 *4, *5 - External bus/address bit2 output (0) SCS41_1 - A Serial chip select 41 output (1) PPG28_0 - PPG ch.28 output (0) TOT1_0 - Reload timer ch.1 output (0) P031 - A03 *3, *4, *5 - External bus/address bit3 output (0) SCS42_1 - A Serial chip select 42 output (1) PPG29_0 - PPG ch.29 output (0) TOT2_0 *3 - Reload timer ch.2 output (0) Document Number: Rev. *F Page 19 of 280

20 Pin No *1 7 *1 9 *1 12 * *1 8 *1 10 *1 13 * *1 9 *1 11 *1 14 * *1 10 * Pin Name Polarity P032 - I/O Circuit types* 8 Function* 9 A04 *2, *3, *4, *5 - External bus/address bit4 output (0) SCS43_1 - Serial chip select 43 output (1) A PPG30_0 - PPG ch.30 output (0) TOT3_0 - Reload timer ch.3 output (0) RTO2_1 - Waveform generator ch.2 output pin (1) P033 - A05 *2, *3, *4, *5 - External bus/address bit5 output (0) PPG31_0 - PPG ch.31 output (0) ICU3_3 - A Input capture ch.3 input (3) TIN4_0 - Reload timer ch.4 event input (0) RTO1_1 - Waveform generator ch.1 output pin (1) SCK3_2 - Multi-function serial ch.3 clock I/O (2) P034 - A06 *2, *3, *4, *5 - External bus/address bit6 output (0) OCU11_1 - Output compare ch.11 output (1) ICU2_3 - Input capture ch.2 input (3) A TIN5_0 - Reload timer ch.5 event input (0) RTO0_1 - Waveform generator ch.0 output pin (1) SOT3_2 - P150 - SOT8_0/ SDA8 - Multi-function serial ch.3 serial data output (2) Multi-function serial ch.8 serial data output (0)/ I 2 C bus serial data I/O OCU10_1 - F Output compare ch.10 output (1) TRG6_0 - PPG trigger 6 input (0) ICU1_3 - Input capture ch.1 input (3) TIN6_0 - Reload timer ch.6 event input (0) P151 - SCK8_0/ SCL8 *2, *3 - Multi-function serial ch.8 clock I/O (0)/ I 2 C bus serial clock I/O OCU9_1 - Output compare ch.9 output (1) TRG7_0 - F PPG trigger 7 input (0) ICU0_3 - Input capture ch.0 input (3) TIN7_0 - Reload timer ch.7 event input (0) ZIN0_2 - U/D counter ch.0 ZIN input (2) DTTI_1 - Waveform generator ch.1 input pin (1) Document Number: Rev. *F Page 20 of 280

21 Pin No *1 10 *1 11 *1 12 *1 14 *1 17 * *1 18 * *1 19 * *1 12 *1 13 *1 13 *1 14 *1 15 *1 17 *1 20 * *1 21 * *1 22 * Pin Name Polarity P035 - I/O Circuit types* 8 Function* 9 A07 *2, *3, *4, *5 - External bus/address bit7 output SIN8_0 *2, *3 - Multi-function serial ch.8 serial data input (0) OCU8_1 - I Output compare ch.8 output (1) TOT4_0 - Reload timer ch.4 output (0) AIN0_0 - U/D counter ch.0 AIN input (0) INT11_0 - INT11 External interrupt input (0) P036 - A08 *2, *3, *4, *5 - External bus/address bit8 output (0) SCS8_0 *2, *3 - Serial chip select 8 I/O (0) A OCU7_1 - Output compare ch.7 output (1) TOT5_0 - Reload timer ch.5 output (0) BIN0_0 - U/D counter ch.0 BIN input (0) P037 - A09 *4, *5 - External bus/address bit9 output (0) OCU6_1 - A Output compare ch.6 output (1) TOT6_0 - Reload timer ch.6 output (0) ZIN0_0 - U/D counter ch.0 ZIN input (0) P174 - A TRG8_1 - PPG trigger 8 input (1) P175 - A TRG9_1 - PPG trigger 9 input (1) P040 - A10 *2, *3, *4, *5 - External bus/address bit10 output (0) PPG23_1 - PPG ch.23 output (1) A TOT7_0 - Reload timer ch.7 output (0) AIN1_0 - U/D counter ch.1 AIN input (0) SIN0_1 - Multi-function serial ch.0 serial data input (1) P041 - A11 *2, *3, *4, *5 - External bus/address bit11 output (0) SIN9_0 - Multi-function serial ch.9 serial data input (0) I ICU9_1 - Input capture ch.9 input (1) BIN1_0 - U/D counter ch.1 BIN input (0) INT12_0 - INT12 External interrupt input (0) P042 - A12 *2, *3, *4, *5 - External bus/address bit12 output Multi-function serial ch.9 serial data output SOT9_0 - (0) B AN47 - ADC analog 47 input ICU8_1 - Input capture ch.8 input (1) TRG0_1 - PPG trigger 0 input (1) ZIN1_0 - U/D counter ch.1 ZIN input (0) Document Number: Rev. *F Page 21 of 280

22 Pin No *1 23 * *1 16 *1 17 *1 21 *1 24 * *1 25 * * *1 18 *1 23 *1 27 * * Pin Name Polarity P043 - I/O Circuit types* 8 Function* 9 A13 *4, *5 - External bus/address bit13 output (0) A ICU7_1 - Input capture ch.7 input (1) TRG1_1 - PPG trigger 1 input (1) P044 - A14 *3, *4, *5 - External bus/address bit14 output (0) SCS9_0 - A Serial chip select 9 I/O (0) ICU6_1 - Input capture ch.6 input (1) TRG2_1 - PPG trigger 2 input (1) P045 - A15 *2, *3, *4, *5 - External bus/address bit15 output (0) SCK9_0 - Multi-function serial ch.9 clock I/O (0) AN46 - G ADC analog 46 input ICU5_1 - Input capture ch.5 input (1) TRG3_1 - PPG trigger 3 input (1) TOT1_2 - Reload timer ch.1 output (2) P046 - A16 *5 - External bus/address bit16 output (0) A ICU4_1 - Input capture ch.4 input (1) TRG4_1 - PPG trigger 4 input (1) P176 - A TRG10_0 - PPG trigger 10 input (0) P047 - A17 *2, *3, *4, *5 - External bus/address bit17 output (0) AN45 - ADC analog 45 input TRG8_0 - B PPG trigger 8 input (0) TIN3_2 - Reload timer ch.3 event input (2) SOT0_1 - Multi-function serial ch.0 serial data output (1) P177 - A TRG11_0 - PPG trigger 11 input (0) P050 - A18 *5 - External bus/address bit18 output A TRG5_1 - PPG trigger 5 input (1) PPG33_0 - PPG ch.33 output (0) P051 - A19 - A External bus/address bit19 output TRG9_0 - PPG trigger 9 input (0) P052 - A20 - External bus/address bit20 output A PPG34_0 - PPG ch.34 output (0) INT14_0 - INT14 External interrupt input (0) Document Number: Rev. *F Page 22 of 280

23 Pin No *1 19 *1 24 *1 29 * *1 22 *1 27 *1 32 * * *1 24 *1 29 *1 35 * Pin Name Polarity P053 - I/O Circuit types* 8 AN44 - ADC analog 44 input B PPG35_0 - PPG ch.35 output (0) Function* 9 A21 *2, *3, *4, *5 - External bus/address bit21 output INT14_1 - INT14 External interrupt input (1) SCK0_1 - Multi-function serial ch.0 clock I/O (1) P054 - SYSCLK - A External bus/system clock output PPG36_0 - PPG ch.36 output (0) P055 - CS2X *2, *3, *4, *5 - External bus chip select 2 output SIN10_0 - Multi-function serial ch.10 serial data input (0) G AN43 - ADC analog 43 input PPG37_0 - PPG ch.37 output (0) TIN4_1 - Reload timer ch.4 event input (1) P180 - A PPG40_0 - PPG ch.40 output (0) P181 - A PPG41_0 - PPG ch.41 output (0) P056 - CS3X *5 - External bus chip select 3 output ICU9_0 - Input capture ch.9 input (0) PPG0_1 - A PPG ch.0 output (1) ICU0_1 - Input capture ch.0 input (1) TIN5_1 - Reload timer ch.5 event input (1) DTTI_2 - Waveform generator ch.0-ch.5 input pin (2) P057 - RDY *2, *3, *4, *5 - External bus/ready input (0) SCK10_1 - Multi-function serial ch.10 clock I/O (1) AN42 - ADC analog 42 input ICU8_0 - G Input capture ch.8 input (0) TRG0_2 - PPG trigger 0 input (2) PPG1_1 - PPG ch.1 output (1) ICU1_1 - Input capture ch.1 input (1) TIN6_1 - Reload timer ch.6 event input (1) P142 - SCK10_0/ Multi-function serial ch.10 clock I/O (0)/ - SCL10 F I 2 C bus serial clock I/O PPG38_0 - PPG ch.38 output (0) TIN7_1 - Reload timer ch.7 event input (1) Document Number: Rev. *F Page 23 of 280

24 Pin No Pin Name Polarity P143 - I/O Circuit types* 8 Function* 9 SOT10_0/SDA1 Multi-function serial ch.10 serial data output - 0 F (0)/ I 2 C bus serial data I/O PPG39_0 - PPG ch.39 output (0) TOT4_1 - Reload timer ch.4 output (1) P182 - A PPG42_0 - PPG ch.42 output (0) P060 - SCS10_0 - Serial chip select 10 I/O (0) PPG2_1 - PPG ch.2 output (1) A ICU2_1 - Input capture ch.2 input (1) TOT5_1 - Reload timer ch.5 output (1) INT13_0 - INT13 External interrupt input (0) P061 - SOT10_1 - Multi-function serial ch.10 serial data output (1) AN41 - ADC analog 41 input ICU6_0 - B Input capture ch.6 input (0) PPG3_1 - PPG ch.3 output (1) ICU3_1 - Input capture ch.3 input (1) TOT6_1 - Reload timer ch.6 output (1) INT13_1 - INT13 External interrupt input (1) P062 - SCS10_1 - Serial chip select 10 I/O (1) SCS40_0 - Serial chip select 40 I/O (0) AN40 - ADC analog 40 input B PPG4_1 - PPG ch.4 output (1) FRCK0_0 - Free-run timer 0 clock input (0) TOT7_1 - Reload timer ch.7 output (1) ZIN1_1 - U/D counter ch.1 ZIN input (1) P063 - SCS41_0 - Serial chip select 41 output (0) AN39 - ADC analog 39 input B PPG5_1 - PPG ch.5 output (1) FRCK1_0 - Free-run timer 1 clock input (0) BIN1_1 - U/D counter ch.1 BIN input (1) P183 - A PPG43_0 - PPG ch.43 output (0) Document Number: Rev. *F Page 24 of 280

25 Pin No Pin Name Polarity P064 - I/O Circuit types* 8 Function* 9 SCS42_0 - Serial chip select 42 output (0) AN38 - ADC analog 38 input B FRCK2_0 - Free-run timer 2 clock input (0) AIN1_1 - U/D counter ch.1 AIN input (1) PPG43_1 - PPG ch.43 output (1) P065 - SCS43_0 - Serial chip select 43 output (0) FRCK3_0 - A Free-run timer 3 clock input (0) ZIN0_1 - U/D counter ch.0 ZIN input (1) PPG44_1 - PPG ch.44 output (1) P184 - A PPG44_0 - PPG ch.44 output (0) P185 - A PPG45_0 - PPG ch.45 output (0) P066 - SOT4_2 - Multi-function serial ch.4 serial data output (2) SCS3_0 - B Serial chip select 3 I/O (0) AN37 - ADC analog 37 input FRCK4_0 - Free-run timer 4 clock input (0) BIN0_1 - U/D counter ch.0 BIN input (1) P067 - AN36 - ADC analog 36 input B FRCK5_0 - Free-run timer 5 clock input (0) AIN0_1 - U/D counter ch.0 AIN input (1) P070 - A ICU0_2 - Input capture ch.0 input (2) P071 - Multi-function serial ch.4 SCK4_2 - clock I/O (2) G AN35 - ADC analog 35 input ICU1_2 - Input capture ch.1 input (2) MONCLK - Clock monitor output pin P072 - SIN4_0 - Multi-function serial ch.4 serial data input (0) AN34 - G ADC analog 34 input ICU2_2 - Input capture ch.2 input (2) INT5_0 - INT5 External interrupt input (0) Document Number: Rev. *F Page 25 of 280

26 Pin No *3 43 * Pin Name Polarity P073 - I/O Circuit types* 8 Function* 9 SOT4_0/ Multi-function serial ch.4 serial data output SDA4 *3, *4 - D (0)/I 2 C bus serial data I/O AN33 - ADC analog 33 input ICU3_2 - Input capture ch.3 input (2) P186 - A PPG46_0 - PPG ch.46 output (0) P187 - A PPG47_0 - PPG ch.47 output (0) P074 - SCK4_0/ SCL4 P E Multi-function serial ch.4 clock I/O (0)/ I 2 C bus serial clock I/O SIN3_0 - F Multi-function serial ch.3 serial data input (0) INT4_0 - INT4 External interrupt input (0) P076 - SOT3_0/ SDA3 P077 - SCK3_0/ SCL3 - - E E Multi-function serial ch.3 serial data output (0)/I 2 C bus serial data I/O Multi-function serial ch.3 clock I/O (0)/ I 2 C bus serial clock I/O P152 - A SCS53_0 - Serial chip select 53 output (0) P153 - SCK5_0/ Multi-function serial ch.5 clock I/O (0)/ - SCL5 I 2 C bus serial clock I/O G AN32 - ADC analog 32 input FRCK1_1 - Free-run timer 1 clock input (1) INT4_1 - INT4 External interrupt input (1) P080 - SCS52_0 - A Serial chip select 52 output (0) PPG0_0 - PPG ch.0 output (0) P081 - SOT5_0/ Multi-function serial ch.5 serial data output - SDA5 G (0)/I 2 C bus serial data I/O AN0 - ADC analog 0 input PPG1_0 - PPG ch.1 output (0) P082 - SIN5_0 - Multi-function serial ch.5 serial data input (0) G AN1 - ADC analog 1 input PPG2_0 - PPG ch.2 output (0) Document Number: Rev. *F Page 26 of 280

27 Pin No Pin Name Polarity P083 - I/O Circuit types* 8 Function* 9 SCS50_0 - Serial chip select 50 I/O (0) B AN2 - ADC analog 2 input PPG3_0 - PPG ch.3 output (0) P084 - SCS51_0 - Serial chip select 51 output (0) B AN3 - ADC analog 3 input PPG4_0 - PPG ch.4 output (0) P085 - A PPG5_0 - PPG ch.5 output (0) P086 - DAO1 - C DAC analog 1 output PPG6_0 - PPG ch.6 output (0) P087 - DAO0 - DAC analog 0 output C PPG7_0 - PPG ch.7 output (0) INT8_0 - INT8 External interrupt input (0) P190 - A TIN0_1 - Reload timer ch.0 event input (1) P191 - A TIN1_1 - Reload timer ch.1 event input (1) P090 - AN4 - ADC analog 4 input B ICU0_0 - Input capture ch.0 input (0) TIN2_1 - Reload timer ch.2 event input (1) P091 - AN5 - ADC analog 5 input PPG41_1 - B PPG ch.41 output (1) ICU1_0 - Input capture ch.1 input (0) TIN3_1 - Reload timer ch.3 event input (1) P092 - AN6 - ADC analog 6 input PPG40_1 - B PPG ch.40 output (1) ICU2_0 - Input capture ch.2 input (0) TOT0_1 - Reload timer ch.0 output (1) P192 - PPG24_1 - A PPG ch.24 output (1) TOT1_1 - Reload timer ch.1 output (1) Document Number: Rev. *F Page 27 of 280

28 Pin No *1 42 * * *1 49 * Pin Name Polarity P093 - I/O Circuit types* 8 Function* 9 TX0_1 - CAN transmission data 0 output (1) SIN11_0 - Multi-function serial ch.11 serial data input (0) AN7 - ADC analog 7 input J ICU4_2 - Input capture ch.4 input (2) PPG16_1 - PPG ch.16 output (1) ICU3_0 - Input capture ch.3 input (0) TOT2_1 *2, *3 - Reload timer ch.2 output (1) P094 - AN8 - ADC analog 8 input B ICU4_0 - Input capture ch.4 input (0) TOT3_1 - Reload timer ch.3 output (1) P095 - TX0(128) - CAN transmission data 0 output B SCS11_0 - Serial chip select 11 I/O (0) AN9 - ADC analog 9 input P096 - G RX0(128) - CAN reception data 0 input SOT11_0/ SDA11 - AN10 - ADC analog 10 input Multi-function serial ch.11 serial data output (0)/I 2 C bus serial data I/O INT0_0 - INT0 External interrupt input (0) P097 - SCK11_0/ Multi-function serial ch.11 clock I/O (0)/ - SCL11 I 2 C bus serial clock I/O G AN11 - ADC analog 11 input ICU5_0 - Input capture ch.5 input (0) PPG17_1 - PPG ch.17 output (1) P100 - SCK7_0/ Multi-function serial ch.7 clock I/O (0)/ SCL7 *3 - G I 2 C bus serial clock I/O AN12 - ADC analog 12 input PPG8_0 - PPG ch.8 output (0) P101 - SOT7_0/ Multi-function serial ch.7 serial data output - SDA7 G (0)/I 2 C bus serial data I/O AN13 - ADC analog 13 input PPG9_0 - PPG ch.9 output (0) P102 - SIN7_0 *2, *3 - Multi-function serial ch.7 serial data input (0) AN14 - G ADC analog 14 input PPG10_0 - PPG ch.10 output (0) INT10_0 - INT10 External interrupt input (0) Document Number: Rev. *F Page 28 of 280

29 Pin No *1 42 *1 43 *1 50 *1 51 *1 52 * Pin Name Polarity P103 - I/O Circuit types* 8 Function* 9 SCS73_0 *2, *3 - Serial chip select 73 output (0) H AN15 - ADC analog 15 input PPG11_0 - PPG ch.11 output (0) P104 - SCS72_0 *2, *3 - Serial chip select 72 output (0) H AN16 - ADC analog 16 input PPG12_0 - PPG ch.12 output (0) P105 - SCS71_0 *2, *3 - Serial chip select 71 output (0) H AN17 - ADC analog 17 input PPG13_0 - PPG ch.13 output (0) P106 - SCS70_0 - Serial chip select 70 I/O (0) H AN18 - ADC analog 18 input PPG14_0 - PPG ch.14 output (0) P107 - AN19 - B ADC analog 19 input PPG15_0 - PPG ch.15 output (0) P193 - A PPG25_1 - PPG ch.25 output (1) P154 - B AN20 - ADC analog 20 input P155 - B AN21 - ADC analog 21 input NMIX N M Non-masking interrupt input P110 - TX1(64) - CAN transmission data 1 output B SCS63_0 - Serial chip select 63 output (0) AN22 - ADC analog 22 input P111 - RX1(64) - CAN reception data 1 input SCS62_0 - G Serial chip select 62 output (0) AN23 - ADC analog 23 input INT1_0 - INT1 External interrupt input (0) P112 - AN24 - ADC analog 24 input B PPG16_0 - PPG ch.16 output (0) RTO0_0 - Waveform generator ch. 0 output pin (0) Document Number: Rev. *F Page 29 of 280

30 Pin No Pin Name Polarity P113 - I/O Circuit types* 8 AN25 - ADC analog 25 input B PPG17_0 - PPG ch.17 output (0) Function* 9 RTO1_0 - Waveform generator ch. 1 output pin (0) P194 - FRCK5_1 - A Free-run timer 5 clock input (1) PPG26_1 - PPG ch.26 output (1) P195 - FRCK4_1 - A Free-run timer 4 clock input (1) PPG27_1 - PPG ch.27 output (1) P114 - SCS61_0 - Serial chip select 61 output (0) AN26 - B ADC analog 26 input PPG18_0 - PPG ch.18 output (0) RTO2_0 - Waveform generator ch.2 output pin (0) P115 - RX1_1 - CAN reception data 1 input (1) SOT6_0/ Multi-function serial ch.6 serial data output - SDA6 (0)/I 2 C bus serial data I/O G AN27 - ADC analog 27 input PPG19_0 - PPG ch.19 output (0) RTO3_0 - Waveform generator ch.3 output pin (0) INT1_1 - INT1 External interrupt input (1) P116 - SCK6_0/ Multi-function serial ch.6 clock I/O (0)/ - SCL6 I 2 C bus serial clock I/O G AN28 - ADC analog 28 input PPG20_0 - PPG ch.20 output (0) RTO4_0 - Waveform generator ch.4 output pin (0) P117 - SCS60_0 - Serial chip select 60 I/O (0) AN29 - B ADC analog 29 input PPG21_0 - PPG ch.21 output (0) RTO5_0 - Waveform generator ch.5 output pin (0) P196 - FRCK3_1 - A Free-run timer 3 clock input (1) PPG28_1 - PPG ch.28 output (1) P120 - AN30 - ADC analog 30 input OCU6_0 - B Output compare ch.6 output (0) PPG22_0 - PPG ch.22 output (0) INT9_0 - INT9 External interrupt input (0) Document Number: Rev. *F Page 30 of 280

31 Pin No Pin Name Polarity P121 - I/O Circuit types* 8 Function* 9 OCU7_0 - A Output compare ch.7 output (0) PPG23_0 - PPG ch.23 output (0) P122 - SIN6_0 - Multi-function serial ch.6 serial data input (0) AN31 - J ADC analog 31 input OCU8_0 - Output compare ch.8 output (0) INT9_1 - INT9 External interrupt input (1) P197 - A PPG29_1 - PPG ch.29 output (1) P123 - A OCU9_0 - Output compare ch.9 output (0) DEBUGIF - L MDI I/O for debugger (OCD) P160 - A PPG30_1 - PPG ch.30 output (1) P161 - A PPG31_1 - PPG ch.31 output (1) P124 - A OCU10_0 - Output compare ch.10 output (0) P125 - A OCU11_0 - Output compare ch.11 output (0) P126 - SIN0_0 - F Multi-function serial ch.0 serial data input (0) INT6_0 - INT6 External interrupt input (0) P127 - SOT0_0 - A Multi-function serial ch.0 serial data output (0) P130 - F SCK0_0 - Multi-function serial ch.0 clock I/O (0) P162 - A TRG5_2 - PPG trigger 5 input (2) P163 - A TRG6_2 - PPG trigger 6 input (2) MD0 - K Mode pin MD1 - K Mode pin X0 - N Main clock oscillation input X1 - N Main clock oscillation output P135 - A DTTI_0 - Waveform generator ch.0-ch.5 input pin (0) X1A - O Sub clock oscillation output P136 - A X0A - O Sub clock oscillation input Document Number: Rev. *F Page 31 of 280

32 Pin No Pin Name Polarity I/O Circuit types* RSTX N M External reset input *1-75 *1 95 * *1 96 *1 111 *1 112 *1 113 *1 114 * Function* 9 P131 - A ADTG0_0 - A/D converter external trigger input 0 (0) P132 - SCS1_0 - A Serial chip select 1 I/O (0) ADTG1_0 - A/D converter external trigger input 1 (0) P133 - A TX2(64) - CAN transmission data 2 output P134 - RX2(64) - CAN reception data 2 input SCS1_1 - F Serial chip select 1 I/O (1) ICU7_0 - Input capture ch.7 input (0) INT7_0 - INT7 External interrupt input (0) P144 - F SCK1_1 - Multi-function serial ch.1 clock I/O (1) P000 - D16 *4, *5 - External bus data bit16 I/O (0) SIN1_0 - F Multi-function serial ch.1 serial data input (0) TIOA0_1 *4 - TIOA output of Base timer ch.0 (1) INT2_0 - INT2 External interrupt input (0) P001 - D17 *3, *4, *5 - External bus data bit17 I/O SOT1_0 *3 - A Multi-function serial ch.1 serial data output (0) TIOA1_1 - TIOA I/O of Base timer ch.1 (1) P002 - D18 *5 - External bus data bit18 I/O F SCK1_0 - Multi-function serial ch.1 clock I/O (0) TIOB0_1 - TIOB input of Base timer ch.0 (1) P003 - D19 *3, *4, *5 - External bus data bit19 I/O SIN2_0 - F Multi-function serial ch.2 serial data input (0) TIOB1_1 - TIOB input of Base timer ch.1 (1) INT3_0 - INT3 External interrupt input (0) P004 - D20 - External bus data bit20 I/O (0) A Multi-function serial ch.2 serial data output SOT2_0 - (0) P164 - A PPG32_1 - PPG ch.32 output (1) Document Number: Rev. *F Page 32 of 280

33 Pin No *1 77 *1 97 *1 115 *1 136 *1 165 * *1 78 *1 98 * *1 117 *1 137 *1 167 * *1 79 *1 99 *1 118 *1 119 * Pin Name Polarity P005 - I/O Circuit types* 8 Function* 9 D21 *2, *3, *4, *5 - External bus data bit21 I/O (0) SCK2_0 *2 - Multi-function serial ch.2 clock I/O (0) ADTG0_1 - F A/D converter external trigger input 0 (1) INT7_1 - INT7 External interrupt input (1) RX2(64) *4, *5, *6, *7 - CAN reception data 2 input P165 - A PPG33_1 - PPG ch.33 output (1) P006 - D22 *2, *3, *4, *5 - External bus data bit22 I/O (0) SCS2_0 *2 - Serial chip select 2 I/O (0) ADTG1_1 - A A/D converter external trigger input 1 (1) INT2_1 - INT2 External interrupt input (1) TX2(64) *4, *5, *6, *7 - CAN transmission data 2 output P007 - A D23 *5 - External bus data bit23 I/O P166 - A PPG34_1 - PPG ch.34 output (1) P010 - A D24 *5 - External bus data bit24 I/O P011 - WOT - RTC output signal D25 *2, *3, *4, *5 - External bus data bit25 I/O SOT2_1 *2 - A Multi-function serial ch.2 serial data output (1) TIOA0_0 *2, *3, *4 - TIOA output of Base timer ch.0 (0) INT3_1 - INT3 External interrupt input (1) P012 - D26 - A External bus data bit26 I/O TIOB0_0 - TIOB input of Base timer ch.0 (0) P167 - A PPG35_1 - PPG ch.35 output (1) P013 - D27 - A External bus data bit27 I/O TIOA1_0 - TIOA I/O of Base timer ch.1 (0) P AVCC AVCC0 - - D28 - A External bus data bit28 I/O TIOB1_0 - TIOB input of Base timer ch.1 (0) Analog power supply for AD/DA convertor unit1 Analog power supply for AD/DA convertor unit0 Document Number: Rev. *F Page 33 of 280

34 Pin No Pin Name Polarity I/O Circuit types* AVRH AVRH AVSS1/ AVRL1 AVSS0/ AVRL Function* 9 Upper limit reference voltage for AD convertor unit1 Upper limit reference voltage for AD convertor unit0 GND for AD/DA convertor unit1 Lower limit reference voltage for AD convertor unit1 GND for AD/DA convertor unit0 Lower limit reference voltage for AD convertor unit C - - External capacity connection output VCC V power supply VSS - - GND *1: There is a restriction of pin functions. See "Pin Name" of this table. *2: not supported in 64 pin *3: not supported in 80 pin *4: not supported in 100 pin *5: not supported in 120 pin *6: not supported in 144 pin *7: not supported in 176 pin *8: For the I/O circuit types, see I/O Circuit Type. *9: For switching, see "I/O Port" in HARDWARE MANUAL. Document Number: Rev. *F Page 34 of 280

35 4. I/O Circuit Type Type Circuit Remarks Pull-up control A Digital output Digital output Output 4 ma Pull-up resistor control 50 kω Automotive input Automotive input Standby control Pull-up control B Digital output Digital output Analog input, Output 4 ma Pull-up resistor control 50 kω Automotive input Automotive input Standby control Analog input Pull-up control C Digital output Digital output DAC output, Output 4 ma Pull-up resistor control 50 kω Automotive input Automotive input Standby control DAC output Document Number: Rev. *F Page 35 of 280

36 Type Circuit Remarks Pull-up control Digital output D Digital output I 2 C Analog input, Output 3 ma Pull-up resistor control 50 kω I 2 C hysteresis input I 2 C input Standby control Analog input Pull-up control E Digital output Digital output I 2 C, Output 3 ma Pull-up resistor control 50 kω I 2 C hysteresis input I 2 C input Standby control Pull-up control F Digital output Digital output Output 4 ma Pull-up resistor control 50 kω CMOS hysteresis input CMOS-hys input Standby control Document Number: Rev. *F Page 36 of 280

37 Type Circuit Remarks Pull-up control Digital output G Digital output CMOS-hys input Analog input, Output 4 ma Pull-up resistor control 50 kω CMOS hysteresis input Standby control Analog input Pull-up control Digital output H Digital output Automotive input Standby control Analog input, Output 12 ma Pull-up resistor control 50 kω Automotive input Analog input Digital output I Digital output (5 V tolerant) Output 4 ma CMOS hysteresis input CMOS-hys input Standby control Document Number: Rev. *F Page 37 of 280

38 Type Circuit Remarks Digital output J Digital output CMOS-hys input Standby control Analog input, (5 V tolerant) Output 4 ma CMOS hysteresis input Analog input K Mode input Control Mode I/O CMOS hysteresis input L Digital output TTL input Open-drain I/O Output 25 ma (Nch open-drain) TTL input M CMOS hysteresis input Pull-up resistor 50 kω CMOS-hys input Input N Main oscillation I/O Standby control Document Number: Rev. *F Page 38 of 280

39 Type Circuit Remarks Input O Sub oscillation I/O Standby control Document Number: Rev. *F Page 39 of 280

40 5. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Document Number: Rev. *F Page 40 of 280

41 Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause Document Number: Rev. *F Page 41 of 280

42 absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70 % relative humidity, and at temperatures between 5 C and 30 C. When you open Dry Package that recommends humidity 40 % to 70 % relative humidity. (3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125 C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40 % and 70 %. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame Document Number: Rev. *F Page 42 of 280

43 CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: Rev. *F Page 43 of 280

44 6. Handling Devices This section explains the latch-up prevention and pin processing. For latch-up prevention If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding the ratings is applied between VCC and VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs, the power supply current increases excessively and device elements may be damaged by heat. Take care to prevent any voltage from exceeding the maximum ratings in device application. Also, the analog power supply (AVCC, AVRH) and analog input must not be exceed the digital power supply (VCC) when the power supply to the analog system is turned on or off. In the correct power-on sequence of the microcontroller, turn on the digital power supply (VCC) and analog power supplies (AVCC, AVRH) simultaneously. Or, turn on the digital power supply (VCC), and then turn on analog power supplies (AVCC, AVRH). Treatment of unused pins If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or latch-up. Connect at least a 2 kω resistor to each of the unused pins for pull-up or pull-down processing. Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the input state and treated in the same way as for the input pins. Power supply pins The device is designed to ensure that if the device contains multiple VCC or VSS pins, the pins that should be at the same potential are interconnected to prevent latch-up or other malfunctions. Further, connect these pins to an external power supply or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. As shown in figure 1, all Vss power supply pins must be treated in the similar way. If multiple Vcc or Vss systems are connected, the device cannot operate correctly even within the guaranteed operating range. Figure 1 Power Supply Input Pins Vcc Vss Vss Vcc Vcc Vss Vcc Vss Vcc Vss The power supply pins should be connected to VCC and VSS pins of this device at the low impedance from the power supply source. In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin is recommended to use as a bypass capacitor between VCC and VSS pins. Document Number: Rev. *F Page 44 of 280

45 Crystal oscillation circuit An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be designed to lay out X0 and X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be grounded to the close position to the device. The printed circuit board artwork is recommended to surround the X0 and X1 pins by ground circuits. Mode pins (MD1, MD0) Connect the MD1 and MD0 mode pins to the VCC or VSS pin directly. To prevent an erroneous selection of test mode caused by the noise, reduce the pattern length between each mode pin and VCC or VSS pin on the printed circuit board. Also, use the low-impedance pin connection. During power-on To prevent a malfunction of the voltage step-down circuit built in the device, the voltage rising must be monotonic during power-on. Notes during PLL clock operation When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue to operate at the free running frequency of the self-oscillator circuit built in the PLL clock. This operation is not guaranteed. Treatment of A/D converter power supply pins Connect the pins to have AVCC = AVRH = VCC and AVSS/AVRL = VSS even if the A/D converter is not used. Notes on using external clock An external clock is not supported. None of the external direct clock input can be used for both main clock and sub clock. Power-on sequence of A/D converter analog inputs Be sure to turn on the digital power supply (Vcc) first, and then turn on the A/D converter power supplies (AVcc, AVRH, AVRL) and analog inputs (AN0 to AN47). Also, turn off the A/D converter power supplies and analog inputs first, and then turn off the digital power supply (Vcc). When the AVRH pin voltage is turned on or off, it must not exceed AVCC. Even if a common analog input pin is used as an input port, its input voltage must not exceed AVcc. (However, the analog power supply and digital power supply can be turned on or off simultaneously.) Treatment of C pin This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to assure the internal stabilization of the device. For the standard values, see the "Recommended Operating Conditions" of the latest data sheet. Note: Please see the latest data sheet for a detailed specification of the operation voltage. Function switching of a multiplexed port To switch between the port function and the multiplexed pin function, use the PFR (port function register). However, if a pin is also used for an external bus, its function is switched by the external bus setting. For details, see " I/O PORTS" in the hardware manual. Low-power consumption mode To transit to the sleep mode, watch mode, stop mode, watch mode(power-off) or stop mode(power-off), follow the procedure explained in "Activating the sleep mode, watch mode, or stop mode" or "Activating the watch mode (power-off) or stop mode(power-off)" of " POWER CONSUMPTION CONTROL" in the hardware manual. Take the following notes when using a monitor debugger. Do not set a break point for the low-power consumption transition program. Do not execute an operation step for the low-power consumption transition program. Document Number: Rev. *F Page 45 of 280

46 Notes When Writing Data in a Register Having the Status Flag When writing data in the register that has a status flag (especially, an interrupt request flag) to control function, taking care not to clear its status flag erroneously must be followed. The program must be written not to clear the flag to the status bit, and then to set the control bits to have the desired value. Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can access to a single bit only.) By the Byte, Half-word, or Word access, data is written to the control bits and status flag simultaneously. During this time, take care not to clear other bits (in this case, the bits of status flag) erroneously. Note: These points can be ignored because the bit instructions are already taken the points into consideration. Document Number: Rev. *F Page 46 of 280

47 I / O Port 32bit Peripheral Bus (APB) MB91520 Series 7. Block Diagram MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B Regulator Power-on reset CR oscillator FR81s CPU core M P U Instruction Data Debug Interface From Master To Slave From Master To Slave RAM 48K/64K/96K/128K Wild register XBS Crossbar Switch Flash Main Flash 256K/384K/512K/768K/ 1024KB +64KB Timing Protection Unit On-chip bus layer 2 On-chip bus layer 1 On-chip bus(ahb) XBS RAM ECC Control(XBS RAM) DMAC (16 ch) CAN (3ch) Clock / Bus Bridge Peripheral Bus Bridge Bus performance counter Operation mode register RX,T RAM ECC Control (BackUp RAM) BackUp RAM +8KB MD0,MD1,P00 Async Bus Bridge (PCLK1 <-> PCLK2) Async Bus Bridge (PCLK1 <-> PCLK2) CAN prescaler CRC FRCK ICU OCU TIOA,TIOB AIN,BIN,ZI TIN,TOT DAO MONCLK RTC/WDT1 Calibration I/O port setting 32bit Free-run timer(1ch) 32bit Input capture(5ch) 32bit Output compare(4ch) Base timer (1ch) U/D counter (2ch) Reload timer (7ch) 8bit DA converter (1ch) Clock monitor Watchdog timer(sw and HW) DMA transfer request generate/clear 16bit Peripheral Bus Wave generator (6ch) 16bit Free-run timer (3ch) 16bit Input capture (4ch) 16bit Output compare (6ch) 12bit AD converter (13ch + 13ch) (8ch) Bus Bridge (32bit <-> 16bit) PPG(21ch) Bus Bridge (32bit <-> 16bit) External interrupt input(16ch) Real time clock Clock supervisor NMI NMIX DTTI,RTO FRCK ICU ADTG,AIN SOUT, SIN, SCK TRG,PPG INT WOT I / O Port Interrupt request batch read Clock control (divide control) Low-voltage detection (External power supply low-voltage detection) RST Reset control register Low-power consumption setting register Low-voltage detection (Internal power supply low-voltage detection) Delay interrupt Interrupt controller Clock control (Clock setting, Main timer, Sub timer, PLL timer) Document Number: Rev. *F Page 47 of 280

48 I / O Port 32bit Peripheral Bus (APB) MB91520 Series MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D Regulator Power-on reset CR oscillator FR81s CPU core M P U Instruction Data Debug Interface From Master To Slave From Master To Slave RAM 48K/64K/96K/128K Wild register XBS Crossbar Switch Flash Main Flash 256K/384K/512K/768K/ 1024KB +64KB Timing Protection Unit On-chip bus layer 2 On-chip bus layer 1 On-chip bus(ahb) XBS RAM ECC Control(XBS RAM) DMAC (16 ch) CAN (3ch) Clock / Bus Bridge Peripheral Bus Bridge Bus performance counter Operation mode register RX,T RAM ECC Control (BackUp RAM) BackUp RAM +8KB MD0,MD1,P00 Async Bus Bridge (PCLK1 <-> PCLK2) Async Bus Bridge (PCLK1 <-> PCLK2) CAN prescaler CRC FRCK ICU OCU TIOA,TIOB AIN,BIN,ZI TIN,TOT DAO MONCLK RTC/WDT1 Calibration I/O port setting 32bit Free-run timer(2ch) 32bit Input capture(5ch) 32bit Output compare(4ch) Base timer (1ch) U/D counter (2ch) Reload timer (7ch) 8bit DA converter (2ch) Clock monitor Watchdog timer(sw and HW) DMA transfer request generate/clear 16bit Peripheral Bus Wave generator (6ch) 16bit Free-run timer (3ch) 16bit Input capture (4ch) 16bit Output compare (6ch) 12bit AD converter (21ch + 16ch) (9ch) Bus Bridge (32bit <-> 16bit) PPG(27ch) Bus Bridge (32bit <-> 16bit) External interrupt input(16ch) Real time clock Clock supervisor NMI NMIX DTTI,RTO FRCK ICU ADTG,AIN SOUT, SIN, SCK TRG,PPG INT WOT I / O Port Interrupt request batch read Clock control (divide control) Low-voltage detection (External power supply low-voltage detection) RST Reset control register Low-power consumption setting register Low-voltage detection (Internal power supply low-voltage detection) Delay interrupt Interrupt controller Clock control (Clock setting, Main timer, Sub timer, PLL timer) Document Number: Rev. *F Page 48 of 280

49 I / O Port 32bit Peripheral Bus (APB) MB91520 Series MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F Regulator Power-on reset CR oscillator FR81s CPU core M P U Instruction Data Debug Interface From Master To Slave From Master To Slave RAM 48K/64K/96K/128K Wild register XBS Crossbar Switch Flash Main Flash 256K/384K/512K/768K/ 1024KB +64KB WorkFlash 64KB Timing Protection Unit On-chip bus layer 2 On-chip bus layer 1 On-chip bus(ahb) XBS RAM ECC Control(XBS RAM) DMAC (16 ch) CAN (3ch) Clock / Bus Bridge Peripheral Bus Bridge Bus performance counter Operation mode register RX,TX RAM ECC Control (BackUp RAM) BackUp RAM +8KB MD0,MD1,P006 Async Bus Bridge (PCLK1 <-> PCLK2) Async Bus Bridge (PCLK1 <-> PCLK2) CAN prescaler CRC FRCK ICU OCU TIOA,TIOB AIN,BIN,ZIN TIN,TOT DAO MONCLK RTC/WDT1 Calibration I/O port setting 32bit Free-run timer(3ch) 32bit Input capture(6ch) 32bit Output compare(6ch) Base timer (1ch) U/D counter (2ch) Reload timer (8ch) 8bit DA converter (2ch) Clock monitor Watchdog timer(sw and HW) DMA transfer request generate/clear 16bit Peripheral Bus Wave generator (6ch) 16bit Free-run timer (3ch) 16bit Input capture (4ch) 16bit Output compare (6ch) 12bit AD converter (21ch + 16ch) (12ch) Bus Bridge (32bit <-> 16bit) PPG(34ch) Bus Bridge (32bit <-> 16bit) External interrupt input(16ch) Real time clock Clock supervisor NMI NMIX DTTI,RTO FRCK ICU ADTG,AIN ADC enable(ader) SOUT, SIN, SCK TRG,PPG INT WOT I / O Port Interrupt request batch read Clock control (divide control) Low-voltage detection (External power supply low-voltage detection) RSTX Reset control register Low-power consumption setting register Low-voltage detection (Internal power supply low-voltage detection) Delay interrupt Interrupt controller Clock control (Clock setting, Main timer, Sub timer, PLL timer) Document Number: Rev. *F Page 49 of 280

50 I / O Port 32bit Peripheral Bus (APB) MB91520 Series MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J Regulator Power-on reset CR oscillator FR81s CPU core M P U Instruction Data Debug Interface From Master To Slave From Master To Slave RAM 48K/64K/96K/128K Wild register XBS Crossbar Switch Flash Main Flash 256K/384K/512K/768K/ 1024KB +64KB WorkFlash 64KB Timing Protection Unit On-chip bus layer 2 On-chip bus layer 1 On-chip bus(ahb) XBS RAM ECC Control(XBS RAM) DMAC (16 ch) CAN (3ch) Clock / Bus Bridge Peripheral Bus Bridge Bus performance counter Operation mode register RX,TX RAM ECC Control (BackUp RAM) BackUp RAM +8KB MD0,MD1,P006 Async Bus Bridge (PCLK1 <-> PCLK2) Async Bus Bridge (PCLK1 <-> PCLK2) CAN prescaler CRC FRCK ICU OCU TIOA,TIOB AIN,BIN,ZIN TIN,TOT DAO MONCLK RTC/WDT1 Calibration I/O port setting 32bit Free-run timer(3ch) 32bit Input capture(6ch) 32bit Output compare(6ch) Base timer (2ch) U/D counter (2ch) Reload timer (8ch) 8bit DA converter (2ch) Clock monitor Watchdog timer(sw and HW) DMA transfer request generate/clear 16bit Peripheral Bus Wave generator (6ch) 16bit Free-run timer (3ch) 16bit Input capture (4ch) 16bit Output compare (6ch) 12bit AD converter (26ch + 16ch) (12ch) Bus Bridge (32bit <-> 16bit) PPG(38ch) Bus Bridge (32bit <-> 16bit) External interrupt input(16ch) Real time clock Clock supervisor NMI NMIX DTTI,RTO FRCK ICU ADTG,AIN ADC enable(ader) SOUT, SIN, SCK TRG,PPG INT WOT I / O Port Interrupt request batch read Clock control (divide control) Low-voltage detection (External power supply low-voltage detection) RSTX Reset control register Low-power consumption setting register Low-voltage detection (Internal power supply low-voltage detection) Delay interrupt Interrupt controller Clock control (Clock setting, Main timer, Sub timer, PLL timer) Document Number: Rev. *F Page 50 of 280

51 I / O Port 32bit Peripheral Bus (APB) MB91520 Series MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K Regulator Power-on reset CR oscillator FR81s CPU core M P U Instruction Data Debug Interface From Master To Slave From Master To Slave RAM 48K/64K/96K/128K Wild register XBS Crossbar Switch Flash Main Flash 256K/384K/512K/768K/ 1024KB +64KB WorkFlash 64KB Timing Protection Unit On-chip bus layer 2 On-chip bus layer 1 On-chip bus(ahb) XBS RAM ECC Control(XBS RAM) DMAC (16 ch) External Bus I / F CAN (3ch) Clock / Bus Bridge Peripheral Bus Bridge Bus performance counter Operation mode register RX,TX RAM ECC Control (BackUp RAM) BackUp RAM +8KB MD0,MD1,P006 D,A, ASX,CS, RDX, WRX, SYSCLK, RDY FRCK ICU OCU TIOA,TIOB AIN,BIN,ZIN TIN,TOT DAO MONCLK Async Bus Bridge (PCLK1 <-> PCLK2) CAN prescaler RTC/WDT1 Calibration I/O port setting 32bit Free-run timer(3ch) 32bit Input capture(6ch) 32bit Output compare(6ch) Base timer (2ch) U/D counter (2ch) Reload timer (8ch) 8bit DA converter (2ch) Clock monitor Watchdog timer(sw and HW) DMA transfer request generate/clear 16bit Peripheral Bus Async Bus Bridge (PCLK1 <-> PCLK2) CRC Wave generator (6ch) 16bit Free-run timer (3ch) 16bit Input capture (4ch) 16bit Output compare (6ch) 12bit AD converter (32ch + 16ch) (12ch) Bus Bridge (32bit <-> 16bit) PPG(44ch) Bus Bridge (32bit <-> 16bit) External interrupt input(16ch) Real time clock Clock supervisor NMI NMIX DTTI,RTO FRCK ICU ADTG,AIN ADC enable(ader) SOUT, SIN, SCK TRG,PPG INT WOT I / O Port Interrupt request batch read Clock control (divide control) Low-voltage detection (External power supply low-voltage detection) RSTX Reset control register Low-power consumption setting register Low-voltage detection (Internal power supply low-voltage detection) Delay interrupt Interrupt controller Clock control (Clock setting, Main timer, Sub timer, PLL timer) Document Number: Rev. *F Page 51 of 280

52 I / O Port 32bit Peripheral Bus (APB) MB91520 Series MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L Regulator Power-on reset CR oscillator FR81s CPU core M P U Instruction Data Debug Interface From Master To Slave From Master To Slave RAM 48K/64K/96K/128K Wild register XBS Crossbar Switch Flash Main Flash 256K/384K/512K/768K/ 1024KB +64KB WorkFlash 64KB Timing Protection Unit On-chip bus layer 2 On-chip bus layer 1 On-chip bus(ahb) XBS RAM ECC Control(XBS RAM) DMAC (16 ch) External Bus I / F CAN (3ch) Clock / Bus Bridge Peripheral Bus Bridge Bus performance counter Operation mode register RX,TX RAM ECC Control (BackUp RAM) BackUp RAM +8KB MD0,MD1,P006 D,A, ASX,CS, RDX, WRX, SYSCLK, RDY FRCK ICU OCU TIOA,TIOB AIN,BIN,ZIN TIN,TOT DAO MONCLK Async Bus Bridge (PCLK1 <-> PCLK2) CAN prescaler RTC/WDT1 Calibration I/O port setting 32bit Free-run timer(3ch) 32bit Input capture(6ch) 32bit Output compare(6ch) Base timer (2ch) U/D counter (2ch) Reload timer (8ch) 8bit DA converter (2ch) Clock monitor Watchdog timer(sw and HW) DMA transfer request generate/clear 16bit Peripheral Bus Async Bus Bridge (PCLK1 <-> PCLK2) CRC Wave generator (6ch) 16bit Free-run timer (3ch) 16bit Input capture (4ch) 16bit Output compare (6ch) 12bit AD converter (32ch + 16ch) (12ch) Bus Bridge (32bit <-> 16bit) PPG(48ch) Bus Bridge (32bit <-> 16bit) External interrupt input(16ch) Real time clock Clock supervisor NMI NMIX DTTI,RTO FRCK ICU ADTG,AIN ADC enable(ader) SOUT, SIN, SCK TRG,PPG INT WOT I / O Port Interrupt request batch read Clock control (divide control) Low-voltage detection (External power supply low-voltage detection) RSTX Reset control register Low-power consumption setting register Low-voltage detection (Internal power supply low-voltage detection) Delay interrupt Interrupt controller Clock control (Clock setting, Main timer, Sub timer, PLL timer) Document Number: Rev. *F Page 52 of 280

53 8. Memory Map MB91F522, MB91F523, MB91F524 MB91F522 MB91F523 MB91F H H H I/O I/O I/O H BackUp RAM (8KB) H H BackUp RAM (8KB) BackUp RAM (8KB) H H H I/O I/O I/O H H H RAM (48KB) RAM (48KB) RAM (64KB) 0001 C000H 0001 C000H H Reserved Reserved Reserved H 000C 0000H Flash memory (256+64)KB Reserved H H 000E 0000H Flash memory (384+64)KB Reserved Flash memory (512+64)KB 000F FC00H H Interrupt vector Reset vector 000F FC00H H Interrupt vector Reset vector 000F FC00H H Interrupt vector Reset vector Reserved Reserved Reserved H H H WorkFlash WorkFlash WorkFlash (64KB) (64KB) (64KB) H H H H H Reserved H Reserved H Reserved H H H External area External area External area FFFF FFFFH FFFF FFFFH FFFF FFFFH Document Number: Rev. *F Page 53 of 280

54 MB91F525, MB91F526 MB91F525 MB91F H H H H I/O BackUp RAM (8KB) I/O H H H H I/O BackUp RAM (8KB) I/O RAM (96KB) RAM (128KB) H H Reserved Reserved H H Flash memory (768+64)KB 000F FC00H Interrupt vector 000F FC00H 0010 Reset vector 0000H Flash memory H H Flash memory ( )KB Interrupt vector Reset vector Flash memory H Reserved Reserved H H WorkFlash (64KB) H H WorkFlash (64KB) H H H Reserved H Reserved H H External area External area FFFF FFFFH FFFF FFFFH Document Number: Rev. *F Page 54 of 280

55 9. I/O Map The following I/O map shows the relationship between memory space and registers for peripheral resources. Legend of I/O Map Read/Write attribute (R: Read W: Write) Address Address offset value/ register name H BT1TMR[R] H BT1TMCR[R/W] BT1STC[R/W] B H H BT1PCSR/BT1PRLL[R /W] H BT1PDU T/BT1PRLH/BT1DTBF[R/W] H 00009C H BTSEL[R/W] B BTSSSR[W] B,H A0 H ADERH [R/W]B, H, W ADERL [R/W]B, H, W 0000A4 H ADCS1 [R/W] B, H,W ADCS0 [R/W] B, H,W ADCR1 [R] B, H,W ADCR0 [R] B, H,W XX XXXXX XXX 0000A8 H ADCT1 [R/W] B, H,W ADCT0 [R/W] B, H,W ADSCH [R/W] B, H,W ADECH [R/W] B, H,W Block Base timer 1 A/D converter Data access attribute B: Byte H: Half-word W: Word (Note)The access by the data access attribute not described is disabled. Initial register value after reset The initial register value after reset indicates as follows: "1": Initial value "1" "0": Initial value "0" "X": Initial value undefined "-": Reserved bit/undefined bit "*": Initial value "0" or "1" according to the setting Note: The access to addresses not described is disabled. Document Number: Rev. *F Page 55 of 280

56 Address Address offset value / Register name PDR00 [R/W] PDR01 [R/W] PDR02 [R/W] PDR03 [R/W] H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PDR04 [R/W] PDR05 [R/W] PDR06 [R/W] PDR07 [R/W] H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PDR08 [R/W] PDR09 [R/W] PDR10 [R/W] PDR11 [R/W] H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PDR12 [R/W] PDR13 [R/W] PDR14 [R/W] PDR15 [R/W] 00000CH XXXXXXXX -XXXXXXX ---XXX-- --XXXXXX H H PDR16 [R/W] PDR17 [R/W] PDR18 [R/W] PDR19 [R/W] H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00001CH to H H 00003CH Block Port Data Register Reserved WDTECR0 [R/W] WDTCR0 [R/W] Watchdog Timer [S] WDTCPR0 [W] WDTCR1 [R] WDTCPR1 [W] H Reserved H H to DICR [R/W] Delayed Interrupt Reserved 00005CH H TMRLRA0 [R/W] H TMR0 [R] H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX H TMRLRB0 [R/W] H TMCSR0 [R/W] XXXXXXXX XXXXXXXX H TMRLRA7 [R/W] H TMR7 [R] H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00006CH TMRLRB7 [R/W] H TMCSR7 [R/W] XXXXXXXX XXXXXXXX H FRS8 [R/W] H FRS9 [R/W] OCLS67 [R/W] H OCLS89 [R/W] 00007CH H BT0TMR [R] H BT0TMCR [R/W] H Reload Timer 0 Reload Timer 7 Free-run timer selection register 8 Free-run timer selection register 9 OCU67 Output level control register OCU89 Output level control register Base Timer 0 Document Number: Rev. *F Page 56 of 280

57 Address H Address offset value / Register name BT0TMCR2 [R/W] B BT0STC [R/W] B Block BT0PCSR/BT0PRLL [R/W] H BT0PDUT/BT0PRLH/BT0DTBF [R/W] H H 00008CH Reserved BT1TMR [R] H BT1TMCR [R/W] H H BT1TMCR2 [R/W] B BT1STC [R/W] B H Base Timer BT1PCSR/BT1PRLL [R/W] H BT1PDUT/BT1PRLH/BT1DTBF [R/W] H H 00009CH 0000A0H to BTSEL01 [R/W] B BTSSSR [W] B,H Base Timer 0,1 Reserved 0000FCH H TMRLRA1 [R/W] H TMR1 [R] H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX H TMRLRB1 [R/W] H TMCSR1 [R/W] B, H,W XXXXXXXX XXXXXXXX H TMRLRA2 [R/W] H TMR2 [R] H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00010CH TMRLRB2 [R/W] H TMCSR2 [R/W] XXXXXXXX XXXXXXXX H TMRLRA3 [R/W] H TMR3 [R] H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX H TMRLRB3 [R/W] H TMCSR3 [R/W] XXXXXXXX XXXXXXXX H MSCY4 [R] H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00011CH MSCY5 [R] H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX H OCCP6 [R/W] W H OCCP7 [R/W] W OCSH67 [R/W] OCSL67 [R/W] H CH OCCP8 [R/W] W H OCCP9 [R/W] W H H to 0001B4H OCSH89 [R/W] OCSL89 [R/W] Reload Timer 1 Reload Timer 2 Reload Timer 3 Input Capture 4,5 Cycle measurement data register 45 Output Compare 6,7 32-bit OCU Output Compare 8,9 32-bit OCU Reserved Document Number: Rev. *F Page 57 of 280

58 Address 0001B8H 0001BCH 0001C0H 0001C4H 0001C8H 0001CCH 0001D0H Address offset value / Register name EPFR65 [R/W] EPFR66 [R/W] EPFR64 [R/W] EPFR68 [R/W] EPFR72 [R/W] EPFR76 [R/W] EPFR80 [R/W] EPFR84 [R/W] EPFR88 [R/W] EPFR69 [R/W] EPFR73 [R/W] EPFR77 [R/W] EPFR81 [R/W] EPFR85 [R/W] EPFR70 [R/W] EPFR74 [R/W] EPFR78 [R/W] EPFR82 [R/W] EPFR86 [R/W] EPFR67 [R/W] EPFR71 [R/W] EPFR75 [R/W] EPFR79 [R/W] EPFR83 [R/W] EPFR87 [R/W] Block Extended port function register 0001D4H Reserved TMRLRA4 [R/W] H TMR4 [R] H 0001D8H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reload Timer 4 TMRLRB4 [R/W] H TMCSR4 [R/W] B, H,W 0001DCH XXXXXXXX XXXXXXXX E0H to 0001ECH 0001F0H 0001F4H 0001F8H 0001FCH H to H 00023CH H H H 00024CH H H Reserved TMRLRA5 [R/W] H XXXXXXXX XXXXXXXX TMRLRB5 [R/W] H XXXXXXXX XXXXXXXX TMRLRA6 [R/W] H XXXXXXXX XXXXXXXX TMRLRB6 [R/W] H XXXXXXXX XXXXXXXX TMR5 [R] H XXXXXXXX XXXXXXXX TMCSR5 [R/W] B, H,W TMR6 [R] H XXXXXXXX XXXXXXXX TMCSR6 [R/W] B, H,W Reload Timer 5 Reload Timer 6 Reserved DACR0 [R/W] TCCSH3 [R/W] TCCSH4 [R/W] DADR0 [R/W] DACR1 [R/W] XXXXXXXX CPCLR3 [R/W] W TCDT3 [R/W] W TCCSL3 [R/W] CPCLR4 [R/W] W TCDT4 [R/W] W TCCSL4 [R/W] DADR1 [R/W] XXXXXXXX DA Converter Free-run Timer 3 32-bit FRT Free-run Timer 4 32-bit FRT Document Number: Rev. *F Page 58 of 280

59 Address H to 0002C0H 0002C4H to 0002FCH H to Address offset value / Register name Block Reserved Reserved Reserved 00030CH H MPUCR [R/W] H H H 00031CH H DPVAR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX H DPVSR [R/W] H H DEAR [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00032CH DESR [R/W] H H PABR0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX H PACR0 [R/W] H H PABR1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX CH PACR1 [R/W] H H PABR2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX H PACR2 [R/W] H H PABR3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX CH PACR3 [R/W] H H PABR4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX H PACR4 [R/W] H H PABR5 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX CH PACR5 [R/W] H H PABR6 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX H PACR6 [R/W] H MPU [S] (Only CPU core can access this area) Document Number: Rev. *F Page 59 of 280

60 Address H Address offset value / Register name CH H to 0003ACH 0003B0H to 0003FCH H H H 00040CH H H H PABR7 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000 PACR7 [R/W] H Block MPU [S] (Only CPU core can access this area) Reserved [S] Reserved [S] ICSEL0 [R/W] ICSEL8 [R/W] ICSEL16 [R/W] ICSEL20 [R/W] IRPR0H [R] ICSEL1 [R/W] ICSEL2 [R/W] ICSEL3 [R/W] ICSEL5 [R/W] ICSEL6 [R/W] ICSEL7 [R/W] ICSEL10 [R/W] ICSEL11 [R/W] ICSEL9 [R/W] ICSEL13 [R/W] ICSEL17 [R/W] ICSEL21 [R/W] IRPR0L [R] CH IRPR4H [R] H IRPR6H [R] H IRPR8H [R] H IRPR10H [R] 00042CH IRPR12H [R] H IRPR14H [R] H ICSEL24 [R/W] H IRPR4L [R] IRPR6L [R] IRPR8L [R] IRPR10L [R] IRPR12L [R] IRPR14L [R] ICSEL25 [R/W] ICSEL14 [R/W] ICSEL18 [R/W] ICSEL22 [R/W] IRPR1H [R] IRPR3H [R] IRPR5H [R] IRPR7H [R] IRPR9H [R] IRPR11H [R] IRPR13H [R] IRPR15H [R] ICSEL26 [R/W] ICSEL15 [R/W] ICSEL19 [R/W] ICSEL23 [R/W] IRPR1L [R] IRPR3L [R] IRPR5L [R] IRPR7L [R] IRPR9L [R] IRPR11L [R] IRPR13L [R] IRPR15L [R] ICSEL27 [R/W] DMA request generation and clear Interrupt Request Batch Reading Register DMA request generation and clear 00043CH Reserved [S] Document Number: Rev. *F Page 60 of 280

61 Address H H H 00044CH H H H 00045CH H H H 00046CH H to 00047CH H Address offset value / Register name ICR00 [R/W] ICR04 [R/W] ICR08 [R/W] ICR12 [R/W] ICR16 [R/W] ICR20 [R/W] ICR24 [R/W] ICR28 [R/W] ICR32 [R/W] ICR36 [R/W] ICR40 [R/W] ICR44 [R/W] ICR01 [R/W] ICR05 [R/W] ICR09 [R/W] ICR13 [R/W] ICR17 [R/W] ICR21 [R/W] ICR25 [R/W] ICR29 [R/W] ICR33 [R/W] ICR37 [R/W] ICR41 [R/W] ICR45 [R/W] ICR02 [R/W] ICR06 [R/W] ICR10 [R/W] ICR14 [R/W] ICR18 [R/W] ICR22 [R/W] ICR26 [R/W] ICR30 [R/W] ICR34 [R/W] ICR38 [R/W] ICR42 [R/W] ICR46 [R/W] ICR03 [R/W] ICR07 [R/W] ICR11 [R/W] ICR15 [R/W] ICR19 [R/W] ICR23 [R/W] ICR27 [R/W] ICR31 [R/W] ICR35 [R/W] ICR39 [R/W] ICR43 [R/W] ICR47 [R/W] Block Interrupt Controller [S] Reserved [S] RSTRR [R] XXXX--XX RSTCR [R/W] STBCR [R/W] * Reset Control [S] Power Control [S] *: Writing STBCR by DMA is forbidden H Reserved [S] DIVR0 [R/W] DIVR1 [R/W] DIVR2 [R/W] H Clock Control [S] 00048CH Reserved [S] IORR0 [R/W] IORR1 [R/W] IORR2 [R/W] IORR3 [R/W] H IORR4 [R/W] IORR5 [R/W] IORR6 [R/W] IORR7 [R/W] DMA request by H peripheral [S] IORR8 [R/W] IORR9 [R/W] IORR10 [R/W] IORR11 [R/W] H IORR12 [R/W] IORR13 [R/W] IORR14 [R/W] IORR15 [R/W] DMA request by 00049CH peripheral [S] 0004A0H Reserved 0004A4H CANPRE [R/W] CAN prescaler 0004A8H CSCFG[R/W] CMCFG[R/W] Clock monitor control register 0004ACH ADERH0[R/W] B,H ADERL0[R/W] B,H Analog input control register Document Number: Rev. *F Page 61 of 280

62 Address 0004B0H Address offset value / Register name ADERL1[R/W] B,H Block Analog input control register B4H Reserved 0004B8H CUCR0 [R/W] CUTD0 [R/W] BCH CUTR0 [R] C0H RTC/WDT1 calibration 0004C4H 0004C8H 0004CCH to 00050CH H H CUCR1 [R/W] CUTR1 [R] CUTD1 [R/W] Reserved CSELR [R/W] PLLCR [R/W] CMONR [R] H MTMCR [R/W] CSTBR [R/W] CPUAR [R/W] 0----XXX STMCR [R/W] PTMCR [R/W] Clock Control [S] Reset Control [S] 00051CH Reserved [S] H H H 00052CH H H to CCPSSELR [R/W] CCRTSELR [R/W] CCPLLFBR [R/W] CCSSCCR0 [R/W] CCCGRCR0 [R/W] CCSSFBR0 [R/W] CCPSDIVR [R/W] CCSSFBR1 [R/W] CCSSCCR1 [R/W] H,W CCCGRCR1 [R/W] CCPMUCR0 [R/W] CCCGRCR2 [R/W] CCPMUCR1 [R/W] Clock Control 2 [S] Clock Control 2 [S] Reserved 00054CH EIRR0 [R/W] ENIR0 [R/W] ELVR0 [R/W] External Interrupt H XXXXXXXX (INT0 to 7) EIRR1 [R/W] ENIR1 [R/W] ELVR1 [R/W] External Interrupt H XXXXXXXX (INT8 to 15) H Reserved Document Number: Rev. *F Page 62 of 280

63 Address Address offset value / Register name CH H H H 00056CH H to 00057CH H H H to 00058CH H H WTHR [R/W] B,H WTCRH [R/W] B WTBRH [R/W] B --XXXXXX WTMR [R/W] B,H CSVCR [R/W] B WTDR [R/W] H WTCRM [R/W] B,H WTCRL [R/W] B,H WTBRM [R/W] B WTBRL [R/W] B XXXXXXXX XXXXXXXX WTSR [R/W] B Block Real Time Clock (RTC) Clock Supervisor Reserved REGSEL [R/W] LVD5R [R/W] LVD5F [R/W] LVD [R/W] Regulator Control / Low Voltage Detection Reserved PMUSTR [R/W] X PMUINTF0 [R/W] PMUCTLR [R/W] PMUINTF1 [R/W] PWRTMCTL [R/W] PMUINTF2 [R/W] H 00059CH to 0005BCH 0005C0H to 0005FCH H H H 00060CH H to 00063CH PMU Reserved Reserved ASR0 [R/W] W ASR1 [R/W] W XXXXXXXX XXXXXXXX XXXX-XX0 ASR2 [R/W] W XXXXXXXX XXXXXXXX XXXX-XX0 ASR3 [R/W] W XXXXXXXX XXXXXXXX XXXX-XX0 External Bus Interface [S] Reserved [S] Document Number: Rev. *F Page 63 of 280

64 Address H H H 00064CH H to 00067CH H H H 00068CH H to 0006FCH H to 00070CH H H H 00071CH H to 0007F8H 0007FCH H to 00083CH H H to H Address offset value / Register name ACR0 [R/W] W ACR1 [R/W] W XX--XX-- ACR2 [R/W] W XX--XX-- ACR3 [R/W] W XX--XX-- Block External Bus Interface [S] Reserved [S] AWR0 [R/W] W External Bus AWR1 [R/W] W Interface [S] ----XXXX XXXXXXXX XXXXXXXX XXXXX-X- AWR2 [R/W] W ----XXXX XXXXXXXX XXXXXXXX XXXXX-X- External Bus AWR3 [R/W] W Interface [S] ----XXXX XXXXXXXX XXXXXXXX XXXXX-X- Reserved [S] Reserved BPCCRA [R/W] B BPCCRB [R/W] B BPCCRC [R/W] B BPCTRA [R/W] W BPCTRB [R/W] W BPCTRC [R/W] W Bus Performance Counter Reserved BMODR [R] B, H, W XXXXXXXX Mode Register Reserved [S] FCTLR [R/W] H FSTR [R/W] B Flash Memory Register [S] Reserved [S] H 00085CH to 00087CH WREN [R/W] H Wild Register [S] Reserved [S] Document Number: Rev. *F Page 64 of 280

65 Address H H H 00088CH H H H 00089CH 0008A0H 0008A4H 0008A8H 0008ACH 0008B0H 0008B4H 0008B8H 0008BCH 0008C0H 0008C4H 0008C8H 0008CCH 0008D0H 0008D4H 0008D8H 0008DCH 0008E0H Address offset value / Register name WRAR00 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR00 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR01 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR01 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR02 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR02 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR03 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR03 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR04 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR04 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR05 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR05 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR06 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR06 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR07 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR07 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR08 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR08 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR09 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR09 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR10 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR10 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR11 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR11 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR12 [R/W] W XXXXXX XXXXXXXX XXXXXX-- Block Wild Register [S] Wild Register [S] Document Number: Rev. *F Page 65 of 280

66 Address 0008E4H 0008E8H 0008ECH 0008F0H 0008F4H 0008F8H 0008FCH H H H Address offset value / Register name TPULST [R] CH TPUTIR [R] H TPUTST [R] TPUTIE [R/W] H H 00091CH to 00092CH H H H 00093CH H H H 00094CH H WRDR12 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR13 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR13 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR14 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR14 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WRAR15 [R/W] W XXXXXX XXXXXXXX XXXXXX-- WRDR15 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX TPUUNLOCK [R/W] W TPUVST [R/W] TPUCFG [R/W] TPUTMID [R] TPUTCN10 [R/W] TPUTCN00 [R/W] TPUTCN01 [R/W] TPUTCN02 [R/W] TPUTCN03 [R/W] TPUTCN04 [R/W] TPUTCN05 [R/W] TPUTCN06 [R/W] TPUTCN07 [R/W] Block Wild Register [S] Wild Register [S] Time Protection Unit [S] Document Number: Rev. *F Page 66 of 280

67 Address H H 00095CH H H H 00096CH H H H 00097CH H H H 00098CH H to 0009FCH 000A00H to Address offset value / Register name TPUTCN11 [R/W] TPUTCN12 [R/W] TPUTCN13 [R/W] TPUTCN14 [R/W] TPUTCN15 [R/W] TPUTCN16 [R/W] TPUTCN17 [R/W] TPUTCC0 [R] TPUTCC1 [R] TPUTCC2 [R] TPUTCC3 [R] TPUTCC4 [R] TPUTCC5 [R] TPUTCC6 [R] TPUTCC7 [R] Block Time Protection Unit [S] Reserved 000BECH HSCFR [R/W] 000BF0H OCDU 000BF4H MBR [R/W] 000BF8H XXXXXXXX OCDU UER [W] 000BFCH X Document Number: Rev. *F Page 67 of 280

68 Address 000C00H 000C04H 000C08H 000C0CH 000C10H 000C14H 000C18H 000C1CH 000C20H 000C24H 000C28H 000C2CH 000C30H 000C34H 000C38H 000C3CH 000C40H 000C44H 000C48H 000C4CH 000C50H 000C54H 000C58H 000C5CH 000C60H Address offset value / Register name DCSR0 [R/W] H DCCR0 [R/W] W DTCR0 [R/W] H DSAR0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR0 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR1 [R/W] W DCSR1 [R/W] H DTCR1 [R/W] H DSAR1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR1 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR2 [R/W] W DCSR2 [R/W] H DTCR2 [R/W] H DSAR2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR2 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR3 [R/W] W DCSR3 [R/W] H DTCR3 [R/W] H DSAR3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR3 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR4 [R/W] W DCSR4 [R/W] H DTCR4 [R/W] H DSAR4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR5 [R/W] W DCSR5 [R/W] H DTCR5 [R/W] H DSAR5 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR5 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR6 [R/W] W Block DMA Controller [S] Document Number: Rev. *F Page 68 of 280

69 Address 000C64H 000C68H 000C6CH 000C70H 000C74H 000C78H 000C7CH 000C80H 000C84H 000C88H 000C8CH 000C90H 000C94H 000C98H 000C9CH 000CA0H 000CA4H 000CA8H 000CACH 000CB0H 000CB4H 000CB8H 000CBCH 000CC0H 000CC4H Address offset value / Register name DCSR6 [R/W] H DTCR6 [R/W] H DSAR6 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR6 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR7 [R/W] W DCSR7 [R/W] H DTCR7 [R/W] H DSAR7 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR7 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR8 [R/W] W DCSR8 [R/W] H DTCR8 [R/W] H DSAR8 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR8 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR9 [R/W] W DCSR9 [R/W] H DTCR9 [R/W] H DSAR9 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR9 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR10 [R/W] W DCSR10 [R/W] H DTCR10 [R/W] H DSAR10 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR10 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR11 [R/W] W DCSR11 [R/W] H DTCR11 [R/W] H DSAR11 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR11 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR12 [R/W] W DCSR12 [R/W] H DTCR12 [R/W] H Block DMA Controller [S] Document Number: Rev. *F Page 69 of 280

70 Address 000CC8H 000CCCH 000CD0H 000CD4H 000CD8H 000CDCH 000CE0H 000CE4H 000CE8H 000CECH 000CF0H 000CF4H 000CF8H 000CFCH 000D00H to Address offset value / Register name DSAR12 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR12 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR13 [R/W] W DCSR13 [R/W] H DTCR13 [R/W] H DSAR13 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR13 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR14 [R/W] W DCSR14 [R/W] H DTCR14 [R/W] H DSAR14 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR14 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DCCR15 [R/W] W DCSR15 [R/W] H DTCR15 [R/W] H DSAR15 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDAR15 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block DMA Controller [S] Reserved [S] 000DF0H 000DF4H DNMIR [R/W] B DF8H DMACR[R/W] W DILVR [R/W] B DMA Controller [S] 000DFCH Reserved [S] DDR00 [R/W] DDR01 [R/W] DDR02 [R/W] DDR03 [R/W] 000E00H Data Direction DDR04 [R/W] DDR05 [R/W] DDR06 [R/W] DDR07 [R/W] Register 000E04H DDR08 [R/W] DDR09 [R/W] DDR10 [R/W] DDR11 [R/W] 000E08H DDR12 [R/W] DDR13 [R/W] DDR14 [R/W] DDR15 [R/W] 000E0CH E10H 000E14H Data Direction Register DDR16 [R/W] DDR17 [R/W] DDR18 [R/W] DDR19 [R/W] 000E18H 000E1CH Reserved Document Number: Rev. *F Page 70 of 280

71 Address Address offset value / Register name Block PFR00 [R/W] PFR01 [R/W] PFR02 [R/W] PFR03 [R/W] 000E20H PFR04 [R/W] PFR05 [R/W] PFR06 [R/W] PFR07 [R/W] 000E24H PFR08 [R/W] PFR09 [R/W] PFR10 [R/W] PFR11 [R/W] 000E28H Port Function PFR12 [R/W] PFR13 [R/W] PFR14 [R/W] PFR15 [R/W] Register 000E2CH E30H 000E34H PFR16 [R/W] PFR17 [R/W] PFR18 [R/W] PFR19 [R/W] 000E38H 000E3CH Reserved PDDR00 [R] PDDR01 [R] PDDR02 [R] PDDR03 [R] 000E40H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PDDR04 [R] PDDR05 [R] PDDR06 [R] PDDR07 [R] 000E44H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PDDR08 [R] PDDR09 [R] PDDR10 [R] PDDR11 [R] 000E48H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Port Direct PDDR12 [R] PDDR13 [R] PDDR14 [R] PDDR15 [R] Read Register 000E4CH XXXXXXXX -XXXXXXX ---XXX-- --XXXXXX 000E50H 000E54H PDDR16 [R] PDDR17 [R] PDDR18 [R] PDDR19 [R] 000E58H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000E5CH Reserved 000E60H EPFR00 [R/W] EPFR01 [R/W] EPFR02 [R/W] EPFR03 [R/W] EPFR04 [R/W] EPFR05 [R/W] EPFR06 [R/W] EPFR07 [R/W] 000E64H EPFR08 [R/W] EPFR09 [R/W] EPFR10 [R/W] EPFR11 [R/W] 000E68H EPFR12 [R/W] EPFR13 [R/W] EPFR14 [R/W] EPFR15 [R/W] 000E6CH E70H 000E74H EPFR26 [R/W] EPFR27 [R/W] 000E78H E7CH 000E80H EPFR28 [R/W] EPFR29 [R/W] EPFR33 [R/W] EPFR34 [R/W] EPFR35 [R/W] Extended Port Function Register Document Number: Rev. *F Page 71 of 280

72 Address 000E84H Address offset value / Register name EPFR36 [R/W] E88H 000E8CH EPFR44 [R/W] EPFR45 [R/W] EPFR42 [R/W] EPFR43 [R/W] E90H 000E94H 000E98H EPFR56 [R/W] EPFR57 [R/W] EPFR58 [R/W] EPFR59 [R/W] E9CH 000EA0H to EPFR60 [R/W] EPFR61 [R/W] EPFR62 [R/W] EPFR63 [R/W] Block Extended Port Function Register Reserved 000EBCH PPER00 [R/W] PPER01 [R/W] PPER02 [R/W] PPER03 [R/W] 000EC0H PPER04 [R/W] PPER05 [R/W] PPER06 [R/W] PPER07 [R/W] 000EC4H PPER08 [R/W] PPER09 [R/W] PPER10 [R/W] PPER11 [R/W] 000EC8H PPER12 [R/W] PPER13 [R/W] PPER14 [R/W] PPER15 [R/W] 000ECCH ED0H 000ED4H PPER16 [R/W] PPER17 [R/W] PPER18 [R/W] PPER19 [R/W] 000ED8H 000EDCH to 000F3CH 000F40H 000F44H 000F48H to 000F64H Port Pull-up/down Enable Register Reserved PORTEN [R/W] Port Enable Register KEYCDR [R/W] H KeyCodeRegister Reserved Document Number: Rev. *F Page 72 of 280

73 Address 000F68H 000F6CH 000F70H 000F74H 000F78H to 000F7CH 000F80H 000F84H Address offset value / Register name MSCY6 [R] H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX MSCY7 [R] H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX RCRH0 [W] H,W RCRL0 [W] UDCRH0 [R] H,W UDCRL0 [R] XXXXXXXX XXXXXXXX CCR0 [R/W] B,H CSR0 [R/W] B Block Input Capture 6,7 Cycle measurement data register 67 Up/Down Counter 0 Reserved RCRH1 [W] H,W RCRL1 [W] XXXXXXXX XXXXXXXX CCR1 [R/W] B,H F88H 000F8CH UDCRH1 [R] H,W MSCH45 [R] MSCH67 [R] UDCRL1 [R] CSR1 [R/W] B MSCL45 [R/W] MSCL67 [R/W] Up/Down Counter 1 Input Capture 4,5 32-bit ICU Cycle and pulse width measurement control 45 Input Capture 6,7 32-bit ICU Cycle and pulse width measurement control F90H OCCP10 [R/W] W Output Compare 10,11 000F94H OCCP11 [R/W] W 32-bit OCU 000F98H OCSH1011 [R/W] OCSL1011 [R/W] Output Compare 10,11 32-bit OCU F9CH 000FA0H 000FA4H 000FA8H 000FACH to TCCSH5 [R/W] CPCLR5 [R/W] W TCDT5 [R/W] W TCCSL5 [R/W] OCLS1011 [R/W] OCU1011 Output level control register Free-run Timer 5 32-bit FRT Reserved 000FCCH 000FD0H IPCP4 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000FD4H IPCP5 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000FD8H LSYNS1 [R/W] ICS45 [R/W] Input Capture 4,5 32-bit ICU Document Number: Rev. *F Page 73 of 280

74 Address Address offset value / Register name FDCH IPCP6 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000FE0H IPCP7 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000FE4H ICS67 [R/W] 000FE8H IPCP8 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000FECH IPCP9 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000FF0H ICS89 [R/W] 000FF4H MSCY8 [R] H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000FF8H 000FFCH H H to 00112CH SACR [R/W] MSCY9 [R] H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PICD [R/W] MSCH89 [R] MSCL89 [R/W] Block Input Capture 6,7 32-bit ICU Input Capture 8,9 32-bit ICU Input Capture 8,9 32-bit ICU Cycle measurement data register 89 Cycle and pulse width measurement control 89 Clock Control Reserved H H H 00113CH H to 0011FCH H H H 00120CH H H H CRCINIT [R/W] CRCIN [R/W] CRCR [R] CRCCR [R/W] CRC calculation unit Reserved TCGS [R/W] TCGSE [R/W] CPCLRB0/CPCLR0 [W] H,W TCDT0 [R/W] H,W TCCS0 [R/W] CPCLRB1/CPCLR1 [W] H,W TCDT1 [R/W] H,W TCCS1 [R/W] CPCLRB2/CPCLR2 [W] H,W TCDT2 [R/W] H,W TCCS2 [R/W] bit Free-run timer synchronous activation 16-bit Free-run Timer 0 16-bit Free-run Timer 1 16-bit Free-run Timer 2 Document Number: Rev. *F Page 74 of 280

75 Address 00121CH to H H H 00123CH H H Address offset value / Register name Block Reserved FRS0 [R/W] FRS1 [R/W] FRS2 [R/W] FRS3 [R/W] FRS4 [R/W] bit Free-run timer selection H Reserved 00124CH OCCPB0/OCCP0 [R/W] H,W OCCPB1/OCCP1 [R/W] H,W H OCMOD01 [R/W] 16-bit Output compare 0/1 OCS01 [R/W] H OCCPB2/OCCP2 [R/W] H,W OCCPB3/OCCP3 [R/W] H,W H OCMOD23 [R/W] 16-bit Output compare 2/3 OCS23 [R/W] CH OCCPB4/OCCP4 [R/W] H,W OCCPB5/OCCP5 [R/W] H,W H OCMOD45 [R/W] 16-bit Output compare 4/5 OCS45 [R/W] H to H 00127CH H H H 00128CH to H Reserved IPCP0 [R] H,W ICS01 [R/W] IPCP2 [R] H,W ICS23 [R/W] IPCP1 [R] H,W LSYNS [R/W] IPCP3 [R] H,W 16-bit Input capture 0/1 16-bit Input capture 2/3 Reserved 00129CH Reserved Document Number: Rev. *F Page 75 of 280

76 Address 0012A0H 0012A4H 0012A8H 0012ACH 0012B0H 0012B4H 0012B8H to 0012CCH 0012D0H 0012D4H 0012D8H 0012DCH to 0012FCH Address offset value / Register name TMRR0 [R/W] H,W TMRR2 [R/W] H,W DTSCR0 [R/W] DTSCR1 [R/W] DTIR0 [R/W] DTSCR2 [R/W] SIGCR10 [R/W] PICS0 [R/W] TMRR1 [R/W] H,W DTMNS0 [R/W] SIGCR20 [R/W] Block Waveform generator 0/1/2 Reserved FRS5 [R/W] FRS6 [R/W] FRS7 [R/W] bit Free-run timer selection A/D activation compare 16-bit Free-run timer selection A/D activation compare Reserved H Reserved H ADTSS0[R/W] H ADTSE0[R/W] 00130CH ADCOMP0/ADCOMPB0[R/W] H,W ADCOMP1/ADCOMPB1[R/W] H,W H ADCOMP2/ADCOMPB2[R/W] H,W ADCOMP3/ADCOMPB3[R/W] H,W H ADCOMP4/ADCOMPB4[R/W] H,W ADCOMP5/ADCOMPB5[R/W] H,W 12-bit A/D converter 1/2 unit H ADCOMP6/ADCOMPB6[R/W] H,W ADCOMP7/ADCOMPB7[R/W] H,W 00131CH ADCOMP8/ADCOMPB8[R/W] H,W ADCOMP9/ADCOMPB9[R/W] H,W H ADCOMP10/ADCOMPB10[R/W] H,W ADCOMP11/ADCOMPB11[R/W] H,W H ADCOMP12/ADCOMPB12[R/W] H,W ADCOMP13/ADCOMPB13[R/W] H,W H ADCOMP14/ADCOMPB14[R/W] H,W ADCOMP15/ADCOMPB15[R/W] H,W Document Number: Rev. *F Page 76 of 280

77 Address 00132CH H H H 00133CH H H H 00134CH H H H 00135CH H H H 00136CH H H H 00137CH H H H 00138CH Address offset value / Register name ADCOMP16/ADCOMPB16[R/W] H,W ADCOMP18/ADCOMPB18[R/W] H,W ADCOMP20/ADCOMPB20[R/W] H,W ADCOMP22/ADCOMPB22[R/W] H,W ADCOMP24/ADCOMPB24[R/W] H,W ADCOMP26/ADCOMPB26[R/W] H,W ADCOMP28/ADCOMPB28[R/W] H,W ADCOMP30/ADCOMPB30[R/W] H,W ADTCS0[R/W] ADTCS2[R/W] ADTCS4[R/W] ADTCS6[R/W] ADTCS8[R/W] ADTCS10[R/W] ADTCS12[R/W] ADTCS14[R/W] ADTCS16[R/W] ADTCS18[R/W] ADTCS20[R/W] ADTCS22[R/W] ADTCS24[R/W] ADTCS26[R/W] ADTCS28[R/W] ADTCS30[R/W] ADTCD0[R] ADCOMP17/ADCOMPB17[R/W] H,W ADCOMP19/ADCOMPB19[R/W] H,W ADCOMP21/ADCOMPB21[R/W] H,W ADCOMP23/ADCOMPB23[R/W] H,W ADCOMP25/ADCOMPB25[R/W] H,W ADCOMP27/ADCOMPB27[R/W] H,W ADCOMP29/ADCOMPB29[R/W] H,W ADCOMP31/ADCOMPB31[R/W] H,W ADTCS1[R/W] ADTCS3[R/W] ADTCS5[R/W] ADTCS7[R/W] ADTCS9[R/W] ADTCS11[R/W] ADTCS13[R/W] ADTCS15[R/W] ADTCS17[R/W] ADTCS19[R/W] ADTCS21[R/W] ADTCS23[R/W] ADTCS25[R/W] ADTCS27[R/W] ADTCS29[R/W] ADTCS31[R/W] ADTCD1[R] Block 12-bit A/D converter 1/2 unit Document Number: Rev. *F Page 77 of 280

78 Address H H H 00139CH 0013A0H 0013A4H 0013A8H 0013ACH 0013B0H 0013B4H 0013B8H 0013BCH 0013C0H 0013C4H 0013C8H 0013CCH 0013D0H 0013D4H 0013D8H 0013DCH 0013E0H 0013E4H 0013E8H 0013ECH 0013F0H Address offset value / Register name ADTCD2[R] ADTCD4[R] ADTCD6[R] ADTCD8[R] ADTCD10[R] ADTCD12[R] ADTCD14[R] ADTCD16[R] ADTCD18[R] ADTCD20[R] ADTCD22[R] ADTCD24[R] ADTCD26[R] ADTCD28[R] ADTCD30[R] ADTECS0[R/W] ADTECS2[R/W] ADTECS4[R/W] ADTECS6[R/W] ADTECS8[R/W] ADTECS10[R/W] ADTECS12[R/W] ADTECS14[R/W] ADTECS16[R/W] ADTECS18[R/W] ADTCD3[R] ADTCD5[R] ADTCD7[R] ADTCD9[R] ADTCD11[R] ADTCD13[R] ADTCD15[R] ADTCD17[R] ADTCD19[R] ADTCD21[R] ADTCD23[R] ADTCD25[R] ADTCD27[R] ADTCD29[R] ADTCD31[R] ADTECS1[R/W] ADTECS3[R/W] ADTECS5[R/W] ADTECS7[R/W] ADTECS9[R/W] ADTECS11[R/W] ADTECS13[R/W] ADTECS15[R/W] ADTECS17[R/W] ADTECS19[R/W] Block 12-bit A/D converter 1/2 unit Document Number: Rev. *F Page 78 of 280

79 Address 0013F4H 0013F8H 0013FCH H H H 00140CH H H H 00141CH H H H 00142CH H H H 00143CH H H Address offset value / Register name ADTECS20[R/W] ADTECS22[R/W] ADTECS24[R/W] ADTECS26[R/W] ADTECS28[R/W] ADTECS30[R/W] ADRCUT0[R/W] ADRCUT1[R/W] ADRCUT2[R/W] ADRCUT3[R/W] ADRCCS0[R/W] ADRCCS4[R/W] ADRCCS8[R/W] ADRCCS12[R/W] ADRCCS16[R/W] ADRCCS20[R/W] ADRCCS24[R/W] ADRCCS28[R/W] ADSCANS0[R/W] ADRCCS1[R/W] ADRCCS5[R/W] ADRCCS9[R/W] ADRCCS13[R/W] ADRCCS17[R/W] ADRCCS21[R/W] ADRCCS25[R/W] ADRCCS29[R/W] ADTECS21[R/W] ADTECS23[R/W] ADTECS25[R/W] ADTECS27[R/W] ADTECS29[R/W] ADTECS31[R/W] ADRCLT0[R/W] ADRCLT1[R/W] ADRCLT2[R/W] ADRCLT3[R/W] ADRCCS2[R/W] ADRCCS6[R/W] ADRCCS10[R/W] ADRCCS14[R/W] ADRCCS18[R/W] ADRCCS22[R/W] ADRCCS26[R/W] ADRCCS30[R/W] ADRCOT0[R] ADRCIF0[R,W] ADRCCS3[R/W] ADRCCS7[R/W] ADRCCS11[R/W] ADRCCS15[R/W] ADRCCS19[R/W] ADRCCS23[R/W] ADRCCS27[R/W] ADRCCS31[R/W] Block 12-bit A/D converter 1/2 unit Document Number: Rev. *F Page 79 of 280

80 Address H 00144CH H H H 00145CH H H H 00146CH H H H 00147CH H H H 00148CH H H H to 0014B4H Address offset value / Register name ADNCS0[R/W] ADNCS4[R/W] ADNCS8[R/W] ADNCS12[R/W] ADSTPCS0[R/W] ADSTPCS4[R/W] ADNCS1[R/W] ADNCS5[R/W] ADNCS9[R/W] ADNCS13[R/W] ADNCS2[R/W] ADNCS6[R/W] ADNCS10[R/W] ADNCS14[R/W] ADNCS3[R/W] ADNCS7[R/W] ADNCS11[R/W] ADNCS15[R/W] Block ADPRTF0[R] 12-bit A/D converter 1/2 unit ADEOCF0[R] ADCS0[R] ADCH0[R] ADMD0[R/W] ADSTPCS1[R/W] ADSTPCS5[R/W] ADSTPCS2[R/W] ADSTPCS6[R/W] ADSTPCS3[R/W] ADSTPCS7[R/W] ADTSS1[R/W] ADTSE1[R/W] ADCOMP32/ADCOMPB32[R/W] H,W ADCOMP33/ADCOMPB33[R/W] H,W ADCOMP34/ADCOMPB34[R/W] H,W ADCOMP35/ADCOMPB35[R/W] H,W ADCOMP36/ADCOMPB36[R/W] H,W ADCOMP37/ADCOMPB37[R/W] H,W ADCOMP38/ADCOMPB38[R/W] H,W ADCOMP39/ADCOMPB39[R/W] H,W ADCOMP40/ADCOMPB40[R/W] H,W ADCOMP41/ADCOMPB41[R/W] H,W ADCOMP42/ADCOMPB42[R/W] H,W ADCOMP43/ADCOMPB43[R/W] H,W ADCOMP44/ADCOMPB44[R/W] H,W ADCOMP45/ADCOMPB45[R/W] H,W ADCOMP46/ADCOMPB46[R/W] H,W ADCOMP47/ADCOMPB47[R/W] H,W 12-bit A/D converter 2/2 unit 12-bit A/D converter 2/2 unit Reserved Document Number: Rev. *F Page 80 of 280

81 Address 0014B8H 0014BCH 0014C0H 0014C4H 0014C8H 0014CCH 0014D0H 0014D4H 0014D8H to 0014F4H 0014F8H 0014FCH H H H 00150CH H H H to H Address offset value / Register name ADTCS32[R/W] ADTCS34[R/W] ADTCS36[R/W] ADTCS38[R/W] ADTCS40[R/W] ADTCS42[R/W] ADTCS44[R/W] ADTCS46[R/W] ADTCS33[R/W] ADTCS35[R/W] ADTCS37[R/W] ADTCS39[R/W] ADTCS41[R/W] ADTCS43[R/W] ADTCS45[R/W] ADTCS47[R/W] Block 12-bit A/D converter 2/2 unit Reserved ADTCD32[R] ADTCD34[R] ADTCD36[R] ADTCD38[R] ADTCD40[R] ADTCD42[R] ADTCD44[R] ADTCD46[R] ADTCD33[R] ADTCD35[R] ADTCD37[R] ADTCD39[R] ADTCD41[R] ADTCD43[R] ADTCD45[R] ADTCD47[R] bit A/D converter 2/2 unit 12-bit A/D converter 2/2 unit Reserved Document Number: Rev. *F Page 81 of 280

82 Address H 00153CH H H H 00154CH H H H to H H 00157CH H H H 00158CH H H H to 0015A4H 0015A8H 0015ACH 0015B0H Address offset value / Register name ADTECS32[R/W] ADTECS34[R/W] ADTECS36[R/W] ADTECS38[R/W] ADTECS40[R/W] ADTECS42[R/W] ADTECS44[R/W] ADTECS46[R/W] ADTECS33[R/W] ADTECS35[R/W] ADTECS37[R/W] ADTECS39[R/W] ADTECS41[R/W] ADTECS43[R/W] ADTECS45[R/W] ADTECS47[R/W] Block 12-bit A/D converter 2/2 unit Reserved ADRCUT4[R/W] ADRCUT5[R/W] ADRCUT6[R/W] ADRCUT7[R/W] ADRCCS32[R/W] ADRCCS36[R/W] ADRCCS40[R/W] ADRCCS44[R/W] ADRCCS33[R/W] ADRCCS37[R/W] ADRCCS41[R/W] ADRCCS45[R/W] ADRCLT4[R/W] ADRCLT5[R/W] ADRCLT6[R/W] ADRCLT7[R/W] ADRCCS34[R/W] ADRCCS38[R/W] ADRCCS42[R/W] ADRCCS46[R/W] ADRCCS35[R/W] ADRCCS39[R/W] ADRCCS43[R/W] ADRCCS47[R/W] 12-bit A/D converter 2/2 unit 12-bit A/D converter 2/2 unit Reserved ADSCANS1 [R/W] ADRCOT1 [R] ADRCIF1 [R,W] bit A/D converter 2/2 unit Document Number: Rev. *F Page 82 of 280

83 Address 0015B4H 0015B8H Address offset value / Register name ADNCS16 [R/W] ADNCS20 [R/W] ADNCS17 [R/W] ADNCS21 [R/W] ADNCS18 [R/W] ADNCS22 [R/W] ADNCS19 [R/W] ADNCS23 [R/W] BCH 0015C0H 0015C4H ADPRTF1 [R] 12-bit A/D converter 2/2 unit C8H ADEOCF1 [R] CCH ADCS1 [R] ADCH1 [R] ADMD1 [R/W] D0H 0015D4H to 00174CH H H H 00175CH H H H 00176CH H H ADSTPCS8 [R/W] ADSTPCS9 [R/W] ADSTPCS10 [R/W] ADSTPCS11 [R/W] Block Reserved SCR0/(IBCR0)[R/W] SMR0[R/W] /(RDR10/(TDR10))[R/W] *3 SACSR0[R/W] STMCR0[R/W] /(SCSTR30)/ (LAMSR0) [R/W] *3 /(TBYTE30)/ (LAMESR0) [R/W] *3 FCR10[R/W] BGR0[R/W] H, W FTICR0[R/W] /(SCSTR20)/ (LAMCR0) [R/W] *3 /(SCSFR20) [R/W] *3 /(TBYTE20) /(LAMERT0) [R/W] *3 FCR00[R/W] SSR0[R/W] ESCR0/(IBSR0)[R/W ] RDR00/(TDR00)[R/W] *1 STMR0[R] /(SCSCR0/SFUR0)[R/W] *3 *4 /(SCSTR10) /(SCSTR00)/ /(SFLR10) (SFLR00) [R/W] [R/W] * *3 /(SCSFR10) [R/W] *3 /(TBYTE10)/ (LAMIER0) [R/W] *3 /(ISMK0) [R/W] *2 /(SCSFR00) [R/W] *3 TBYTE00/(LAMRID0) / (LAMTID0) [R/W] FBYTE0[R/W] /(ISBA0) [R/W] *2 Multi-UART0 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I 2 C mode is not set immediately after reset. *3: Reserved because CSIO mode is not set immediately after reset. *4: Reserved because LIN2.1 mode is not set immediately after reset. Document Number: Rev. *F Page 83 of 280

84 Address H 00177CH H H H 00178CH H H H 00179CH Address offset value / Register name SCR1/(IBCR1) [R/W] SMR1[R/W] /(RDR11/(TDR11))[R/W] *3 SACSR1[R/W] STMCR1[R/W] /(SCSTR31)/ (LAMSR1) [R/W] *3 /(TBYTE31)/ (LAMESR1) [R/W] *3 FCR11[R/W] /(SCSTR21)/ (LAMCR1) [R/W] *3 /(SCSFR21)[R/W] *3 BGR1[R/W] H,W FTICR1[R/W] /(TBYTE21)/ (LAMERT1) [R/W] *3 FCR01[R/W] SSR1[R/W] Block ESCR1/(IBSR1)[R/W ] Multi-UART1 RDR01/(TDR01)[R/W] *1 STMR1[R] Multi-UART1 /(SCSCR1/SFUR1)[R/W] *3 * /(SCSTR11)/ /(SCSTR01)/ (SFLR11) (SFLR01) [R/W] [R/W] * *3 /(SCSFR11) [R/W] *3 /(TBYTE11)/ (LAMIER1) [R/W] *3 /(ISMK1)[R/W] *2 FBYTE1[R/W] /(SCSFR01) [R/W] *3 TBYTE01/(LAMRID1) / (LAMTID1) [R/W] /(ISBA1)[R/W] *2 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I 2 C mode is not set immediately after reset. Multi-UART1 *3: Reserved because CSIO mode is not set immediately after reset. *4: Reserved because LIN2.1 mode is not set immediately after reset. Document Number: Rev. *F Page 84 of 280

85 Address 0017A0H 0017A4H 0017A8H 0017ACH 0017B0H 0017B4H 0017B8H 0017BCH 0017C0H 0017C4H Address offset value / Register name SCR2/(IBCR2)[R/W] SMR2[R/W] /(RDR12/(TDR12))[R/W] *3 SACSR2[R/W] STMCR2[R/W] /(SCSTR32)/ (LAMSR2) [R/W] *3 /(TBYTE32)/ (LAMESR2) [R/W] *3 FCR12[R/W] BGR2[R/W] H, W FTICR2[R/W] /(SCSTR22)/ (LAMCR2) [R/W] *3 /(SCSFR22) [R/W] *3 /(TBYTE22)/ (LAMERT2) [R/W] *3 FCR02[R/W] SSR2[R/W] ESCR2/(IBSR2)[R/W ] RDR02/(TDR02)[R/W] *1 STMR2[R] /(SCSCR2/SFUR2)[R/W] *3 * /(SCSTR12)/ /(SCSTR02)/ (SFLR12) (SFLR02) [R/W] [R/W] * *3 /(SCSFR12) [R/W] *3 /(TBYTE12)/ (LAMIER2) [R/W] *3 /(ISMK2)[R/W] *2 FBYTE2[R/W] /(SCSFR02) [R/W] *3 TBYTE02/(LAMRID2) / (LAMTID2) [R/W] /(ISBA2)[R/W] *2 Block Multi-UART2 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I 2 C mode is not set immediately after reset. *3: Reserved because CSIO mode is not set immediately after reset. *4: Reserved because LIN2.1 mode is not set immediately after reset. Multi-UART2 Document Number: Rev. *F Page 85 of 280

86 Address 0017C8H 0017CCH 0017D0H 0017D4H 0017D8H 0017DCH 0017E0H 0017E4H 0017E8H 0017ECH 0017F0H 0017F4H 0017F8H 0017FCH H Address offset value / Register name SCR3/(IBCR3) [R/W] SMR3[R/W] /(RDR13/(TDR13))[R/W] *3 SACSR3[R/W] STMCR3[R/W] /(SCSTR33)/ (LAMSR3) [R/W] *3 /(TBYTE33)/ (LAMESR3) [R/W] *3 FCR13[R/W] BGR3[R/W] H, W FTICR3[R/W] SCR4/(IBCR4) [R/W] /(SCSTR23)/ (LAMCR3) [R/W] *3 /(SCSFR23) [R/W] *3 /(TBYTE23)/ (LAMERT3) [R/W] *3 FCR03[R/W] SMR4[R/W] /(RDR14/(TDR14))[R/W] *3 SACSR4[R/W] STMCR4[R/W] /(SCSTR34)/ (LAMSR4) [R/W] *3 /(SCSTR24)/ (LAMCR4) [R/W] *3 SSR3[R/W] ESCR3/(IBSR3)[R/W ] RDR03/(TDR03)[R/W] *1 STMR3[R] /(SCSCR3/SFUR3)[R/W] *3 * /(SCSTR13)/ /(SCSTR03)/ (SFLR13) (SFLR03) [R/W] [R/W] * *3 /(SCSFR13) [R/W] *3 /(TBYTE13)/ (LAMIER3) [R/W] *3 /(ISMK3)[R/W] *2 SSR4[R/W] FBYTE3[R/W] /(SCSFR03) [R/W] *3 TBYTE03/(LAMRID3) / (LAMTID3) [R/W] /(ISBA3)[R/W] *2 Block Multi-UART3 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I 2 C mode is not set immediately after reset. *3: Reserved because CSIO mode is not set immediately after reset. *4: Reserved because LIN2.1 mode is not set immediately after reset. ESCR4/(IBSR4)[R/W ] Multi-UART4 RDR04/(TDR04)[R/W] *1 STMR4[R] /(SCSCR4/SFUR4)[R/W] *3 *4 /(SCSTR14)/ /(SCSTR04)/ (SFLR14) (SFLR04) [R/W] [R/W] * *3 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I 2 C mode is not set immediately after reset. Document Number: Rev. *F Page 86 of 280

87 Address H H 00180CH H H H 00181CH H H H 00182CH H H H 00183CH H Address offset value / Register name /(TBYTE34)/ (LAMESR4) [R/W] *3 FCR14[R/W] BGR4[R/W] H, W FTICR4[R/W] SCR5/(IBCR5) [R/W] /(SCSFR24) [R/W] *3 /(TBYTE24)/ (LAMERT4) [R/W] *3 FCR04[R/W] SMR5[R/W] /(RDR15/(TDR15))[R/W] *3 SACSR5[R/W] STMCR5[R/W] /(SCSTR35)/ (LAMSR5) [R/W] *3 /(TBYTE35)/ (LAMESR5) [R/W] *3 FCR15[R/W] SCR6/(IBCR6) [R/W] BGR5[R/W] H, W FTICR5[R/W] /(SCSTR25)/ (LAMCR5) [R/W] *3 /(SCSFR25) [R/W] *3 /(TBYTE25)/ (LAMERT5) [R/W] *3 FCR05[R/W] SMR6[R/W] /(SCSFR14) [R/W] *3 /(TBYTE14)/ (LAMIER4) [R/W] *3 /(ISMK4)[R/W] *2 SSR5[R/W] /(SCSFR04) [R/W] *3 TBYTE04/(LAMRID4) / (LAMTID4) [R/W] FBYTE4[R/W] /(ISBA4)[R/W] *2 ESCR5/(IBSR5)[R/W ] RDR05/(TDR05)[R/W] *1 STMR5[R] /(SCSCR5/SFUR5)[R/W] *3 *4 /(SCSTR15)/ /(SCSTR05)/ (SFLR15) (SFLR05) [R/W] [R/W] * *3 /(SCSFR15) [R/W] *3 /(TBYTE15)/ (LAMIER5) [R/W] *3 /(ISMK5)[R/W] *2 SSR6[R/W] /(SCSFR05) [R/W] *3 Block Multi-UART4 *3: Reserved because CSIO mode is not set immediately after reset. *4: Reserved because LIN2.1 mode is not set immediately after reset. Multi-UART5 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I 2 C mode is not set immediately after reset. TBYTE05/(LAMRID5) *3: Reserved because CSIO / mode is not set immediately (LAMTID5) after reset. [R/W] FBYTE5[R/W] /(ISBA5)[R/W] *2 ESCR6/(IBSR6)[R/W ] *4: Reserved because LIN2.1 mode is not set immediately after reset. Multi-UART6 Document Number: Rev. *F Page 87 of 280

88 Address H H 00184CH H H H 00185CH H H H 00186CH H H H 00187CH H Address offset value / Register name /(RDR16/(TDR16))[R/W] *3 SACSR6[R/W] STMCR6[R/W] /(SCSTR36)/ (LAMSR6) [R/W] *3 /(TBYTE36)/ (LAMESR6) [R/W] *3 FCR16[R/W] BGR6[R/W] H, W FTICR6[R/W] SCR7/(IBCR7) [R/W] /(SCSTR26)/ (LAMCR6) [R/W] *3 /(SCSFR26) [R/W] *3 /(TBYTE26)/ (LAMERT6) [R/W] *3 FCR06[R/W] SMR7[R/W] /(RDR17/(TDR17))[R/W] *3 SACSR7[R/W] STMCR7[R/W] /(SCSTR37)/ (LAMSR7) [R/W] *3 /(TBYTE37)/ (LAMESR7) [R/W] *3 /(SCSTR27)/ (LAMCR7) [R/W] *3 /(SCSFR27) [R/W] *3 /(TBYTE27)/ (LAMERT7) [R/W] *3 RDR06/(TDR06)[R/W] *1 STMR6[R] /(SCSCR6/SFUR6)[R/W] *3 *4 /(SCSTR16)/ /(SCSTR06)/ (SFLR16) (SFLR06) [R/W] [R/W] * *3 /(SCSFR16) [R/W] *3 /(TBYTE16)/ (LAMIER6) [R/W] *3 /(ISMK6)[R/W] *2 SSR7[R/W] /(SCSFR06) [R/W] *3 TBYTE06/(LAMRID6) / (LAMTID6) [R/W] FBYTE6[R/W] /(ISBA6)[R/W] *2 ESCR7/(IBSR7)[R/W ] RDR07/(TDR07)[R/W] *1 STMR7[R] /(SCSCR7/SFUR7)[R/W] *3 *4 /(SCSTR17)/ /(SCSTR07)/ (SFLR17) (SFLR07) [R/W] [R/W] * *3 /(SCSFR17) [R/W] *3 /(TBYTE17)/ (LAMIER7) [R/W] *3 /(SCSFR07) [R/W] *3 TBYTE07/(LAMRID7) / (LAMTID7) [R/W] Block Multi-UART6 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I2C mode is not set immediately after reset. *3: Reserved because CSIO mode is not set immediately after reset. *4: Reserved because LIN2.1 mode is not set immediately after reset. Multi-UART7 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I 2 C mode is not set immediately after reset. Multi-UART7 *3: Reserved because CSIO mode is not set immediately after reset. *4: Reserved because LIN2.1 mode is not set immediately after reset. Document Number: Rev. *F Page 88 of 280

89 Address H H 00188CH H H H 00189CH 0018A0H 0018A4H 0018A8H 0018ACH 0018B0H 0018B4H Address offset value / Register name FCR17[R/W] BGR7[R/W] H, W FTICR7[R/W] SCR8/(IBCR8) [R/W] FCR07[R/W] SMR8[R/W] /(RDR18/(TDR18))[R/W] *3 SACSR8[R/W] STMCR8[R/W] /(SCSTR38)/ (LAMSR8) [R/W] *3 /(TBYTE38)/ (LAMESR8) [R/W] *3 FCR18[R/W] BGR8[R/W] H,W FTICR8[R/W] /(SCSTR28)/ (LAMCR8) [R/W] *3 /(SCSFR28) [R/W] *3 /(TBYTE28)/ (LAMERT8) [R/W] *3 FCR08[R/W] /(ISMK7)[R/W] *2 SSR8[R/W] FBYTE7[R/W] /(ISBA7)[R/W] *2 ESCR8/(IBSR8)[R/W ] RDR08/(TDR08)[R/W] *1 STMR8[R] /(SCSCR8/SFUR8)[R/W] *3 *4 /(SCSTR18)/ /(SCSTR08)/ (SFLR18) (SFLR08) [R/W] [R/W] * *3 /(SCSFR18) [R/W] *3 /(TBYTE18)/ (LAMIER8) [R/W] *3 /(ISMK8)[R/W] *2 /(SCSFR08) [R/W] *3 TBYTE08/(LAMRID8) / (LAMTID8) [R/W] FBYTE8[R/W] /(ISBA8)[R/W] *2 Block Multi-UART7 Multi-UART8 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I 2 C mode is not set immediately after reset. *3: Reserved because CSIO mode is not set immediately after reset. *4: Reserved because LIN2.1 mode is not set immediately after reset. Multi-UART8 Document Number: Rev. *F Page 89 of 280

90 Address 0018B8H 0018BCH 0018C0H 0018C4H 0018C8H 0018CCH 0018D0H 0018D4H 0018D8H 0018DCH 0018E0H 0018E4H 0018E8H 0018ECH Address offset value / Register name SCR9/(IBCR9) [R/W] SMR9[R/W] /(RDR19/(TDR19))[R/W] *3 SACSR9[R/W] STMCR9[R/W] /(SCSTR39)/ (LAMSR9) [R/W] *3 /(TBYTE39)/ (LAMESR9) [R/W] *3 FCR19[R/W] SCR10/(IBCR10) [R/W] BGR9[R/W] H, W FTICR9[R/W] /(SCSTR29)/ (LAMCR9) [R/W] *3 /(SCSFR29) [R/W] *3 /(TBYTE29)/ (LAMERT9) [R/W] *3 FCR09[R/W] SMR10[R/W] /(RDR110/(TDR110))[R/W] *3 SACSR10[R/W] STMCR10[R/W] SSR9[R/W] ESCR9/(IBSR9)[R/W ] RDR09/(TDR09)[R/W] *1 STMR9[R] /(SCSCR9/SFUR9)[R/W] *3 * /(SCSTR19)/ /(SCSTR09)/ (SFLR19) (SFLR09) [R/W] [R/W] * *3 /(SCSFR19) [R/W] *3 /(TBYTE19)/ (LAMIER9) [R/W] *3 /(ISMK9)[R/W] *2 SSR10[R/W] FBYTE9[R/W] /(SCSFR09) [R/W] *3 TBYTE09/(LAMRID9) / (LAMTID9) [R/W] /(ISBA9)[R/W] *2 ESCR10/(IBSR10) [R/W] RDR010/(TDR010)[R/W] *1 STMR10[R] /(SCSCR10/SFUR10)[R/W] *3 *4 Block Multi-UART9 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I 2 C mode is not set immediately after reset. *3: Reserved because CSIO mode is not set immediately after reset. *4: Reserved because LIN2.1 mode is not set immediately after reset. Multi-UART10 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I 2 C mode is not set immediately after reset. Document Number: Rev. *F Page 90 of 280

91 Address 0018F0H 0018F4H 0018F8H 0018FCH H H H 00190CH H H H 00191CH H H H 00192CH H to 0019D8H Address offset value / Register name /(SCSTR310)/ (LAMSR10) [R/W] *3 /(TBYTE310)/ (LAMESR10) [R/W] *3 FCR110[R/W] BGR10[R/W] H, W /(SCSTR210)/ (LAMCR10) [R/W] *3 /(SCSFR210) [R/W] *3 /(TBYTE210)/ (LAMERT10) [R/W] *3 FTICR10[R/W] SCR11/(IBCR11) [R/W] FCR010[R/W] SMR11[R/W] /(RDR111/(TDR111))[R/W] *3 SACSR11[R/W] STMCR11[R/W] /(SCSTR311)/ (LAMSR11) [R/W] *3 /(TBYTE311)/ (LAMESR11) [R/W] *3 FCR111[R/W] BGR11[R/W] H, W FTICR11[R/W] /(SCSTR211)/ (LAMCR11) [R/W] *3 /(SCSFR211) [R/W] *3 /(TBYTE211)/ (LAMERT11) [R/W] *3 FCR011[R/W] /(SCSTR110)/ (SFLR110)[R/W] *3 /(SCSFR110) [R/W] *3 /(TBYTE110)/ (LAMIER10) [R/W] *3 /(ISMK10)[R/W] *2 /(SCSTR010)/ (SFLR010)[R/W] *3 /(SCSFR010) [R/W] *3 TBYTE010/(LAMRID 10)/(LAMTID10) [R/W] /(ISBA10)[R/W] *2 FBYTE10[R/W] SSR11[R/W] ESCR11/(IBSR11) [R/W] RDR011/(TDR011)[R/W] *1 STMR11[R] /(SCSCR11/SFUR11)[R/W] *3 *4 /(SCSTR111)/ /(SCSTR011)/ (SFLR111)[R/W] (SFLR011)[R/W] * *3 /(SCSFR111) [R/W] *3 /(TBYTE111)/ (LAMIER11) [R/W] *3 /(ISMK11)[R/W] *2 /(SCSFR011) [R/W] *3 TBYTE011/(LAMRID 11)/(LAMTID11) [R/W] /(ISBA11)[R/W] *2 FBYTE11[R/W] Block Multi-UART10 *3: Reserved because CSIO mode is not set immediately after reset. *4: Reserved because LIN2.1 mode is not set immediately after reset. Multi-UART11 *1: Byte access is possible only for access to lower 8 bits. *2: Reserved because I 2 C mode is not set immediately after reset. *3: Reserved because CSIO mode is not set immediately after reset. *4: Reserved because LIN2.1 mode is not set immediately after reset. Multi-UART11 Reserved Document Number: Rev. *F Page 91 of 280

92 Address 0019DCH 0019E0H Address offset value / Register name GATEC0 [R/W] GATEC4 [R/W] GATEC2 [R/W] Block PPG GATE control 0019E4H Reserved 0019E8H GTRS0 [R/W] GTRS1 [R/W] ECH GTRS2 [R/W] GTRS3 [R/W] PPG 0019F0H GTRS4 [R/W] GTRS5 [R/W] controller F4H GTRS6 [R/W] GTRS7 [R/W] F8H GTRS8 [R/W] GTRS9 [R/W] FCH GTRS10 [R/W] GTRS11 [R/W] A00H GTRS12 [R/W] GTRS13 [R/W] A04H GTRS14 [R/W] GTRS15 [R/W] PPG 001A08H GTRS16 [R/W] GTRS17 [R/W] controller A0CH GTRS18 [R/W] GTRS19 [R/W] A10H GTRS20 [R/W] GTRS21 [R/W] A14H 001A18H to 001A2CH GTRS22 [R/W] GTRS23 [R/W] Reserved 001A30H 001A34H Reserved 001A38H GTREN0 [R/W] H,W GTREN1 [R/W] H,W PPG 001A3CH GTREN2 [R/W] H,W controller 001A40H PCN0 [R/W] PCSR0 [W] H,W XXXXXXXX XXXXXXXX 001A44H PDUT0 [W] H,W PTMR0 [R] H,W XXXXXXXX XXXXXXXX A48H PCN200 [R/W] PSDR0 [R/W] H,W PPG * for communication 001A4CH PTPC0 [R/W] H,W PCMDWD0 [R/W] A50H PHCSR0 [W] H,W XXXXXXXX XXXXXXXX PLCSR0 [W] H,W XXXXXXXX XXXXXXXX Document Number: Rev. *F Page 92 of 280

93 Address 001A54H 001A58H 001A5CH 001A60H 001A64H 001A68H 001A6CH 001A70H 001A74H 001A78H 001A7CH 001A80H 001A84H 001A88H 001A8CH 001A90H 001A94H 001A98H 001A9CH 001AA0H 001AA4H 001AA8H 001AACH 001AB0H 001AB4H Address offset value / Register name PHDUT0 [W] H,W XXXXXXXX XXXXXXXX PCMDDT0 [R/W] H,W PCN1 [R/W] PDUT1 [W] H,W XXXXXXXX XXXXXXXX PCN201 [R/W] PTPC1 [R/W] H,W PHCSR1 [W] H,W XXXXXXXX XXXXXXXX PHDUT1 [W] H,W XXXXXXXX XXXXXXXX PCMDDT1 [R/W] H,W PCN2 [R/W] PDUT2 [W] H,W XXXXXXXX XXXXXXXX PCN202 [R/W] PTPC2 [R/W] H,W PHCSR2 [W] H,W XXXXXXXX XXXXXXXX PHDUT2 [W] H,W XXXXXXXX XXXXXXXX PCMDDT2 [R/W] H,W PCN3 [R/W] PDUT3 [W] H,W XXXXXXXX XXXXXXXX PCN203 [R/W] PTPC3 [R/W] H,W PHCSR3 [W] H,W XXXXXXXX XXXXXXXX PHDUT3 [W] H,W XXXXXXXX XXXXXXXX PCMDDT3 [R/W] H,W PCN4 [R/W] PDUT4 [W] H,W XXXXXXXX XXXXXXXX PLDUT0 [W] H,W XXXXXXXX XXXXXXXX PCSR1 [W] H,W XXXXXXXX XXXXXXXX PTMR1 [R] H,W PSDR1 [R/W] H,W PCMDWD1 [R/W] PLCSR1 [W] H,W XXXXXXXX XXXXXXXX PLDUT1 [W] H,W XXXXXXXX XXXXXXXX PCSR2 [W] H,W XXXXXXXX XXXXXXXX PTMR2 [R] H,W PSDR2 [R/W] H,W PCMDWD2 [R/W] PLCSR2 [W] H,W XXXXXXXX XXXXXXXX PLDUT2 [W] H,W XXXXXXXX XXXXXXXX PCSR3 [W] H,W XXXXXXXX XXXXXXXX PTMR3 [R] H,W PSDR3 [R/W] H,W PCMDWD3 [R/W] PLCSR3 [W] H,W XXXXXXXX XXXXXXXX PLDUT3 [W] H,W XXXXXXXX XXXXXXXX PCSR4 [W] H,W XXXXXXXX XXXXXXXX PTMR4 [R] H,W Block PPG0 * for communication PPG1 * for communication PPG1 * for communication PPG2 * for communication PPG2 * for communication PPG3 * for communication PPG4 Document Number: Rev. *F Page 93 of 280

94 Address 001AB8H 001ABCH 001AC0H 001AC4H 001AC8H 001ACCH 001AD0H 001AD4H 001AD8H 001ADCH 001AE0H 001AE4H 001AE8H 001AECH 001AF0H 001AF4H 001AF8H 001AFCH 001B00H 001B04H 001B08H 001B0CH 001B10H 001B14H Address offset value / Register name PCN204 [R/W] PTPC4 [R/W] H,W PCN5 [R/W] PDUT5 [W] H,W XXXXXXXX XXXXXXXX PCN205 [R/W] PTPC5 [R/W] H,W PCN6 [R/W] PDUT6 [W] H,W XXXXXXXX XXXXXXXX PCN206 [R/W] PTPC6 [R/W] H,W PCN7 [R/W] PDUT7 [W] H,W XXXXXXXX XXXXXXXX PCN207 [R/W] PTPC7 [R/W] H,W PCN8 [R/W] PDUT8 [W] H,W XXXXXXXX XXXXXXXX PCN208 [R/W] PTPC8 [R/W] H,W PCN9 [R/W] PDUT9 [W] H,W XXXXXXXX XXXXXXXX PCN209 [R/W] PTPC9 [R/W] H,W PCN10 [R/W] PDUT10 [W] H,W XXXXXXXX XXXXXXXX PSDR4 [R/W] H,W PCSR5 [W] H,W XXXXXXXX XXXXXXXX PTMR5 [R] H,W PSDR5 [R/W] H,W PCSR6 [W] H,W XXXXXXXX XXXXXXXX PTMR6 [R] H,W PSDR6 [R/W] H,W PCSR7 [W] H,W XXXXXXXX XXXXXXXX PTMR7 [R] H,W PSDR7 [R/W] H,W PCSR8 [W] H,W XXXXXXXX XXXXXXXX PTMR8 [R] H,W PSDR8 [R/W] H,W PCSR9 [W] H,W XXXXXXXX XXXXXXXX PTMR9 [R] H,W PSDR9 [R/W] H,W PCSR10 [W] H,W XXXXXXXX XXXXXXXX PTMR10 [R] H,W Block PPG4 PPG5 PPG6 PPG7 PPG8 PPG9 PPG10 Document Number: Rev. *F Page 94 of 280

95 Address 001B18H 001B1CH 001B20H 001B24H 001B28H 001B2CH 001B30H 001B34H 001B38H 001B3CH 001B40H 001B44H 001B48H 001B4CH 001B50H 001B54H 001B58H 001B5CH 001B60H 001B64H 001B68H 001B6CH 001B70H 001B74H Address offset value / Register name PCN210 [R/W] PTPC10 [R/W] H,W PCN11 [R/W] PDUT11 [W] H,W XXXXXXXX XXXXXXXX PCN211 [R/W] PTPC11 [R/W] H,W PCN12 [R/W] PDUT12 [W] H,W XXXXXXXX XXXXXXXX PCN212 [R/W] PTPC12 [R/W] H,W PCN13 [R/W] PDUT13 [W] H,W XXXXXXXX XXXXXXXX PCN213 [R/W] PTPC13 [R/W] H,W PCN14 [R/W] PDUT14 [W] H,W XXXXXXXX XXXXXXXX PCN214 [R/W] PTPC14 [R/W] H,W PCN15 [R/W] PDUT15 [W] H,W XXXXXXXX XXXXXXXX PCN215 [R/W] PTPC15 [R/W] H,W PCN16 [R/W] PDUT16 [W] H,W XXXXXXXX XXXXXXXX PSDR10 [R/W] H,W PCSR11 [W] H,W XXXXXXXX XXXXXXXX PTMR11 [R] H,W PSDR11 [R/W] H,W PCSR12 [W] H,W XXXXXXXX XXXXXXXX PTMR12 [R] H,W PSDR12 [R/W] H,W PCSR13 [W] H,W XXXXXXXX XXXXXXXX PTMR13 [R] H,W PSDR13 [R/W] H,W PCSR14 [W] H,W XXXXXXXX XXXXXXXX PTMR14 [R] H,W PSDR14 [R/W] H,W PCSR15 [W] H,W XXXXXXXX XXXXXXXX PTMR15 [R] H,W PSDR15 [R/W] H,W PCSR16 [W] H,W XXXXXXXX XXXXXXXX PTMR16 [R] H,W Block PPG10 PPG11 PPG11 PPG12 PPG13 PPG14 PPG15 PPG16 Document Number: Rev. *F Page 95 of 280

96 Address 001B78H 001B7CH 001B80H 001B84H 001B88H 001B8CH 001B90H 001B94H 001B98H 001B9CH 001BA0H 001BA4H 001BA8H 001BACH 001BB0H 001BB4H 001BB8H 001BBCH 001BC0H 001BC4H 001BC8H 001BCCH Address offset value / Register name PCN216 [R/W] PTPC16 [R/W] H,W PCN17 [R/W] PDUT17 [W] H,W XXXXXXXX XXXXXXXX PCN217 [R/W] PTPC17 [R/W] H,W PCN18 [R/W] PDUT18 [W] H,W XXXXXXXX XXXXXXXX PCN218 [R/W] PTPC18 [R/W] H,W PCN19 [R/W] PDUT19 [W] H,W XXXXXXXX XXXXXXXX PCN219 [R/W] PTPC19 [R/W] H,W PCN20 [R/W] PDUT20 [W] H,W XXXXXXXX XXXXXXXX PCN220 [R/W] PTPC20 [R/W] H,W PCN21 [R/W] PDUT21 [W] H,W XXXXXXXX XXXXXXXX PCN221 [R/W] PTPC21 [R/W] H,W PSDR16 [R/W] H,W PCSR17 [W] H,W XXXXXXXX XXXXXXXX PTMR17 [R] H,W PSDR17 [R/W] H,W PCSR18 [W] H,W XXXXXXXX XXXXXXXX PTMR18 [R] H,W PSDR18 [R/W] H,W PCSR19 [W] H,W XXXXXXXX XXXXXXXX PTMR19 [R] H,W PSDR19 [R/W] H,W PCSR20 [W] H,W XXXXXXXX XXXXXXXX PTMR20 [R] H,W PSDR20 [R/W] H,W PCSR21 [W] H,W XXXXXXXX XXXXXXXX PTMR21 [R] H,W PSDR21 [R/W] H,W Block PPG16 PPG17 PPG18 PPG19 PPG20 PPG21 PPG21 Document Number: Rev. *F Page 96 of 280

97 Address 001BD0H 001BD4H 001BD8H 001BDCH 001BE0H 001BE4H 001BE8H 001BECH 001BF0H 001BF4H 001BF8H 001BFCH 001C00H 001C04H 001C08H 001C0CH 001C10H 001C14H 001C18H 001C1CH 001C20H 001C24H 001C28H 001C2CH Address offset value / Register name PCN22 [R/W] PDUT22 [W] H,W XXXXXXXX XXXXXXXX PCN222 [R/W] PTPC22 [R/W] H,W PCN23 [R/W] PDUT23 [W] H,W XXXXXXXX XXXXXXXX PCN223 [R/W] PTPC23 [R/W] H,W PCN24 [R/W] PDUT24 [W] H,W XXXXXXXX XXXXXXXX PCN224 [R/W] PTPC24 [R/W] H,W PCN25 [R/W] PDUT25 [W] H,W XXXXXXXX XXXXXXXX PCN225 [R/W] PTPC25 [R/W] H,W PCN26 [R/W] PDUT26 [W] H,W XXXXXXXX XXXXXXXX PCN226 [R/W] PTPC26 [R/W] H,W PCN27 [R/W] PDUT27 [W] H,W XXXXXXXX XXXXXXXX PCN227 [R/W] PTPC27 [R/W] H,W PCSR22 [W] H,W XXXXXXXX XXXXXXXX PTMR22 [R] H,W PSDR22 [R/W] H,W PCSR23 [W] H,W XXXXXXXX XXXXXXXX PTMR23 [R] H,W PSDR23 [R/W] H,W PCSR24 [W] H,W XXXXXXXX XXXXXXXX PTMR24 [R] H,W PSDR24 [R/W] H,W PCSR25 [W] H,W XXXXXXXX XXXXXXXX PTMR25 [R] H,W PSDR25 [R/W] H,W PCSR26 [W] H,W XXXXXXXX XXXXXXXX PTMR26 [R] H,W PSDR26 [R/W] H,W PCSR27 [W] H,W XXXXXXXX XXXXXXXX PTMR27 [R] H,W PSDR27 [R/W] H,W Block PPG22 PPG23 PPG24 PPG25 PPG26 PPG27 PPG27 PPG27 Document Number: Rev. *F Page 97 of 280

98 Address 001C30H 001C34H 001C38H 001C3CH 001C40H 001C44H 001C48H 001C4CH 001C50H 001C54H 001C58H 001C5CH 001C60H 001C64H 001C68H 001C6CH 001C70H 001C74H 001C78H 001C7CH 001C80H 001C84H 001C88H 001C8CH Address offset value / Register name PCN28 [R/W] PDUT28 [W] H,W XXXXXXXX XXXXXXXX PCN228 [R/W] PTPC28 [R/W] H,W PCN29 [R/W] PDUT29 [W] H,W XXXXXXXX XXXXXXXX PCN229 [R/W] PTPC29 [R/W] H,W PCN30 [R/W] PDUT30 [W] H,W XXXXXXXX XXXXXXXX PCN230 [R/W] PTPC30 [R/W] H,W PCN31 [R/W] PDUT31 [W] H,W XXXXXXXX XXXXXXXX PCN231 [R/W] PTPC31 [R/W] H,W PCN32 [R/W] PDUT32 [W] H,W XXXXXXXX XXXXXXXX PCN232 [R/W] PTPC32 [R/W] H,W PCN33 [R/W] PDUT33 [W] H,W XXXXXXXX XXXXXXXX PCN233 [R/W] PTPC33 [R/W] H,W PCSR28 [W] H,W XXXXXXXX XXXXXXXX PTMR28 [R] H,W PSDR28 [R/W] H,W PCSR29 [W] H,W XXXXXXXX XXXXXXXX PTMR29 [R] H,W PSDR29 [R/W] H,W PCSR30 [W] H,W XXXXXXXX XXXXXXXX PTMR30 [R] H,W PSDR30 [R/W] H,W PCSR31 [W] H,W XXXXXXXX XXXXXXXX PTMR31 [R] H,W PSDR31 [R/W] H,W PCSR32 [W] H,W XXXXXXXX XXXXXXXX PTMR32 [R] H,W PSDR32 [R/W] H,W PCSR33 [W] H,W XXXXXXXX XXXXXXXX PTMR33 [R] H,W PSDR33 [R/W] H,W Block PPG28 PPG29 PPG30 PPG31 PPG32 PPG32 PPG33 PPG33 Document Number: Rev. *F Page 98 of 280

99 Address 001C90H 001C94H 001C98H 001C9CH 001CA0H 001CA4H 001CA8H 001CACH 001CB0H 001CB4H 001CB8H 001CBCH 001CC0H 001CC4H 001CC8H 001CCCH 001CD0H 001CD4H 001CD8H 001CDCH 001CE0H 001CE4H 001CE8H 001CECH Address offset value / Register name PCN34 [R/W] PDUT34 [W] H,W XXXXXXXX XXXXXXXX PCN234 [R/W] PTPC34 [R/W] H,W PCN35 [R/W] PDUT35 [W] H,W XXXXXXXX XXXXXXXX PCN235 [R/W] PTPC35 [R/W] H,W PCN36 [R/W] PDUT36 [W] H,W XXXXXXXX XXXXXXXX PCN236 [R/W] PTPC36 [R/W] H,W PCN37 [R/W] PDUT37 [W] H,W XXXXXXXX XXXXXXXX PCN237 [R/W] PTPC37 [R/W] H,W PCN38 [R/W] PDUT38 [W] H,W XXXXXXXX XXXXXXXX PCN238 [R/W] PTPC38 [R/W] H,W PCN39 [R/W] PDUT39 [W] H,W XXXXXXXX XXXXXXXX PCN239 [R/W] PTPC39 [R/W] H,W PCSR34 [W] H,W XXXXXXXX XXXXXXXX PTMR34 [R] H,W PSDR34 [R/W] H,W PCSR35 [W] H,W XXXXXXXX XXXXXXXX PTMR35 [R] H,W PSDR35 [R/W] H,W PCSR36 [W] H,W XXXXXXXX XXXXXXXX PTMR36 [R] H,W PSDR36 [R/W] H,W PCSR37 [W] H,W XXXXXXXX XXXXXXXX PTMR37 [R] H,W PSDR37 [R/W] H,W Block PPG34 PPG35 PPG36 PPG37 PPG37 PCSR38 [W] H,W XXXXXXXX XXXXXXXX PTMR38 [R] H,W PSDR38 [R/W] H,W PCSR39 [W] H,W XXXXXXXX XXXXXXXX PTMR39 [R] H,W PSDR39 [R/W] H,W PPG38 PPG39 PPG39 Document Number: Rev. *F Page 99 of 280

100 Address 001CF0H 001CF4H 001CF8H 001CFCH 001D00H 001D04H 001D08H 001D0CH 001D10H 001D14H 001D18H 001D1CH 001D20H 001D24H 001D28H 001D2CH 001D30H 001D34H 001D38H 001D3CH 001D40H 001D44H 001D48H 001D4CH Address offset value / Register name PCN40 [R/W] PDUT40 [W] H,W XXXXXXXX XXXXXXXX PCN240 [R/W] PTPC40 [R/W] H,W PCN41 [R/W] PDUT41 [W] H,W XXXXXXXX XXXXXXXX PCN241 [R/W] PTPC41 [R/W] H,W PCN42 [R/W] PDUT42 [W] H,W XXXXXXXX XXXXXXXX PCN242 [R/W] PTPC42 [R/W] H,W PCN43 [R/W] PDUT43 [W] H,W XXXXXXXX XXXXXXXX PCN243 [R/W] PTPC43 [R/W] H,W PCN44 [R/W] PDUT44 [W] H,W XXXXXXXX XXXXXXXX PCN244 [R/W] PTPC44 [R/W] H,W PCN45 [R/W] PDUT45 [W] H,W XXXXXXXX XXXXXXXX PCN245 [R/W] PTPC45 [R/W] H,W PCSR40 [W] H,W XXXXXXXX XXXXXXXX PTMR40 [R] H,W PSDR40 [R/W] H,W PCSR41 [W] H,W XXXXXXXX XXXXXXXX PTMR41 [R] H,W PSDR41 [R/W] H,W PCSR42 [W] H,W XXXXXXXX XXXXXXXX PTMR42 [R] H,W PSDR42 [R/W] H,W PCSR43 [W] H,W XXXXXXXX XXXXXXXX PTMR43 [R] H,W PSDR43 [R/W] H,W PCSR44 [W] H,W XXXXXXXX XXXXXXXX PTMR44 [R] H,W PSDR44 [R/W] H,W PCSR45 [W] H,W XXXXXXXX XXXXXXXX PTMR45 [R] H,W PSDR45 [R/W] H,W Block PPG40 PPG41 PPG42 PPG43 PPG44 PPG45 Document Number: Rev. *F Page 100 of 280

101 Address 001D50H 001D54H 001D58H 001D5CH 001D60H 001D64H 001D68H 001D6CH 001D70H to 001FFCH H H H 00200CH H H H 00201CH H H Address offset value / Register name PCN46 [R/W] PDUT46 [W] H,W XXXXXXXX XXXXXXXX PCN246 [R/W] PTPC46 [R/W] H,W PCN47 [R/W] PDUT47 [W] H,W XXXXXXXX XXXXXXXX PCN247 [R/W] PTPC47 [R/W] H,W PCSR46 [W] H,W XXXXXXXX XXXXXXXX PTMR46 [R] H,W PSDR46 [R/W] H,W PCSR47 [W] H,W XXXXXXXX XXXXXXXX PTMR47 [R] H,W PSDR47 [R/W] H,W Block PPG46 PPG47 Reserved CTRLR0 [R/W] ERRCNT0 [R] INTR0 [R] BRPER0 [R/W] IF1CREQ0 [R/W] IF1MSK20 [R/W] IF1ARB20 [R/W] IF1MCTR0 [R/W] IF1DTA10 [R/W] IF1DTB10 [R/W] STATR0 [R/W] BTR0 [R/W] TESTR0 [R/W] X IF1CMSK0 [R/W] IF1MSK10 [R/W] IF1ARB10 [R/W] IF1DTA20 [R/W] IF1DTB20 [R/W] H 00202CH H, H Reserved(IF1 data mirror) H 00203CH H IF2CREQ0 [R/W] IF2CMSK0 [R/W] H IF2MSK20 [R/W] IF2MSK10 [R/W] H IF2ARB20 [R/W] IF2ARB10 [R/W] CAN0 (128msb) Document Number: Rev. *F Page 101 of 280

102 Address Address offset value / Register name CH IF2MCTR0 [R/W] H IF2DTA10 [R/W] IF2DTA20 [R/W] H IF2DTB10 [R/W] IF2DTB20 [R/W] H 00205CH H, H Reserved(IF2 data mirror) H to 00207CH H H H 00208CH H H H 00209CH 0020A0H 0020A4H 0020A8H 0020ACH 0020B0H 0020B4H 0020B8H 0020BCH 0020C0H to 0020FCH TREQR20 [R] TREQR40 [R] TREQR60 [R] TREQR80 [R] NEWDT20 [R] NEWDT40 [R] NEWDT60 [R] NEWDT80 [R] INTPND20 [R] INTPND40 [R] INTPND60 [R] INTPND80 [R] MSGVAL20 [R] MSGVAL40 [R] MSGVAL60 [R] MSGVAL80 [R] TREQR10 [R] TREQR30 [R] TREQR50 [R] TREQR70 [R] NEWDT10 [R] NEWDT30 [R] NEWDT50 [R] NEWDT70 [R] INTPND10 [R] INTPND30 [R] INTPND50 [R] INTPND70 [R] MSGVAL10 [R] MSGVAL30 [R] MSGVAL50 [R] MSGVAL70 [R] Block CAN0 (128msb) CAN0 (128msb) Document Number: Rev. *F Page 102 of 280

103 Address H H H 00210CH H H H 00211CH Address offset value / Register name CTRLR1 [R/W] ERRCNT1 [R] INTR1 [R] BRPER1 [R/W] IF1CREQ1 [R/W] IF1MSK21 [R/W] IF1ARB21 [R/W] IF1MCTR1 [R/W] IF1DTA11 [R/W] IF1DTB11 [R/W] STATR1 [R/W] BTR1 [R/W] TESTR1 [R/W] X IF1CMSK1 [R/W] IF1MSK11 [R/W] IF1ARB11 [R/W] H IF1DTA21 [R/W] H IF1DTB21 [R/W] H 00212CH H, H Reserved (IF1 data mirror) H 00213CH H IF2CREQ1 [R/W] IF2CMSK1 [R/W] H IF2MSK21 [R/W] IF2MSK11 [R/W] H IF2ARB21 [R/W] IF2ARB11 [R/W] 00214CH IF2MCTR1 [R/W] H IF2DTA11 [R/W] IF2DTA21 [R/W] H IF2DTB11 [R/W] IF2DTB21 [R/W] H 00215CH H, H Reserved (IF2 data mirror) H to 00217CH H TREQR21 [R] TREQR11 [R] H TREQR41 [R] TREQR31 [R] H 00218CH Block CAN1 (64msb) CAN1 (64msb) Document Number: Rev. *F Page 103 of 280

104 Address H H Address offset value / Register name NEWDT21 [R] NEWDT41 [R] NEWDT11 [R] NEWDT31 [R] H 00219CH 0021A0H INTPND21 [R] INTPND11 [R] 0021A4H INTPND41 [R] INTPND31 [R] 0021A8H 0021ACH 0021B0H MSGVAL21 [R] MSGVAL11 [R] 0021B4H MSGVAL41 [R] MSGVAL31 [R] 0021B8H 0021BCH 0021C0H to 0021FCH H CTRLR2 [R/W] STATR2 [R/W] H ERRCNT2 [R] BTR2 [R/W] H INTR2 [R] TESTR2 [R/W] X CH BRPER2 [R/W] H IF1CREQ2 [R/W] IF1CMSK2 [R/W] H IF1MSK22 [R/W] IF1MSK12 [R/W] H IF1ARB22 [R/W] IF1ARB12 [R/W] 00221CH IF1MCTR2 [R/W] H IF1DTA12 [R/W] IF1DTA22 [R/W] H IF1DTB12 [R/W] IF1DTB22 [R/W] H 00222CH H, H Reserved (IF1 data mirror) H 00223CH H IF2CREQ2 [R/W] IF2CMSK2 [R/W] Block CAN1 (64msb) CAN2 (64msb) Document Number: Rev. *F Page 104 of 280

105 Address H H 00224CH H H Address offset value / Register name IF2MSK22 [R/W] IF2ARB22 [R/W] IF2MCTR2 [R/W] IF2DTA12 [R/W] IF2DTB12 [R/W] IF2MSK12 [R/W] IF2ARB12 [R/W] IF2DTA22 [R/W] IF2DTB22 [R/W] H 00225CH H, H Reserved (IF2 data mirror) H to 00227CH H TREQR22 [R] TREQR12 [R] H TREQR42 [R] TREQR32 [R] H 00228CH H NEWDT22 [R] NEWDT12 [R] H NEWDT42 [R] NEWDT32 [R] H 00229CH 0022A0H INTPND22 [R] INTPND12 [R] 0022A4H INTPND42 [R] INTPND32 [R] 0022A8H 0022ACH 0022B0H MSGVAL22 [R] MSGVAL12 [R] 0022B4H MSGVAL42 [R] MSGVAL32 [R] 0022B8H 0022BCH 0022C0H to 0022FCH H DFCTLR [R/W] H H FLIFCTLR [R/W] FLIFFER1 [R/W] FLIFFER2 [R/W] Block CAN2 (64msb) DFSTR [R/W] WorkFlash Flash / WorkFlash Document Number: Rev. *F Page 105 of 280

106 Address 00230CH to 0023FCH H H H 00240CH to 002FFCH H H H 00300CH H H H 00301CH H H to 00302CH H H H 00303CH H H Address offset value / Register name SEEARX [R] EECSRX [R/W] DEEARX [R] EFEARX [R/W] EFECRX [R/W] SEEARA [R] EECSRA [R/W] EFECRA [R/W] TEAR0X[R] TEAR1X[R] TEAR2X[R] TAEARX [R/W] TFECRX [R/W] TICRX [R/W] TSRCRX [W] TFECRA [R/W] TSRCRA [R/W] TAEARA[R/W] DEEARA [R] EFEARA [R/W] TASARX [R/W] TEAR0A[R] TEAR1A[R] TEAR2A[R] TICRA [R/W] TTCRX [R/W] TASARA[R/W] TTCRA [R/W] TKCCRX [R/W] TKCCRA [R/W] Block Reserved XBS RAM ECC control Reserved Backup RAM ECC control RAM/ diagnosis XBS RAM Reserved RAM/ diagnosis Backup RAM RAM/ diagnosis Backup RAM Document Number: Rev. *F Page 106 of 280

107 Address H to Address offset value / Register name FCH H BUSDIGSR0[R/W] H,W BUSDIGSR1[R/W] H,W H BUSDIGSR2[R/W] H,W BUSTSTR0[R/W] H,W H BUSADR0 [R] W 00310CH BUSADR1 [R] W H BUSADR2 [R] W H BUSDIGSR3[R/W] H,W H BUSDIGSR4[R/W] H,W BUSTSTR1[R/W] H,W CH H BUSADR3 [R] W H BUSADR4 [R] W H to 003FFCH H to 005FFCH H to 00EFFCH 00F000H to 00FEFCH 00FF00H 00FF04H to 00FF0CH 00FF10H 00FF14H 00FF18H to 00FFF4H 00FFF8H 00FFFCH Backup-RAM Block Reserved BUS diagnosis Reserved Backup RAM area Reserved Reserved [S] DSUCR [R/W] PCSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PSSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDIR1 [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDIR0 [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX OCDU [S] Reserved [S] OCDU [S] OCDU [S] Reserved [S] OCDU [S] Document Number: Rev. *F Page 107 of 280

108 [S]: It is a system register. The illegal instruction exception (data access error) is generated in these registers in the user mode when reading and writing to it. Document Number: Rev. *F Page 108 of 280

109 10. Interrupt Vector Table This list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers. Interrupt Vector 64 Pins Interrupt Factor Interrupt Number Interrupt Hexa Decimal Level Decimal Offset Default Address for TBR Reset 0 0-3FCH 000FFFFCH - System reserved 1 1-3F8H 000FFFF8H - System reserved 2 2-3F4H 000FFFF4H - System reserved 3 3-3F0H 000FFFF0H - System reserved 4 4-3ECH 000FFFECH - FPU exception 5 5-3E8H 000FFFE8H - Exception of instruction access protection violation 6 6-3E4H 000FFFE4H - Exception of data access protection violation 7 7-3E0H 000FFFE0H - Data access error interrupt 8 8-3DCH 000FFFDCH - INTE instruction 9 9-3D8H 000FFFD8H - Instruction break 10 0A - 3D4H 000FFFD4H - System reserved 11 0B - 3D0H 000FFFD0H - System reserved 12 0C - 3CCH 000FFFCCH - System reserved 13 0D - 3C8H 000FFFC8H - Exception of invalid instruction 14 0E - 3C4H 000FFFC4H - NMI request Error generation during internal bus diagnosis 15 (FH) XBS RAM double-bit error generation 15 0F Fixed Backup RAM double-bit error generation 3C0H 000FFFC0H - TPU violation External interrupt ICR00 3BCH 000FFFBCH 0 External interrupt 8-15 External low-voltage detection interrupt ICR01 3B8H 000FFFB8H 1* 7 Reload timer 0/1/4/ ICR02 3B4H 000FFFB4H 2* 2 Reload timer 3/6/ ICR03 3B0H 000FFFB0H 3* 2 ch.0 (reception completed) ICR04 3ACH 000FFFACH 4* 1 ch.0 (status) ch.0 (transmission completed) ICR05 3A8H 000FFFA8H 5* ICR06 3A4H 000FFFA4H -* ICR07 3A0H 000FFFA0H -* ICR08 39CH 000FFF9CH -* ICR09 398H 000FFF98H -* 6 ch.3 (reception completed) 26 1A ICR10 394H 000FFF94H 10* 1 ch.3 (status) ch.3 (transmission completed) 27 1B ICR11 390H 000FFF90H 11 RN Document Number: Rev. *F Page 109 of 280

110 Interrupt Factor Interrupt Number Interrupt Hexa Decimal Level Decimal Offset Default Address for TBR ch.4 (reception completed) 28 1C ICR12 38CH 000FFF8CH 12* 1 ch.4 (status) ch.4 (transmission completed) 29 1D ICR13 388H 000FFF88H 13 ch.5 (reception completed) 30 1E ICR14 384H 000FFF84H 14* 1 ch.5 (status) ch.5 (transmission completed) 31 1F ICR15 380H 000FFF80H 15 ch.6 (reception completed) ICR16 37CH 000FFF7CH 16* 1 ch.6 (status) ch.6 (transmission completed) ICR17 378H 000FFF78H 17 CAN ICR18 374H 000FFF74H - CAN1 RAM diagnosis end RAM initialization completion Error generation during RAM diagnosis Backup RAM diagnosis end Backup RAM initialization completion Error generation during Backup RAM diagnosis CAN ICR19 370H 000FFF70H - Up/down counter 0 Up/down counter 1 Real time clock ICR20 ICR21 36CH 368H 000FFF6CH 000FFF68H ICR22 364H 000FFF64H -* 6 16-bit Free-run timer 0 (0 detection) / (compare clear) ICR23 360H 000FFF60H 23 PPG 1/10/11/20/30/31 16-bit Free-run timer 1 (0 detection) / (compare clear) PPG 2/3/12/13/23/ ICR24 35CH 000FFF5CH 24* 3 16-bit Free-run timer 2 (0 detection) / (compare clear) PPG 4/24/ A ICR25 ICR26 358H 354H 000FFF58H 000FFF54H 25* 3 26* 3 PPG 7/16/17/27/ B ICR27 350H 000FFF50H 27* 3 PPG C ICR28 34CH 000FFF4CH 28* 3 16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching) 45 2D ICR29 348H 000FFF48H 29 Main timer Sub timer PLL timer 16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching) 46 2E ICR30 344H 000FFF44H 30 RN Document Number: Rev. *F Page 110 of 280

111 Interrupt Factor Interrupt Number Interrupt Hexa Decimal Level Decimal Offset Default Address for TBR Clock calibration unit (sub oscillation) ch.9 (reception completed) ch.9 (status) 47 2F ICR31 340H 000FFF40H 31* 1, * 4 A/D converter 0/1/7/10/11/14/15/16/17/22/27/28/ ICR32 33CH 000FFF3CH 32 Clock calibration unit (CR oscillation) ch.9 (transmission completed) 16-bit OCU 0 (match) / 16-bit OCU 1 (match) 32-bit Free-run timer 4 16-bit OCU 2 (match) / 16-bit OCU 3 (match) ICR33 ICR34 338H 334H 000FFF38H 000FFF34H 33 34* 5 16-bit OCU 4 (match) / 16-bit OCU 5 (match) ICR35 330H 000FFF30H bit ICU6 (fetching/measurement) ch.10 (reception completed) ch.10 (status) ch.10 (transmission completed) ICR36 ICR37 32CH 328H 000FFF2CH 000FFF28H 36* bit ICU8 (fetching/measurement) ch.11 (reception completed) ch.11 (status) 32-bit ICU9 (fetching/measurement) ICR38 324H 000FFF24H 38* 1 WG dead timer underflow 0 / 1/ 2 WG dead timer reload 0 / 1/ 2 WG DTTI 0 32-bit ICU4 (fetching/measurement) ICR39 320H 000FFF20H 39 ch.11 (transmission completed) 32-bit ICU5 (fetching/measurement) ICR40 31CH 000FFF1CH 40 A/D converter 32/34/35/37/38/40/41/42/43/44/45/46/47 32-bit OCU7/11 (match) A ICR41 ICR42 318H 314H 000FFF18H 000FFF14H bit OCU8/9 (match) 59 3B ICR43 310H 000FFF10H C ICR44 30CH 000FFF0CH - * D ICR45 308H 000FFF08H - DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/ E ICR46 304H 000FFF04H - Delay interrupt 63 3F ICR47 300H 000FFF00H - System reserved (Used for REALOS TM * 8 ) FCH 000FFEFCH - System reserved (Used for REALOS) F8H 000FFEF8H - RN Document Number: Rev. *F Page 111 of 280

112 Interrupt Factor Used with the INT instruction Interrupt Number Interrupt Hexa Decimal Level Decimal FF - Offset 2F4H 000H Default Address for TBR 000FFEF4H 000FFC00H Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no RN (Resource Number) is assigned. *1: It does not support a DMA transfer by the status of the multi-function serial interface and I 2 C reception. *2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt. *3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt. *4: The clock calibration unit does not support a DMA transfer by the interrupt. *5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt. *6: There is no resource corresponding to the interrupt level. *7: It does not support a DMA transfer by the external low-voltage detection interrupt. *8: REALOS is a trademark of Cypress. RN - Document Number: Rev. *F Page 112 of 280

113 80 Pins Interrupt Factor Interrupt Number Hexa Decimal Decimal Interrupt Level Offset Default Address for TBR Reset 0 0-3FCH 000FFFFCH - System reserved 1 1-3F8H 000FFFF8H - System reserved 2 2-3F4H 000FFFF4H - System reserved 3 3-3F0H 000FFFF0H - System reserved 4 4-3ECH 000FFFECH - FPU exception 5 5-3E8H 000FFFE8H - Exception of instruction access protection violation 6 6-3E4H 000FFFE4H - Exception of data access protection violation 7 7-3E0H 000FFFE0H - Data access error interrupt 8 8-3DCH 000FFFDCH - INTE instruction 9 9-3D8H 000FFFD8H - Instruction break 10 0A - 3D4H 000FFFD4H - System reserved 11 0B - 3D0H 000FFFD0H - System reserved 12 0C - 3CCH 000FFFCCH - System reserved 13 0D - 3C8H 000FFFC8H - Exception of invalid instruction 14 0E - 3C4H 000FFFC4H - NMI request Error generation during internal bus diagnosis 15 (FH) XBS RAM double-bit error generation 15 0F Fixed Backup RAM double-bit error generation 3C0H 000FFFC0H - TPU violation External interrupt ICR00 3BCH 000FFFBCH 0 External interrupt 8-15 External low-voltage detection interrupt ICR01 3B8H 000FFFB8H 1* 7 Reload timer 0/1/4/ ICR02 3B4H 000FFFB4H 2* 2 Reload timer 3/6/ ICR03 3B0H 000FFFB0H 3* 2 ch.0 (reception completed) ICR04 3ACH 000FFFACH 4* 1 ch.0 (status) ch.0 (transmission completed) ICR05 3A8H 000FFFA8H 5* ICR06 3A4H 000FFFA4H -* ICR07 3A0H 000FFFA0H -* 6 ch.2 (reception completed) ICR08 39CH 000FFF9CH 8* 1 ch.2 (status) ch.2 (transmission completed) ICR09 398H 000FFF98H 9* 1 ch.3 (reception completed) 26 1A ICR10 394H 000FFF94H 10* 1 ch.3 (status) ch.3 (transmission completed) 27 1B ICR11 390H 000FFF90H 11 RN Document Number: Rev. *F Page 113 of 280

114 Interrupt Factor Interrupt Number Hexa Decimal Decimal Interrupt Level Offset Default Address for TBR ch.4 (reception completed) 28 1C ICR12 38CH 000FFF8CH 12* 1 ch.4 (status) ch.4 (transmission completed) 29 1D ICR13 388H 000FFF88H 13 ch.5 (reception completed) 30 1E ICR14 384H 000FFF84H 14* 1 ch.5 (status) ch.5 (transmission completed) 31 1F ICR15 380H 000FFF80H 15 ch.6 (reception completed) ICR16 37CH 000FFF7CH 16* 1 ch.6 (status) ch.6 (transmission completed) ICR17 378H 000FFF78H 17 CAN ICR18 374H 000FFF74H - CAN1 RAM diagnosis end RAM initialization completion Error generation during RAM diagnosis Backup RAM diagnosis end Backup RAM initialization completion Error generation during Backup RAM diagnosis CAN ICR19 370H 000FFF70H - Up/down counter 0 Up/down counter 1 Real time clock ICR20 ICR21 36CH 368H 000FFF6CH 000FFF68H ICR22 364H 000FFF64H -* 6 16-bit Free-run timer 0 (0 detection) / (compare clear) ICR23 360H 000FFF60H 23 PPG 1/10/11/20/30/31 16-bit Free-run timer 1 (0 detection) / (compare clear) PPG 2/3/12/13/23/ ICR24 35CH 000FFF5CH 24* 3 16-bit Free-run timer 2 (0 detection) / (compare clear) PPG 4/5/15/24/ A ICR25 ICR26 358H 354H 000FFF58H 000FFF54H 25* 3 26* 3 PPG 7/16/17/26/27/ B ICR27 350H 000FFF50H 27* 3 PPG 8/18/19/ C ICR28 34CH 000FFF4CH 28* 3 16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching) 45 2D ICR29 348H 000FFF48H 29 Main timer Sub timer PLL timer 16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching) 46 2E ICR30 344H 000FFF44H 30 RN Document Number: Rev. *F Page 114 of 280

115 Interrupt Factor Interrupt Number Hexa Decimal Decimal Interrupt Level Offset Default Address for TBR Clock calibration unit (sub oscillation) ch.9 (reception completed) ch.9 (status) 47 2F ICR31 340H 000FFF40H 31* 1, * 4 A/D converter 0/1/7/10/11/12/14/15/16/17/19/22/26/27/28/ ICR32 33CH 000FFF3CH 32 Clock calibration unit (CR oscillation) ch.9 (transmission completed) 16-bit OCU 0 (match) / 16-bit OCU 1 (match) 32-bit Free-run timer 4 16-bit OCU 2 (match) / 16-bit OCU 3 (match) ICR33 ICR34 338H 334H 000FFF38H 000FFF34H 33 34* 5 32-bit Free-run timer 5 16-bit OCU 4 (match) / 16-bit OCU 5 (match) ICR35 330H 000FFF30H 35* 5 32-bit ICU6 (fetching/measurement) ch.10 (reception completed) ch.10 (status) ch.10 (transmission completed) ICR36 ICR37 32CH 328H 000FFF2CH 000FFF28H 36* bit ICU8 (fetching/measurement) ch.11 (reception completed) ch.11 (status) 32-bit ICU9 (fetching/measurement) ICR38 324H 000FFF24H 38* 1 WG dead timer underflow 0 / 1/ 2 WG dead timer reload 0 / 1/ 2 WG DTTI 0 32-bit ICU4 (fetching/measurement) ICR39 320H 000FFF20H 39 ch.11 (transmission completed) 32-bit ICU5 (fetching/measurement) ICR40 31CH 000FFF1CH 40 A/D converter 32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/ bit OCU7/11 (match) A ICR41 ICR42 318H 314H 000FFF18H 000FFF14H bit OCU8/9 (match) 59 3B ICR43 310H 000FFF10H C ICR44 30CH 000FFF0CH -* 6 Base timer 1 IRQ0 Base timer 1 IRQ1 - - DMAC 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/ D 3E ICR45 ICR46 308H 304H 000FFF08H 000FFF04H 45 - Delay interrupt 63 3F ICR47 300H 000FFF00H - RN Document Number: Rev. *F Page 115 of 280

116 System reserved (Used for REALOS) System reserved (Used for REALOS) Interrupt Factor Used with the INT instruction Interrupt Number Hexa Decimal Decimal Interrupt Level Offset Default Address for TBR FCH 000FFEFCH F8H 000FFEF8H FF - 2F4H 000H 000FFEF4H 000FFC00H Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no RN (Resource Number) is assigned. *1: It does not support a DMA transfer by the status of the multi-function serial interface and I 2 C reception. *2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt. *3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt. *4: The clock calibration unit does not support a DMA transfer by the interrupt. *5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt. *6: There is no resource corresponding to the interrupt level. *7: It does not support a DMA transfer by the external low-voltage detection interrupt. RN - Document Number: Rev. *F Page 116 of 280

117 100 Pins Interrupt Factor Interrupt number Decimal Hexa Decimal Interrupt Level Offset Default Address for TBR Reset 0 0-3FCH 000FFFFCH - System reserved 1 1-3F8H 000FFFF8H - System reserved 2 2-3F4H 000FFFF4H - System reserved 3 3-3F0H 000FFFF0H - System reserved 4 4-3ECH 000FFFECH - FPU exception 5 5-3E8H 000FFFE8H - Exception of instruction access protection violation 6 6-3E4H 000FFFE4H - Exception of data access protection violation 7 7-3E0H 000FFFE0H - Data access error interrupt 8 8-3DCH 000FFFDCH - INTE instruction 9 9-3D8H 000FFFD8H - Instruction break 10 0A - 3D4H 000FFFD4H - System reserved 11 0B - 3D0H 000FFFD0H - System reserved 12 0C - 3CCH 000FFFCCH - System reserved 13 0D - 3C8H 000FFFC8H - Exception of invalid instruction 14 0E - 3C4H 000FFFC4H - NMI request Error generation during internal bus diagnosis 15 (FH) XBS RAM double-bit error generation 15 0F Fixed Backup RAM double-bit error generation 3C0H 000FFFC0H - TPU violation External interrupt ICR00 3BCH 000FFFBCH 0 External interrupt 8-15 External low-voltage detection interrupt ICR01 3B8H 000FFFB8H 1* 7 Reload timer 0/1/4/ ICR02 3B4H 000FFFB4H 2* 2 Reload timer 2/3/6/ ICR03 3B0H 000FFFB0H 3* 2 ch.0 (reception completed) ICR04 3ACH 000FFFACH 4* 1 ch.0 (status) ch.0 (transmission completed) ICR05 3A8H 000FFFA8H 5* 1 ch.1 (reception completed) ICR06 3A4H 000FFFA4H 6* 1 ch.1 (status) ch.1 (transmission completed) ICR07 3A0H 000FFFA0H 7* 1 ch.2 (reception completed) ICR08 39CH 000FFF9CH 8* 1 ch.2 (status) ch.2 (transmission completed) ICR09 398H 000FFF98H 9* 1 ch.3 (reception completed) ch.3 (status) 26 1A ICR10 394H 000FFF94H 10* 1 RN Document Number: Rev. *F Page 117 of 280

118 Interrupt Factor Interrupt number Decimal Hexa Decimal Interrupt Level Offset Default Address for TBR ch.3 (transmission completed) 27 1B ICR11 390H 000FFF90H 11 ch.4 (reception completed) 28 1C ICR12 38CH 000FFF8CH 12* 1 ch.4 (status) ch.4 (transmission completed) 29 1D ICR13 388H 000FFF88H 13 ch.5 (reception completed) 30 1E ICR14 384H 000FFF84H 14* 1 ch.5 (status) ch.5 (transmission completed) 31 1F ICR15 380H 000FFF80H 15 ch.6 (reception completed) ICR16 37CH 000FFF7CH 16* 1 ch.6 (status) ch.6 (transmission completed) ICR17 378H 000FFF78H 17 CAN ICR18 374H 000FFF74H - CAN1 RAM diagnosis end RAM initialization completion Error generation during RAM diagnosis Backup RAM diagnosis end Backup RAM initialization completion Error generation during Backup RAM diagnosis CAN ICR19 370H 000FFF70H - Up/down counter 0 Up/down counter 1 Real time clock ICR20 ICR21 36CH 000FFF6CH 368H 000FFF68H - - ch.7 (reception completed) ICR22 364H 000FFF64H 22* 1 ch.7 (status) 16-bit Free-running timer 0 (0 detection) / (compare clear) ICR23 360H 000FFF60H 23 ch.7 (transmission completed) PPG 1/10/11/20/21/30/31 16-bit Free-run timer 1 (0 detection) / (compare clear) PPG 2/3/12/13/23/32/ ICR24 35CH 000FFF5CH 24* 3 16-bit Free-run timer 2 (0 detection) / (compare clear) PPG 4/5/14/15/24/25/35/ A ICR25 ICR26 358H 000FFF58H 25* 3 354H 000FFF54H 26* 3 PPG 6/7/16/17/26/27/ B ICR27 350H 000FFF50H 27* 3 PPG 8/9/18/19/28/ C ICR28 34CH 000FFF4CH 28* 3 RN Document Number: Rev. *F Page 118 of 280

119 Interrupt Factor ch.8 (reception completed) ch.8 (status) 16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching) Main timer Sub timer PLL timer ch.8 (transmission completed) 16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching) Clock calibration unit (sub oscillation) ch.9 (reception completed) ch.9 (status) A/D converter 0/1/7/9/10/11/12/13/14/15/16 17/18/19/22/23/26/27/28/29/31 Clock calibration unit (CR oscillation) ch.9 (transmission completed) 16-bit OCU 0 (match) / 16-bit OCU 1 (match) 32-bit Free-run timer 4 16-bit OCU 2 (match) / 16-bit OCU 3 (match) 32-bit Free-run timer 3/5 16-bit OCU 4 (match) / 16-bit OCU 5 (match) 32-bit ICU6 (fetching/measurement) ch.10 (reception completed) ch.10 (status) 32-bit ICU7 (fetching/measurement) ch.10 (transmission completed) 32-bit ICU8 (fetching/measurement) ch.11 (reception completed) ch.11 (status) 32-bit ICU9 (fetching/measurement) WG dead timer underflow 0/1/2 WG dead timer reload 0/1/2 WG DTTI 0 32-bit ICU4 (fetching/measurement) ch.11 (transmission completed) Interrupt number Decimal Hexa Decimal Interrupt Level Offset Default Address for TBR RN 45 2D ICR29 348H 000FFF48H 29* E ICR30 344H 000FFF44H F ICR31 340H 000FFF40H 31*1, * ICR32 33CH 000FFF3CH ICR33 338H 000FFF38H ICR34 334H 000FFF34H 34* ICR35 330H 000FFF30H 35* ICR36 32CH 000FFF2CH 36* ICR37 328H 000FFF28H ICR38 324H 000FFF24H 38* ICR39 320H 000FFF20H ICR40 31CH 000FFF1CH 40 Document Number: Rev. *F Page 119 of 280

120 Interrupt Factor Interrupt number Decimal Hexa Decimal Interrupt Level Offset Default Address for TBR 32-bit ICU5 (fetching/measurement) A/D converter 32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/ bit OCU 6/7/10/11 (match) A ICR41 ICR42 318H 000FFF18H 314H 000FFF14H bit OCU 8/9 (match) 59 3B ICR43 310H 000FFF10H C ICR44 30CH 000FFF0CH 44 Base timer 1 IRQ0 Base timer 1 IRQ1 - - DMAC 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/ D 3E ICR45 ICR46 308H 000FFF08H 304H 000FFF04H 45 - Delay interrupt 63 3F ICR47 300H 000FFF00H - System reserved (Used for REALOS) FCH 000FFEFCH - System reserved (Used for REALOS) F8H 000FFEF8H - Used with the INT instruction FF - 2F4H 000H 000FFEF4H 000FFC00H - Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no RN (Resource Number) is assigned. *1: It does not support a DMA transfer by the status of the multi-function serial interface and I 2 C reception. *2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt. *3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt. *4: The clock calibration unit does not support a DMA transfer by the interrupt. *5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt. *6: There is no resource corresponding to the interrupt level. *7: It does not support a DMA transfer by the external low-voltage detection interrupt. RN Document Number: Rev. *F Page 120 of 280

121 120 Pins Interrupt Factor Interrupt Number Decimal Hexa Decimal Interrupt Level Default Offset Address for TBR Reset 0 0-3FCH 000FFFFCH - System reserved 1 1-3F8H 000FFFF8H - System reserved 2 2-3F4H 000FFFF4H - System reserved 3 3-3F0H 000FFFF0H - System reserved 4 4-3ECH 000FFFECH - FPU exception 5 5-3E8H 000FFFE8H - Exception of instruction access protection violation 6 6-3E4H 000FFFE4H - Exception of data access protection violation 7 7-3E0H 000FFFE0H - Data access error interrupt 8 8-3DCH 000FFFDCH - INTE instruction 9 9-3D8H 000FFFD8H - Instruction break 10 0A - 3D4H 000FFFD4H - System reserved 11 0B - 3D0H 000FFFD0H - System reserved 12 0C - 3CCH 000FFFCCH - System reserved 13 0D - 3C8H 000FFFC8H - Exception of invalid instruction 14 0E - 3C4H 000FFFC4H - NMI request Error generation during internal bus diagnosis 15 (FH) XBS RAM double-bit error generation 15 0F Fixed Backup RAM double-bit error generation 3C0H 000FFFC0H - TPU violation External interrupt ICR00 3BCH 000FFFBCH 0 External interrupt 8-15 External low-voltage detection interrupt ICR01 3B8H 000FFFB8H 1* 7 Reload timer 0/1/4/ ICR02 3B4H 000FFFB4H 2* 2 Reload timer 2/3/6/ ICR03 3B0H 000FFFB0H 3* 2 ch.0 (reception completed) ICR04 3ACH 000FFFACH 4* 1 ch.0 (status) ch.0 (transmission completed) ICR05 3A8H 000FFFA8H 5* 1 ch.1 (reception completed) ICR06 3A4H 000FFFA4H 6* 1 ch.1 (status) ch.1 (transmission completed) ICR07 3A0H 000FFFA0H 7* 1 ch.2 (reception completed) ICR08 39CH 000FFF9CH 8* 1 ch.2 (status) ch.2 (transmission completed) ICR09 398H 000FFF98H 9* 1 ch.3 (reception completed) ch.3 (status) 26 1A ICR10 394H 000FFF94H 10* 1 RN Document Number: Rev. *F Page 121 of 280

122 Interrupt Factor Interrupt Number Decimal Hexa Decimal Interrupt Level Default Offset Address for TBR ch.3 (transmission completed) 27 1B ICR11 390H 000FFF90H 11 ch.4 (reception completed) 28 1C ICR12 38CH 000FFF8CH 12* 1 ch.4 (status) ch.4 (transmission completed) 29 1D ICR13 388H 000FFF88H 13 ch.5 (reception completed) 30 1E ICR14 384H 000FFF84H 14* 1 ch.5 (status) ch.5 (transmission completed) 31 1F ICR15 380H 000FFF80H 15 ch.6 (reception completed) ICR16 37CH 000FFF7CH 16* 1 ch.6 (status) ch.6 (transmission completed) ICR17 378H 000FFF78H 17 CAN ICR18 374H 000FFF74H - CAN1 RAM diagnosis end RAM initialization completion Error generation during RAM diagnosis Backup RAM diagnosis end Backup RAM initialization completion Error generation during Backup RAM diagnosis CAN ICR19 370H 000FFF70H - Up/down counter 0 Up/down counter 1 Real time clock ICR20 ICR21 36CH 000FFF6CH 368H 000FFF68H - - ch.7 (reception completed) ICR22 364H 000FFF64H 22* 1 ch.7 (status) 16-bit Free-run timer 0 (0 detection) / (compare clear) ICR23 360H 000FFF60H 23 ch.7 (transmission completed) PPG 0/1/10/11/20/21/30/31 16-bit Free-run timer 1 (0 detection) / (compare clear) PPG 2/3/12/13/22/23/32/33/ ICR24 35CH 000FFF5CH 24* 3 16-bit Free-run timer 2 (0 detection) / (compare clear) PPG 4/5/14/15/24/25/35/ A ICR25 ICR26 358H 000FFF58H 25* 3 354H 000FFF54H 26* 3 PPG 6/7/16/17/26/27/ B ICR27 350H 000FFF50H 27* 3 PPG 8/9/18/19/28/ C ICR28 34CH 000FFF4CH 28* 3 RN Document Number: Rev. *F Page 122 of 280

123 Interrupt Factor ch.8 (reception completed) ch.8 (status) 16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching) Main timer Sub timer PLL timer ch.8 (transmission completed) 16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching) Clock calibration unit (sub oscillation) ch.9 (reception completed) ch.9 (status) A/D converter 0/1/7/9/10/11/12/13/14/15/16/ 17/18/19/20/21/22/23/24/25/26/27/28/29/30/31 Clock calibration unit ( CR oscillation) ch.9 (transmission completed) 16-bit OCU 0 (match) / 16-bit OCU 1 (match) 32-bit Free-run timer 4 16-bit OCU 2 (match) / 16-bit OCU 3 (match) 32-bit Free-run timer 3/5 16-bit OCU 4 (match) / 16-bit OCU 5 (match) 32-bit ICU6 (fetching/measurement) ch.10 (reception completed) ch.10 (status) 32-bit ICU7 (fetching/measurement) ch.10 (transmission completed) 32-bit ICU8 (fetching/measurement) ch.11 (reception completed) ch.11 (status) 32-bit ICU9 (fetching/measurement) WG dead timer underflow 0/1/2 WG dead timer reload 0/1/2 WG DTTI 0 32-bit ICU4 (fetching/measurement) ch.11 (transmission completed) Interrupt Number Decimal Hexa Decimal Interrupt Level Default Offset Address for TBR RN 45 2D ICR29 348H 000FFF48H 29* E ICR30 344H 000FFF44H F ICR31 340H 000FFF40H 31* 1, * ICR32 33CH 000FFF3CH ICR33 338H 000FFF38H ICR34 334H 000FFF34H 34* ICR35 330H 000FFF30H 35* ICR36 32CH 000FFF2CH 36* ICR37 328H 000FFF28H ICR38 324H 000FFF24H 38* ICR39 320H 000FFF20H ICR40 31CH 000FFF1CH 40 Document Number: Rev. *F Page 123 of 280

124 Interrupt Factor Interrupt Number Decimal Hexa Decimal Interrupt Level Default Offset Address for TBR 32-bit ICU5 (fetching/measurement) A/D converter 32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47 32-bit OCU 6/7/10/11 (match) A ICR41 ICR42 318H 000FFF18H 314H 000FFF14H bit OCU 8/9 (match) 59 3B ICR43 310H 000FFF10H C ICR44 30CH 000FFF0CH 44 Base timer 1 IRQ0 Base timer 1 IRQ1 - - DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/ D 3E ICR45 ICR46 308H 000FFF08H 304H 000FFF04H 45 - Delay interrupt 63 3F ICR47 300H 000FFF00H - System reserved (Used for REALOS) FCH 000FFEFCH - System reserved (Used for REALOS) F8H 000FFEF8H - Used with the INT instruction FF - 2F4H 000FFEF4H 000H 000FFC00H Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no RN (Resource Number) is assigned. *1: It does not support a DMA transfer by the status of the multi-function serial interface and I 2 C reception. *2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt. *3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt. *4: The clock calibration unit does not support a DMA transfer by the interrupt. *5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt. *6: There is no resource corresponding to the interrupt level. *7: It does not support a DMA transfer by the external low-voltage detection interrupt. RN - Document Number: Rev. *F Page 124 of 280

125 144 Pins Interrupt Factor Interrupt Number Hexa Decimal Decimal Interrupt Level Offset Default Address for TBR Reset 0 0-3FCH 000FFFFCH - System reserved 1 1-3F8H 000FFFF8H - System reserved 2 2-3F4H 000FFFF4H - System reserved 3 3-3F0H 000FFFF0H - System reserved 4 4-3ECH 000FFFECH - FPU exception 5 5-3E8H 000FFFE8H - Exception of instruction access protection violation 6 6-3E4H 000FFFE4H - Exception of data access protection violation 7 7-3E0H 000FFFE0H - Data access error interrupt 8 8-3DCH 000FFFDCH - INTE instruction 9 9-3D8H 000FFFD8H - Instruction break 10 0A - 3D4H 000FFFD4H - System reserved 11 0B - 3D0H 000FFFD0H - System reserved 12 0C - 3CCH 000FFFCCH - System reserved 13 0D - 3C8H 000FFFC8H - Exception of invalid instruction 14 0E - 3C4H 000FFFC4H - NMI request Error generation during internal bus diagnosis 15 (FH) XBS RAM double-bit error generation 15 0F Fixed Backup RAM double-bit error generation 3C0H 000FFFC0H - TPU violation External interrupt ICR00 3BCH 000FFFBCH 0 External interrupt 8-15 External low-voltage detection interrupt ICR01 3B8H 000FFFB8H 1* 7 Reload timer 0/1/4/ ICR02 3B4H 000FFFB4H 2* 2 Reload timer 2/3/6/ ICR03 3B0H 000FFFB0H 3* 2 ch.0 (reception completed) ICR04 3ACH 000FFFACH 4* 1 ch.0 (status) ch.0 (transmission completed) ICR05 3A8H 000FFFA8H 5* 1 ch.1 (reception completed) ICR06 3A4H 000FFFA4H 6* 1 ch.1 (status) ch.1 (transmission completed) ICR07 3A0H 000FFFA0H 7* 1 ch.2 (reception completed) ICR08 39CH 000FFF9CH 8* 1 ch.2 (status) ch.2 (transmission completed) ICR09 398H 000FFF98H 9* 1 ch.3 (reception completed) ch.3 (status) 26 1A ICR10 394H 000FFF94H 10* 1 RN Document Number: Rev. *F Page 125 of 280

126 Interrupt Factor Interrupt Number Hexa Decimal Decimal Interrupt Level Offset Default Address for TBR ch.3 (transmission completed) 27 1B ICR11 390H 000FFF90H 11 ch.4 (reception completed) 28 1C ICR12 38CH 000FFF8CH 12* 1 ch.4 (status) ch.4 (transmission completed) 29 1D ICR13 388H 000FFF88H 13 ch.5 (reception completed) 30 1E ICR14 384H 000FFF84H 14* 1 ch.5 (status) ch.5 (transmission completed) 31 1F ICR15 380H 000FFF80H 15 ch.6 (reception completed) ICR16 37CH 000FFF7CH 16* 1 ch.6 (status) ch.6 (transmission completed) ICR17 378H 000FFF78H 17 CAN ICR18 374H 000FFF74H - CAN1 RAM diagnosis end RAM initialization completion Error generation during RAM diagnosis Backup RAM diagnosis end Backup RAM initialization completion Error generation during Backup RAM diagnosis CAN ICR19 370H 000FFF70H - Up/down counter 0 Up/down counter 1 Real time clock ICR20 ICR21 36CH 368H 000FFF6CH 000FFF68H - - ch.7 (reception completed) ICR22 364H 000FFF64H 22* 1 ch.7 (status) 16-bit Free-run timer 0 (0 detection) / (compare clear) ICR23 360H 000FFF60H 23 ch.7 (transmission completed) PPG 0/1/10/11/20/21/30/31/40/41 16-bit Free-run timer 1 (0 detection) / (compare clear) PPG 2/3/12/13/22/23/32/33/ ICR24 35CH 000FFF5CH 24* 3 16-bit Free-run timer 2 (0 detection) / (compare clear) PPG 4/5/14/15/24/25/34/35/ A ICR25 ICR26 358H 354H 000FFF58H 000FFF54H 25* 3 26* 3 PPG 6/7/16/17/26/27/36/ B ICR27 350H 000FFF50H 27* 3 PPG 8/9/18/19/28/29/38/ C ICR28 34CH 000FFF4CH 28* 3 RN Document Number: Rev. *F Page 126 of 280

127 Interrupt Factor ch.8 (reception completed) ch.8 (status) 16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching) Main timer Sub timer PLL timer ch.8 (transmission completed) 16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching) Clock calibration unit (sub oscillation) ch.9 (reception completed) ch.9 (status) A/D converter 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16 17/18/19/20/21/22/23/24/25/26/27/28/29/30/31 Clock calibration unit ( CR oscillation) ch.9 (transmission completed) 16-bit OCU 0 (match) / 16-bit OCU 1 (match) 32-bit Free-run timer 4 16-bit OCU 2 (match) / 16-bit OCU 3 (match) 32-bit Free-run timer 3/5 16-bit OCU 4 (match) / 16-bit OCU 5 (match) 32-bit ICU 6 (fetching/measurement) ch.10 (reception completed) ch.10 (status) 32-bit ICU7 (fetching/measurement) ch.10 (transmission completed) 32-bit ICU8 (fetching/measurement) ch.11 (reception completed) ch.11 (status) 32-bit ICU9 (fetching/measurement) WG dead timer underflow 0 / 1/ 2 WG dead timer reload 0 / 1/ 2 WG DTTI 0 32-bit ICU4 (fetching/measurement) ch.11 (transmission completed) Interrupt Number Hexa Decimal Decimal Interrupt Level Offset Default Address for TBR RN 45 2D ICR29 348H 000FFF48H 29* E ICR30 344H 000FFF44H F ICR31 340H 000FFF40H 31* 1, * ICR32 33CH 000FFF3CH ICR33 338H 000FFF38H ICR34 334H 000FFF34H 34* ICR35 330H 000FFF30H 35* ICR36 32CH 000FFF2CH 36* ICR37 328H 000FFF28H ICR38 324H 000FFF24H 38* ICR39 320H 000FFF20H ICR40 31CH 000FFF1CH 40 Document Number: Rev. *F Page 127 of 280

128 Interrupt Factor Interrupt Number Hexa Decimal Decimal Interrupt Level Offset Default Address for TBR 32-bit ICU5 (fetching/measurement) A/D converter 32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47 32-bit OCU 6/7/10/11 (match) A ICR41 ICR42 318H 314H 000FFF18H 000FFF14H bit OCU8/9 (match) 59 3B ICR43 310H 000FFF10H 43 Base timer 0 IRQ0 Base timer 0 IRQ1 60 3C ICR44 30CH 000FFF0CH 44 Base timer 1 IRQ0 Base timer 1 IRQ1 - - DMAC 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/ D 3E ICR45 ICR46 308H 304H 000FFF08H 000FFF04H 45 - Delay interrupt 63 3F ICR47 300H 000FFF00H - System reserved (Used for REALOS) FCH 000FFEFCH - System reserved (Used for REALOS) F8H 000FFEF8H - Used with the INT instruction FF - 2F4H 000H 000FFEF4H 000FFC00H - Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no RN (Resource Number) is assigned. *1: It does not support a DMA transfer by the status of the multi-function serial interface and I 2 C reception. *2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt. *3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt. *4: The clock calibration unit does not support a DMA transfer by the interrupt. *5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt. *6: There is no resource corresponding to the interrupt level. *7: It does not support a DMA transfer by the external low-voltage detection interrupt. RN Document Number: Rev. *F Page 128 of 280

129 176 Pins Interrupt Factor Interrupt Number Decimal Hexa Decimal Interrupt Level Offset Default Address for TBR Reset 0 0-3FCH 000FFFFCH - System reserved 1 1-3F8H 000FFFF8H - System reserved 2 2-3F4H 000FFFF4H - System reserved 3 3-3F0H 000FFFF0H - System reserved 4 4-3ECH 000FFFECH - FPU exception 5 5-3E8H 000FFFE8H - Exception of instruction access protection violation 6 6-3E4H 000FFFE4H - Exception of data access protection violation 7 7-3E0H 000FFFE0H - Data access error interrupt 8 8-3DCH 000FFFDCH - INTE instruction 9 9-3D8H 000FFFD8H - Instruction break 10 0A - 3D4H 000FFFD4H - System reserved 11 0B - 3D0H 000FFFD0H - System reserved 12 0C - 3CCH 000FFFCCH - System reserved 13 0D - 3C8H 000FFFC8H - Exception of invalid instruction 14 0E - 3C4H 000FFFC4H - NMI request Error generation during internal bus diagnosis 15 (FH) XBS RAM double-bit error generation 15 0F Fixed Backup RAM double-bit error generation 3C0H 000FFFC0H - TPU violation External interrupt ICR00 3BCH 000FFFBCH 0 External interrupt 8-15 External low-voltage detection interrupt ICR01 3B8H 000FFFB8H 1* 7 Reload timer 0/1/4/ ICR02 3B4H 000FFFB4H 2* 2 Reload timer 2/3/6/ ICR03 3B0H 000FFFB0H 3* 2 ch.0 (reception completed) ICR04 3ACH 000FFFACH 4* 1 ch.0 (status) ch.0 (transmission completed) ICR05 3A8H 000FFFA8H 5* 1 ch.1 (reception completed) ICR06 3A4H 000FFFA4H 6* 1 ch.1 (status) ch.1 (transmission completed) ICR07 3A0H 000FFFA0H 7* 1 ch.2 (reception completed) ICR08 39CH 000FFF9CH 8* 1 ch.2 (status) ch.2 (transmission completed) ICR09 398H 000FFF98H 9* 1 ch.3 (reception completed) ch.3 (status) 26 1A ICR10 394H 000FFF94H 10* 1 RN Document Number: Rev. *F Page 129 of 280

130 Interrupt Factor Interrupt Number Decimal Hexa Decimal Interrupt Level Offset Default Address for TBR ch.3 (transmission completed) 27 1B ICR11 390H 000FFF90H 11 ch.4 (reception completed) 28 1C ICR12 38CH 000FFF8CH 12* 1 ch.4 (status) ch.4 (transmission completed) 29 1D ICR13 388H 000FFF88H 13 ch.5 (reception completed) 30 1E ICR14 384H 000FFF84H 14* 1 ch.5 (status) ch.5 (transmission completed) 31 1F ICR15 380H 000FFF80H 15 ch.6 (reception completed) ICR16 37CH 000FFF7CH 16* 1 ch.6 (status) ch.6 (transmission completed) ICR17 378H 000FFF78H 17 CAN ICR18 374H 000FFF74H - CAN1 RAM diagnosis end RAM initialization completion Error generation during RAM diagnosis Backup RAM diagnosis end Backup RAM initialization completion Error generation during Backup RAM diagnosis CAN ICR19 370H 000FFF70H - Up/down counter 0 Up/down counter ICR20 36CH 000FFF6CH - Real time clock ICR21 368H 000FFF68H - ch.7 (reception completed) ICR22 364H 000FFF64H 22* 1 ch.7 (status) 16-bit Free-run timer 0 (0 detection) / (compare clear) ICR23 360H 000FFF60H 23 ch.7 (transmission completed) PPG 0/1/10/11/20/21/30/31/40/41 16-bit Free-run timer 1 (0 detection) / (compare clear) PPG 2/3/12/13/22/23/32/33/ ICR24 35CH 000FFF5CH 24* 3 16-bit Free-run timer 2 (0 detection) / (compare clear) PPG 4/5/14/15/24/25/34/35/44/ A ICR25 ICR26 358H 354H 000FFF58H 25* 3 000FFF54H 26* 3 PPG 6/7/16/17/26/27/36/37/46/ B ICR27 350H 000FFF50H 27* 3 PPG 8/9/18/19/28/29/38/ C ICR28 34CH 000FFF4CH 28* 3 RN Document Number: Rev. *F Page 130 of 280

131 Interrupt Factor ch.8 (reception completed) ch.8 (status) 16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching) Main timer Sub timer PLL timer ch.8 (transmission completed) 16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching) Clock calibration unit (sub oscillation) ch.9 (reception completed) ch.9 (status) A/D converter 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16 17/18/19/20/21/22/23/24/25/26/27/28/29/30/31 Clock calibration unit (CR oscillation) ch.9 (transmission completed) 16-bit OCU 0 (match) / 16-bit OCU 1 (match) 32-bit Free-run timer 4 16-bit OCU 2 (match) / 16-bit OCU 3 (match) 32-bit Free-run timer 3/5 16-bit OCU 4 (match) / 16-bit OCU 5 (match) 32-bit ICU6 (fetching/measurement) ch.10 (reception completed) ch.10 (status) 32-bit ICU7 (fetching/measurement) ch.10 (transmission completed) 32-bit ICU8 (fetching/measurement) ch.11 (reception completed) ch.11 (status) 32-bit ICU9 (fetching/measurement) WG dead timer underflow 0/1/2 WG dead timer reload 0/1/2 WG DTTI 0 32-bit ICU4 (fetching/measurement) ch.11 (transmission completed) Interrupt Number Decimal Hexa Decimal Interrupt Level Offset Default Address for TBR RN 45 2D ICR29 348H 000FFF48H 29* E ICR30 344H 000FFF44H F ICR31 340H 000FFF40H 31*1, * ICR32 33CH 000FFF3CH ICR33 338H 000FFF38H ICR34 334H 000FFF34H 34* ICR35 330H 000FFF30H 35* ICR36 32CH 000FFF2CH 36* ICR37 328H 000FFF28H ICR38 324H 000FFF24H 38* ICR39 320H 000FFF20H ICR40 31CH 000FFF1CH 40 Document Number: Rev. *F Page 131 of 280

132 Interrupt Factor Interrupt Number Decimal Hexa Decimal Interrupt Level Offset Default Address for TBR 32-bit ICU5 (fetching/measurement) A/D converter 32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/ bit OCU 6/7/10/11 (match) A ICR41 ICR42 318H 314H 000FFF18H 000FFF14H bit OCU 8/9 (match) 59 3B ICR43 310H 000FFF10H 43 Base timer 0 IRQ0 Base timer 0 IRQ1 60 3C ICR44 30CH 000FFF0CH 44 Base timer 1 IRQ0 Base timer 1 IRQ1 - - DMAC 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/ D 3E ICR45 ICR46 308H 304H 000FFF08H 000FFF04H 45 - Delay interrupt 63 3F ICR47 300H 000FFF00H - System reserved (Used for REALOS) FCH 000FFEFCH - System reserved (Used for REALOS) F8H 000FFEF8H - Used with the INT instruction FF - 2F4H 000H 000FFEF4H 000FFC00H - Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no RN (Resource Number) is assigned. *1: It does not support a DMA transfer by the status of the multi-function serial interface and I 2 C reception. *2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt. *3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt. *4: The clock calibration unit does not support a DMA transfer by the interrupt. *5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt. *6: There is no resource corresponding to the interrupt level. *7: It does not support a DMA transfer by the external low-voltage detection interrupt. RN Document Number: Rev. *F Page 132 of 280

133 11. Electrical Characteristics Absolute Maximum Ratings Rating Parameter Symbol Unit Min Max Power supply voltage * 1, * 2 VCC VSS-0.3 VSS+6.0 V Analog power supply voltage * 1, * 2 AVCC VSS-0.3 VSS+6.0 V Remarks AVRH AVCC VCC Analog reference voltage * 1 AVRH VSS-0.3 VSS+6.0 V AVRH AVCC Input voltage * 1 VI VSS-0.3 VCC+0.3 V Analog pin input voltage * 1 VIA5 VSS-0.3 VCC+0.3 V Output voltage * 1 Vo VSS-0.3 VCC+0.3 V Maximum clamp current ICLAMP ma *6 Total maximum clamp current Σ ICLAMP - 20 ma *6 "L" level maximum output current * 3 IOL1-15 ma IOL2-30 ma "L" level average output current * 4 IOLAV1-4 ma *9 IOLAV2-12 ma *10 "L" level total output current * 5 ΣIOL1-100 ma ΣIOL2-120 ma "H" level maximum output current* 3 IOH ma IOH ma "H" level average output current* 4 IOHAV ma *9 IOHAV ma *10 "H" level total output current * 5 ΣIOH ma ΣIOH ma Power TA: -40 C to +105 C mw *8 PD consumption TA: -40 C to +125 C mw *8 Operating temperature TA C C *7 Storage temperature Tstg C *1: These parameters are based on the condition that VSS = AVSS = 0.0 V *2: Caution must be taken that AVCC, AVRH do not exceed VCC upon power-on and under other circumstances. *3: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *4: The average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 10 ms period. The average value is the operation current the operation ratio. *5: The total output current is defined as the maximum current value flowing through all of corresponding pins. *6: Corresponding pins: all general-purpose ports except P035, 041, 093, 122. Use within recommended operating conditions. Use at DC voltage (current). The + B signal should always be applied by connecting a limiting resistor between the + B signal and the microcontroller. The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the + B signal is input. Note that when the microcontroller drive current is low, such as in the low power consumption modes, the + B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices. Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied through the pin, the microcontroller may operate incompletely. Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply voltage. Do not leave + B input pins open. *7: When it is used under this condition, contact your sales representative. Document Number: Rev. *F Page 133 of 280

134 *8: It is a standard when four-layer substrate is used. *9: Corresponding pins: General-purpose ports other than those of P103, P104, P105 and P106. *10: Corresponding pins: General-purpose ports of P103, P104, P105 and P106. Sample Recommended Circuit MB91520 series Protective diode Limiting resistor current +B input (12 to 16V) <WARNING> Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Power supply voltage Smoothing capacitor *2 Symbol VCC, AVCC CS Min Value Max Unit Remarks V Recommended operation guarantee range (When 5.0 V is used) V Recommended operation guarantee range (When 3.3 V is used) V Operation guarantee range *1 4.7 (tolerance within ±50 %) µf Use a ceramic capacitor or a capacitor that has the similar frequency characteristics. Use a capacitor with a capacitance greater than CS as the smoothing capacitor on the VCC pin C Operating temperature TA C *3 *1: When it is used outside recommended operation guarantee range (range of the operation guarantee),contact your sales representative. The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to V). This LVD setting and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the Document Number: Rev. *F Page 134 of 280

135 minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD. *2: See the following diagram for details on the connection of smoothing capacitor CS. *3: When it is used under this condition, contact your sales representative. C Pin Connection Diagram C C S V SS V SS AV SS <WARNING> The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: Rev. *F Page 135 of 280

136 DC Characteristics (TA: -40 C to +105 C, VCC = AVcc = 5.0 V ± 10 %/3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Value Conditions Name Min Typ Max Unit Operating frequency FCP = 80 MHz, Fcpp = 40 MHz, at normal operation ma Operating frequency FCP = 80 MHz, Fcpp = 40 MHz, at Flash write ma Operating frequency FCP = 80 MHz, Fcpp = 40 MHz, at Flash erase ma Operating frequency FCP = 64 MHz, Fcpp = 32 MHz, at normal operation ma ICC5 Operating frequency FCP = 64 MHz, Fcpp = 32 MHz, at Flash write ma Operating frequency FCP = 64 MHz, Fcpp = 32 MHz, at Flash erase ma Operating frequency FCP = 48 MHz, Fcpp = 24 MHz, at normal operation ma Operating frequency FCP = 48 MHz, Fcpp = 24 MHz, at Flash write ma Operating frequency FCP = 48 MHz, Fcpp = 24 MHz, at Flash erase ma Operating frequency FCP = 80 MHz, ICCS ma Fcpp = 40 MHz, at CPU sleep mode Power Operating frequency FCP = 80 MHz, supply ICCBS5 VCC ma Fcpp = 40 MHz, at bus sleep mode current When using crystal 4 MHz TA = +25 C * ICCT5 Watch mode When using built-in CR clock 50 khz TA = +25 C * When using sub clock 32 khz TA = +25 C * ICCH5 Stop mode TA = +25 C * µa When using crystal 4 MHz TA = +25 C * ICCT52 ICCH52 Watch mode (power off) Stop mode (power off) When using built-in CR clock 50 khz, TA = +25 C * When using sub clock 32 khz TA = +25 C * µa µa TA = +25 C * µa Remarks LVD/ RTC operation, Backup RAM 8 KB retention Backup RAM 8 KB retention Document Number: Rev. *F Page 136 of 280

137 (TA: -40 C to +125 C, VCC = AVcc = 5.0 V ± 10 %/3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Value Conditions Name Min Typ Max Unit Operating frequency FCP = 80 MHz, Fcpp = 40 MHz, at normal operation ma Operating frequency FCP = 80 MHz, Fcpp = 40 MHz, at Flash write ma Operating frequency FCP = 80 MHz, Fcpp = 40 MHz, at Flash erase ma Operating frequency FCP = 64 MHz, Fcpp = 32 MHz, at normal operation ma ICC5 Operating frequency FCP = 64 MHz, Fcpp = 32 MHz, at Flash write ma Operating frequency FCP = 64 MHz, Fcpp = 32 MHz, at Flash erase ma Operating frequency FCP = 48 MHz, Fcpp = 24 MHz, at normal operation ma Operating frequency FCP = 48 MHz, Fcpp = 24 MHz, at Flash write ma Operating frequency FCP = 48 MHz, Fcpp = 24 MHz, at Flash erase ma Operating frequency FCP = 80 MHz, ICCS ma Fcpp = 40 MHz, at CPU sleep mode Power Operating frequency FCP = 80 MHz, supply ICCBS5 VCC ma Fcpp = 40 MHz, at bus sleep mode current When using crystal 4 MHz TA = +25 C * ICCT5 Watch mode When using built-in CR clock 50 khz TA = +25 C * When using sub clock 32 khz TA = +25 C * ICCH5 Stop mode TA = +25 C * µa When using crystal 4 MHz TA = +25 C * ICCT52 ICCH52 Watch mode (power off) Stop mode (power off) When using built-in CR clock 50 khz, TA = +25 C * When using sub clock 32 khz TA = +25 C * µa µa TA = +25 C * µa Remarks LVD/ RTC operation, Backup RAM 8 KB retention Backup RAM 8 KB retention Document Number: Rev. *F Page 137 of 280

138 (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/Vcc = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions Input leak current Input capacitance 1 Pull-up resistance H level output voltage L level output voltage IIL CIN1 RUP1 RUP2 RUP3 VOH1 VOH2 All input pins Other than VCC,VSS, AVCC, AVSS, C RSTX, NMIX P073, ,077 Port pin other than P035, 041,073,074, 076,077,093, 122 Normal output pin P073,074,076, 077 VOH3 P103 to 106 VOL1 VOL2 Normal output pin P073,074,076, 077 VOL3 P103 to 106 VCC = AVCC = 5.5 V VSS<VI<VCC Value Min Typ Max Unit -5-5 µa pf VCC = 5.0 V ± 10 % Vcc = 3.3 V ± 0.3 V VCC = 5.0 V ± 10 % Vcc = 3.3 V ± 0.3 V VCC = 5.0 V ± 10 % Vcc = 3.3 V ± 0.3 V Vcc = 4.5 V IOH = -4.0 ma Vcc = 3.0 V IOH = -2.0 ma Vcc = 4.5 V IOH = -3.0 ma Vcc = 4.5 V IOH = ma Vcc = 3.0 V IOH = -8.0 ma Vcc = 4.5 V IOL = 4.0 ma Vcc = 3.0 V IOL = 2.0 ma Vcc = 4.5 V IOL = 3.0 ma Vcc = 4.5 V IOL = 12.0 ma Vcc = 3.0 V IOL = 8.0 ma VCC VCC -0.5 VCC -0.5 VCC kω kω V - VCC V - VCC V V V V Remarks I 2 C pin output I 2 C pin output Document Number: Rev. *F Page 138 of 280

139 Parameter Symbol Pin Name Conditions H level input voltage L level input voltage VIH1 VIH3 VIH5 P000,002,003, 005,020,022, 024,026,150, 151,035,041, 045,055,057, ,081, 082,093,096, 097, , 111,115,116, 122,126,130, 134,142,143, 144,153 Port other than VIH1 RSTX,NMIX,MD 0,MD1 CMOS hysteresis input level Automotive input level CMOS hysteresis input level Value Min Typ Max 0.7 VCC 0.8 VCC 0.8 VCC Unit - VCC V - VCC V - VCC V VIHT DEBUGIF TTL input level 2 - VCC V VIL1 VIL3 VIL5 P000,002,003, 005,020,022, 024,026,150, 151,035,041, 045,055,057, ,081, 082,093,096, 097, , 111,115,116, 122,126,130, 134,142,143, 144,153 Port other than VIH1 RSTX,NMIX,MD 0,MD1 CMOS hysteresis input level Automotive input level CMOS hysteresis input level Vss - Vss - Vss VCC 0.5 VCC 0.2 VILT DEBUGIF TTL input level Vss V VCC V V V Remarks *: It is a standard in BRAMSC (Backup RAM sleep control bit) = 1 (Enter the state of the sleep at the standby mode) condition. Document Number: Rev. *F Page 139 of 280

140 AC Characteristics (1) Main Clock Timing (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Source oscillation clock frequency Source oscillation clock cycle time Internal operating clock frequency *1 Internal operating clock cycle time *1 CAN PLL jitter (during lock) Symbol FC Pin Name X0, X1 Conditions - Value Min Typ Max Unit MHz tcyl X0, X ns FCP FCPP 1 40 FCPT tcp tcpp tcpt MHz tpj ns ns Remarks CPU clock Peripheral bus clock External bus clock (When VCC = 5.0 V is used) *2 External bus clock (When VCC = 3.3 V is used) CPU clock Peripheral bus clock External bus clock (When VCC = 5.0 V is used) External bus clock (When VCC = 3.3 V is used) FCP = 80 MHz (4 MHz Multiplied by 20) Built-in CR oscillation frequency FCCR khz *1: The maximum / minimum value is defined when using the main clock and PLL clock. *2: Please use it with external load capacity 12 pf or less for VCC = 3.3 V ± 0.3 V (40 MHz operation). X0,X1 clock timing t CYL X0 Document Number: Rev. *F Page 140 of 280

141 CAN PLL jitter Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles. Document Number: Rev. *F Page 141 of 280

142 (1-2) Sub clock timing (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Source oscillation clock frequency Source oscillation clock cycle time Symbol FCL Pin Name X0A, X1A Conditions - Value Min Typ Max Unit khz tlcyl X0A, X1A µs Remarks X0A,X1A clock timing t LCYL X0A Document Number: Rev. *F Page 142 of 280

143 Guaranteed operation range Internal operation clock frequency vs. Power supply voltage MB91F52x recommended guaranteed operation range Power supply voltage VCC (V) MB91F52x guaranteed operation range PLL guaranteed operation range 2 4 Internal operation clock frequency F CP (MHz) 80 Note: The power supply voltage, which is the low-voltage detection setting voltage or lower, is in the reset state. Document Number: Rev. *F Page 143 of 280

144 Oscillation clock frequency vs. Internal operation clock frequency Internal operation clock frequency PLL clock Main Clock Multiplied Multiplied Multiplied Multiplied... by 1 by 2 by 3 by 4 Oscillation clock frequency Example of oscillation circuit Multiplied by 19 Multiplied by 20 4 MHz 2 MHz 4 MHz 8 MHz 12 MHz 16 MHz MHz 80 MHz X0 X1 4MHz R=0Ω C1=10pF C2=10pF Note: As to the product with its clock supervisor s initial value is ON, when the oscillator is unable to start within 20 ms from the stop state the clock supervisor will detect the oscillation stop. As a result, the CPU moves to the fail safe operation. Design your print circuit board so that the oscillator can start oscillation within 20 ms. Moreover, it is recommended to be designed after the match evaluation of the circuit is requested to the departure pendulum maker when the oscillation circuit is composed. Document Number: Rev. *F Page 144 of 280

145 AC characteristics are specified by the following measurement reference voltage values. Input Signal Waveform Hysteresis Input Pin (Automotive) 0.8Vcc 0.5Vcc Output Signal Waveform Output Pin 2.4V 0.8V Hysteresis Input Pin (CMOS schmitt) 0.7Vcc 0.3Vcc Document Number: Rev. *F Page 145 of 280

146 (2) Reset Input (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks When normal 10 µs operation Reset input time Oscillation time of At Stop mode µs trstl RSTX oscillator* +100 At Power-on *2 100 µs At Watch mode Width for reset 1 µs input removal *1: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90 %. For crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is between several hundred μs and several ms, and for an external clock, the time is 0 ms. *2: In case of using MB91F52xxxD or MB91F52xxxE and corresponding to note in (3) Power-on Conditions of next subsection, assert RSTX with power-on. trstl RSTX 0.2 v cc 0.2 v cc At Stop mode trstl RSTX 0.2 V CC 0.2 V CC X0 90% of amplitude Internal operation clock Oscillation time of oscillator 100 μs Oscillation stabilization waiting time Internal reset Instruction execution Document Number: Rev. *F Page 146 of 280

147 (3) Power-on Conditions (3-1) [MB9152xxxB/MB9152xxxC/MB9152xxxD] (TA: -40 C to +125 C, VSS = 0.0 V) Parameter Level detection voltage Level detection hysteresis width Symbol Pin Name Conditions Value Min Typ Max VCC V Unit VCC 100 mv Level detection time 30 µs *1 Power off time t VCC 50 ms *2 Remarks VCC: Power ramp rate dv/dt VCC 4 mv/µs *3 0.2 V to V C pin voltage at C 60 mv *4 Power-on *1: This spec is at 4 mv/µs of power ramp rate. If the power ramp rate is faster than 4mV/µs, there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: Vcc must be held below 0.2 V for a minimum period of t. *3: Power-on can detect by satisfying power ramp rate when power off time is not satisfied. *4: C-pin voltage is below 60 mv when VCC is turned on again. Note: When using MB91F52xxxB/C, either *2 or *3 or *4 must be satisfied. When neither *2 nor *3 nor *4 can be satisfied, use MB91F52xxxD and assert external reset (RSTX) at power-up and at any brownout event. Power off time, Power ramp rate, C pin voltage at Power-on t VCC 0.2V 0.2V dv/dt C pin =60mV 60mV Document Number: Rev. *F Page 147 of 280

148 (3-2) [MB9152xxxE] (TA: -40 C to +125 C, VSS = 0.0 V) Parameter Level detection voltage Level detection hysteresis width Symbol Pin Name Conditions Value Min Typ Max VCC V Unit VCC 100 mv Level detection time 30 µs *1 Power off time Power ramp rate t1 VCC Vcc 0.2 V 50 ms *2 t2 VCC Vcc 1.3 V 100 µs *4 dv/dt VCC VCC: 0.2 V to V (t1 <50 ms ) 50 mv/µs *3 Remarks dv/dt VCC VCC: 1.3 V to V (t2 100 µs) 1000 mv/µs *4 C pin voltage at Power-on C 60 mv *5 Maximum ramp rate VCC: guaranteed to not dv/dt Vcc Between 2.4 V generate power-on and 4.5 V reset 50 mv/µs *6 *1: The specified level detection time applies only for power ramp rate of 1000 mv/µs or less. *2: Vcc must be held below 0.2 V for a minimum period of t1. *3: Power-on can detect by satisfying power ramp rate when t1 is not satisfied. *4: Vcc must be held below 1.3 V for a minimum period of t2. Power ramp rate must be 1000 mv/µs or less from 1.3 V to V. Power-on can detect by satisfying power ramp rate and power off time. *5: C-pin voltage is below 60 mv when VCC is turned on again. *6: This specification is specified the power supply fluctuation after power on detection. When VCC voltage is between 2.4 V and 4.5 V, the power supply fluctuation is below 50 mv/us, the detection of power-on is suppressed. The power-on does not detect in any power fluctuation between 4.5 V and 5.5 V. Note: When using MB91F52xxxE, either *2 or *3 or *4 or *5 must be satisfied. When neither *2 nor *3 nor *4 nor *5 can be satisfied, assert external reset (RSTX) at power-up and at any brownout event. Power off time, Power ramp rate, C pin voltage at Power-on t 1 *2 *3 *4 *5 VCC 50ms VCC 50mV/us VCC 100us 2.376V VCC dv/dt 1.3V 1.3V dv/dt 0.2V 0.2V t 2 C pin 60mV =60mV Document Number: Rev. *F Page 148 of 280

149 Maximum ramp rate guaranteed to not generate power-on reset VCC dv/dt 5.5V dv/dt 4.5V 2.4V Document Number: Rev. *F Page 149 of 280

150 (4) Multi-function Serial (4-1) CSIO timing (4-1-1) Bit setting: SMR: MD2 = 0, SMR: MD1 = 1, SMR : MD0 = 0, SMR: SCINV = 0, SCR:SPI = 0 (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V±0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Serial clock cycle time tscyc SCK0 to SCK11 4tCPP - ns SCK SOT delay time Valid SIN SCK setup time tslovi tivshi SCK0 to SCK2, SCK5 to SCK11 SOT0 to SOT2, SOT5 to SOT11 SCK3, SCK4 SOT3, SOT4 SCK0 to SCK2, SCK5 to SCK11 SIN0 to SIN2, SIN5 to SIN11 SCK3, SCK4 SIN3, SIN ns ns 34 - ns ns Internal shift clock mode output pin : CL = 50 pf SCK Valid SIN hold time tshixi SCK0 to SCK11 SIN0 to SIN ns Serial clock "H"pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK setup time SCK Valid SIN hold time tshsl tslsh tslove SCK0 to SCK11 SCK0 to SCK2, SCK5 to SCK11 SOT0 to SOT2, SOT5 to SOT11 SCK3, SCK4 SOT3, SOT4 - tcpp+10 - ns 2tCPP ns - 33 ns ns tivshe 10 - ns SCK0 to SCK11 SIN0 to SIN11 tshixe 20 - ns SCK fall time tf SCK0 to SCK11-5 ns External shift clock mode output pin: CL = 50 pf SCK rise time tr SCK0 to SCK11-5 ns Notes: AC characteristic in CLK synchronized mode. CL is the load capacitance applied to pins during testing. The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and ch.4 with maximum baud rate 400 kbps or less. See Hardware Manual for details. Document Number: Rev. *F Page 150 of 280

151 Internal shift clock mode t SCYC SCKx 0.8V 2.4V 0.8V t SLOVI SOTx 2.4V 0.8V tivshi tshixi SINx VIH1 VIL1 VIH1 VIL1 External shift clock mode tslsh tshsl SCKx VIH1 VIL1 VIL1 VIH1 tf tslove tr SOTx 2.4V 0.8V tivshe tshixe SINx VIH1 VIL1 VIH1 VIL1 Document Number: Rev. *F Page 151 of 280

152 (4-1-2) Bit setting: SMR: MD2 = 0, SMR: MD1 = 1, SMR : MD0 = 0, SMR: SCINV = 1, SCR:SPI = 0 (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions Serial clock cycle time SCK SOT delay time Valid SIN SCK setup time SCK Valid SIN hold time Serial clock "H"pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK setup time SCK Valid SIN hold time tscyc tshovi tivsli tslixi tshsl SCK0 to SCK11 SCK0 to SCK2, SCK5 to SCK11 SOT0 to SOT2, SOT5 to SOT11 SCK3, SCK4 SOT3, SOT4 SCK0 to SCK2, SCK5 to SCK11 SIN0 to SIN2, SIN5 to SIN11 SCK3, SCK4 SIN3, SIN4 SCK0 to SCK11 SIN0 to SIN11 SCK0 to SCK Min Value Max Unit 4tCPP - ns ns ns 34 - ns ns 0 - ns tcpp+10 - ns tslsh 2tCPP-10 - ns tshove SCK0 to SCK2, SCK5 to SCK11 SOT0 to SOT2, SOT5 to SOT11 SCK3, SCK4 SOT3, SOT4-33 ns ns tivsle 10 - ns SCK0 to SCK11 SIN0 to SIN11 tslixe 20 - ns SCK fall time tf SCK0 to SCK11-5 ns Remarks Internal shift clock mode output pin : CL = 50 pf External shift clock mode output pin: CL = 50 pf SCK rise time tr SCK0 to SCK11-5 ns Notes: AC characteristic in CLK synchronized mode. CL is the load capacitance applied to pins during testing. The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and ch.4 with maximum baud rate 400 kbps or less. See Hardware Manual for details. Document Number: Rev. *F Page 152 of 280

153 Internal shift clock mode t SCYC SCKx 2.4V 0.8V 2.4V t SHOVI SOTx 2.4V 0.8V tivsli tslixi SINx VIH1 VIL1 VIH1 VIL1 External shift clock mode tshsl tslsh SCKx VIH1 VIL1 VIL1 VIH1 tr tshove tf SOTx 2.4V 0.8V tivsle tslixe SINx VIH1 VIL1 VIH1 VIL1 Document Number: Rev. *F Page 153 of 280

154 (4-1-3) Bit setting: SMR : MD2 = 0, SMR:MD1 = 1, SMR : MD0 = 0, SMR:SCINV = 0, SCR:SPI = 1 (TA:-40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Serial clock cycle time tscyc SCK0 to SCK11 4tCPP - ns SCK SOT delay time Valid SIN SCK setup time tshovi tivsli SCK0 to SCK2, SCK5 to SCK11 SOT0 to SOT2, SOT5 to SOT11 SCK3, SCK4 SOT3, SOT4 SCK0 to SCK2, SCK5 to SCK11 SIN0 to SIN2, SIN5 to SIN11 SCK3, SCK4 SIN3, SIN ns ns 34 - ns ns Internal shift clock mode output pin : CL = 50 pf SCK Valid SIN hold time tslixi SCK0 to SCK11 SIN0 to SIN ns SOT SCK delay time tsovli SCK0 to SCK11 SOT0 to SOT11 2tCPP ns Serial clock "H"pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK setup time SCK Valid SIN hold time tshsl tslsh tshove SCK0 to SCK11 SCK0 to SCK2, SCK5 to SCK11 SOT0 to SOT2, SOT5 to SOT11 SCK3, SCK4 SOT3, SOT4 - tcpp+ 10 2tCPP ns - ns - 33 ns ns tivshe 10 - ns SCK0 to SCK11 SIN0 to SIN11 tslixe 20 - ns External shift clock mode output pin: CL = 50 pf SCK fall time tf SCK0 to SCK11-5 ns SCK rise time tr SCK0 to SCK11-5 ns Notes: AC characteristic in CLK synchronized mode. CL is the load capacitance applied to pins during testing. The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and ch.4 with maximum baud rate 400 kbps or less. See Hardware Manual for details. Document Number: Rev. *F Page 154 of 280

155 Internal shift clock mode t SCYC SCKx 0.8V 2.4V t SHOVI 0.8V t SOVLI SOTx 2.4V 0.8V 2.4V 0.8V t IVSLI t SLIXI SINx VIH VIL VIH VIL External shift clock mode t SLSH t SHSL SCKx VIH VIH VIH VIL VIL VIL * t F t R t SHOVE SOTx 2.4V 0.8V 2.4V 0.8V tivshe t IVSLE t SLIXE SINx VIH VIL VIH VIL *: It writes in the TDR register and, then, it changes. Document Number: Rev. *F Page 155 of 280

156 (4-1-4) Bit setting: SMR : MD2 = 0, SMR:MD1 = 1, SMR : MD0 = 0, SMR:SCINV = 1, SCR:SPI = 1 (TA:-40 C to +125 C, VCC = A VCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ±0.3 V, VSS = AVSS = 0.0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Serial clock cycle time tscyc SCK0 to SCK11 4tCPP - ns SCK SOT delay time Valid SIN SCK setup time tslovi tivshi SCK0 to SCK2, SCK5 to SCK11 SOT0 to SOT2, SOT5 to SOT11 SCK3, SCK4 SOT3, SOT4 SCK0 to SCK2, SCK5 to SCK11 SIN0 to SIN2, SIN5 to SIN11 SCK3, SCK4 SIN3, SIN ns ns 34 - ns ns Internal shift clock mode output pin : CL = 50 pf SCK Valid SIN hold time tshixi SCK0 to SCK11 SIN0 to SIN ns SOT SCK delay time tsovhi SCK0 to SCK11 SOT0 to SOT11 2tCPP-30 - ns Serial clock "H"pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK setup time SCK Valid SIN hold time tshsl SCK0 to SCK11 - tcpp+10 - ns tslsh 2tCPP-10 - ns tslove SCK0 to SCK2, SCK5 to SCK11 SOT0 to SOT2, SOT5 to SOT11 SCK3, SCK4 SOT3, SOT4-33 ns ns tivshe 10 - ns SCK0 to SCK11 SIN0 to SIN11 tshixe 20 - ns External shift clock mode output pin: CL = 50 pf SCK fall time tf SCK0 to SCK11-5 ns SCK rise time tr SCK0 to SCK11-5 ns Notes: AC characteristic in CLK synchronized mode. CL is the load capacitance applied to pins during testing. The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and ch.4 with maximum baud rate 400 kbps or less. See Hardware Manual for details. Document Number: Rev. *F Page 156 of 280

157 Internal shift clock mode t SCYC SCKx t SOVHI 2.4V 2.4V 0.8V t SLOVI SOTx 2.4V 0.8V 2.4V 0.8V t IVSHI t SHIXI SINx VIH VIL VIH VIL External shift clock mode SCKx t SHSL t SLSH t R t t F F VIH VIH VIH VIL VIL VIL SOTx * 2.4V 0.8V t SLOVE 2.4V 0.8V t IVSHE t SHIXE SINx VIH VIL VIH VIL *: It writes in the TDR register and, then, it changes. Document Number: Rev. *F Page 157 of 280

158 (4-1-5) Bit setting: SMR:MD2 = 0, SMR:MD1 = 1, SMR:MD0 = 0, When Serial chip select is used : SCSCR:CSEN = 1, Serial clock output mark level "H" : SMR,SCSFR:SCINV = 0, Serial chip select Inactive level "H" : SCSCR,SCSFR:CSLVL = 1 (TA:-40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V±0.3 V, VSS = AVSS = 0.0V) Parameter Symbol Pin Name Conditions SCS SCK setup time SCK SCS hold time SCS deselect time tcssi tcshi tcsdi SCK1, SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS43 SCK1, SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS43 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 - Min tcssu-50 *1 tcssu-50 *1 tcshd-10 *2 tcshd-300 *2 tcsds-50 *3 Value Max tcssu+0 *1 tcssu+300 *1 tcshd+50 *2 tcshd+50 *2 Unit ns ns ns ns tcsds+50 *3 ns Remarks Internal shift clock mode output pin : CL = 50 pf Document Number: Rev. *F Page 158 of 280

159 Parameter Symbol Pin Name Conditions SCS SCK setup time SCK SCS hold time SCS deselect time SCS SOT delay time SCS SOT delay time SCK SCS clock switch time tcsse tcshe tcsde tdse tdee tscc SCK1 to SCK11 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SOT1, SOT2, SOT5 to SOT11 SCS3, SCS40 to SCS43 SOT3, SOT4 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SOT1 to SOT11 SCK1, SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS43 - Min 3tCPP tCPP+30 Value Max Unit - ns - ns - ns - 40 ns ns ns - 3tCPP-10 3tCPP+50 ns 3tCPP-300 3tCPP+50 ns Remarks External shift clock mode output pin: CL = 50 pf External shift clock mode output pin: CL = 50 pf Internal shift clock mode Round operation output pin: CL = 50 pf *1: tcssu = SCSTR:CSSU7-0 Serial chip select timing operating clock *2: tcshd = SCSTR:CSHD7-0 Serial chip select timing operating clock *3: tcsds = SCSTR:CSDS15-0 Serial chip select timing operating clock Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take at least five peripheral bus clock cycles to be active again Please see the hardware manual for details of above-mentioned *1,*2, and *3. Document Number: Rev. *F Page 159 of 280

160 SCS output tcsdi tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) When Serial chip select is used, Serial clock output mark level "H",Serial chip select Inactive level "H" Internal shift clock mode SCS input tcsde tcsse tcshe SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) When Serial chip select is used, Serial clock output mark level "H",Serial chip select Inactive level "H" External shift clock mode Document Number: Rev. *F Page 160 of 280

161 SCSx output tscc SCSy output SCK output When Serial chip select is used, Serial clock output mark level "H",Serial chip select Inactive level "H" Internal shift clock mode, Example of switching clock by round operation (x,y=0,1,2,3) Document Number: Rev. *F Page 161 of 280

162 (4-1-6) Bit setting: SMR:MD2 = 0, SMR:MD1 = 1, SMR:MD0 = 0, When Serial chip select is used : SCSCR:CSEN = 1, Serial clock output mark level "L" : SMR,SCSFR:SCINV = 1, Serial chip select Inactive level "H" : SCSCR,SCSFR:CSLVL = 1 (TA:-40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0V) Parameter Symbol Pin Name Conditions SCS SCK setup time SCK SCS hold time SCS deselect time tcssi tcshi tcsdi SCK1, SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS43 SCK1, SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS43 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 - Min tcssu-50 *1 tcssu-50 *1 tcshd-10 *2 tcshd-300 *2 tcsds-50 *3 Value Max tcssu+0 *1 tcssu+300 *1 tcshd+50 *2 tcshd+50 *2 Unit ns ns ns ns tcsds+50 *3 ns Remarks Internal shift clock mode output pin : CL = 50 pf Document Number: Rev. *F Page 162 of 280

163 Parameter Symbol Pin Name Conditions SCS SCK setup time SCK SCS hold time SCS deselect time SCS SOT delay time SCS SOT delay time SCK SCS clock switch time tcsse tcshe tcsde tdse tdee tscc SCK1 to SCK11 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SOT1, SOT2, SOT5 to SOT11 SCS3, SCS40 to SCS43 SOT3, SOT4 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SOT1 to SOT11 SCK1, SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS43 - Min 3tCPP tCPP+30 Value Max Unit - ns - ns - ns - 40 ns ns ns - 3tCPP-10 3tCPP+50 ns 3tCPP-300 3tCPP+50 ns Remarks External shift clock mode output pin: CL = 50 pf External shift clock mode output pin: CL = 50 pf Internal shift clock mode Round operation output pin: CL = 50 pf *1: tcssu = SCSTR:CSSU7-0 Serial chip select timing operating clock *2: tcshd = SCSTR:CSHD7-0 Serial chip select timing operating clock *3: tcsds = SCSTR:CSDS15-0 Serial chip select timing operating clock Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take at least five peripheral bus clock cycles to be active again Please see the hardware manual for details of above-mentioned *1,*2, and *3 Document Number: Rev. *F Page 163 of 280

164 SCS output tcsdi tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) When Serial chip select is used, Serial clock output mark level "L", Serial chip select Inactive level "H" Internal shift clock mode SCS input tcsde tcsse tcshe SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) When Serial chip select is used, Serial clock output mark level "L", Serial chip select Inactive level "H" External shift clock mode Document Number: Rev. *F Page 164 of 280

165 SCSx output tscc SCSy output SCK output When Serial chip select is used, Serial clock output mark level "L", Serial chip select Inactive level "H" Internal shift clock mode, Example of switching clock by round operation (x,y=0,1,2,3) Document Number: Rev. *F Page 165 of 280

166 (4-1-7) Bit setting: SMR:MD2 = 0, SMR:MD1 = 1, SMR:MD0 = 0, When Serial chip select is used : SCSCR:CSEN = 1, Serial clock output mark level "H" : SMR,SCSFR:SCINV = 0, Serial chip select Inactive level "L" : SCSCR,SCSFR:CSLVL = 0 (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3V±0.3V, VSS = AVSS = 0.0V) Parameter Symbol Pin Name Conditions SCS SCK setup time SCK SCS hold time SCS deselect time tcssi tcshi tcsdi SCK1, SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS43 SCK1 to SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS43 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 - Min tcssu-50 *1 tcssu-50 *1 tcshd-10 *2 tcshd-300 *2 tcsds-50 *3 Value Max tcssu+0 *1 tcssu +300 *1 tcshd+50 *2 tcshd+50 *2 Unit ns ns ns ns tcsds+50 *3 ns Remarks Internal shift clock mode output pin : CL = 50 pf Document Number: Rev. *F Page 166 of 280

167 Parameter Symbol Pin Name Conditions SCS SCK setup time SCK SCS hold time SCS deselect time SCS SOT delay time tcsse tcshe tcsde tdse SCK1 to SCK11 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SOT1, SOT2, SOT5 to SOT11 SCS3, SCS40 to SCS43 SOT3, SOT4 - Min 3tCPP tCPP+3 0 Value Max Unit - ns - ns - ns - 40 ns ns Remarks External shift clock mode output pin: CL = 50 pf SCS SOT delay time SCK SCS clock switch time tdee tscc SCS1 to ~SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SOT1 to SOT11 SCK1, SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS ns - 3tCPP-10 3tCPP tCPP+5 0 3tCPP+5 0 ns External shift clock mode output pin: CL = 50 pf Internal shift clock mode Round operation output pin: CL = 50 pf *1: tcssu = SCSTR:CSSU7-0 Serial chip select timing operating clock *2: tcshd = SCSTR:CSHD7-0 Serial chip select timing operating clock *3: tcsds = SCSTR:CSDS15-0 Serial chip select timing operating clock Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take at least five peripheral bus clock cycles to be active again Please see the hardware manual for details of above-mentioned *1,*2, and *3. ns Document Number: Rev. *F Page 167 of 280

168 tcsdi SCS output tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) When Serial chip select is used, Serial clock output mark level "H", Serial chip select Inactive level "L" Internal shift clock mode tcsde SCS input tcsse tcshe SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) When Serial chip select is used, Serial clock output mark level "H", Serial chip select Inactive level "L" External shift clock mode Document Number: Rev. *F Page 168 of 280

169 SCSx output tscc SCSy output SCK output When Serial chip select is used, Serial clock output mark level "H", Serial chip select Inactive level "L" Internal shift clock mode, Example of switching clock by round operation (x,y=0,1,2,3) Document Number: Rev. *F Page 169 of 280

170 (4-1-8) Bit setting: SMR:MD2 = 0, SMR:MD1 = 1, SMR:MD0 = 0, When Serial chip select is used: SCSCR:CSEN = 1, Serial clock output mark level "L" : SMR,SCSFR:SCINV = 1, Serial chip select Inactive level "L" : SCSCR,SCSFR:CSLVL = 0 (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions SCS SCK setup time SCK SCS hold time SCS deselect time tcssi tcshi tcsdi SCK1, SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS43 SCK1, SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS43 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 - Min tcssu-50 *1 tcssu-50 *1 tcshd-10 *2 tcshd-300 *2 tcsds-50 *3 Value Max tcssu+0 *1 tcssu+300 *1 tcshd+50 *2 tcshd+50 *2 Unit ns ns ns ns tcsds+50 *3 ns Remarks Internal shift clock mode output pin : CL = 50 pf Document Number: Rev. *F Page 170 of 280

171 Parameter Symbol Pin Name Conditions SCS SCK setup time SCK SCS hold time SCS deselect time SCS SOT delay time SCS SOT delay time SCK SCS clock switch time tcsse tcshe tcsde tdse tdee tscc SCK1 to SCK11 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCS1, SCS2, SCS50~SCS53, SCS60~SCS63, SCS70~SCS73, SCS8~SCS11 SOT1, SOT2, SOT5~SOT11 SCS3, SCS40~SCS43 SOT3,SOT4 SCS1 to SCS3, SCS40 to SCS43, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SOT1 to SOT11 SCK1, SCK2, SCK5 to SCK11 SCS1, SCS2, SCS50 to SCS53, SCS60 to SCS63, SCS70 to SCS73, SCS8 to SCS11 SCK3, SCK4 SCS3, SCS40 to SCS43 - Min 3tCPP tCPP+30 Value Max Unit - ns - ns - ns - 40 ns ns ns - 3tCPP-10 3tCPP-300 3tCPP+50 3tCPP+50 ns Remarks External shift clock mode output pin: CL = 50 pf External shift clock mode output pin: CL = 50 pf Internal shift clock mode Round operation output pin: CL = 50 pf *1: tcssu = SCSTR:CSSU7-0 Serial chip select timing operating clock *2: tcshd = SCSTR:CSHD7-0 Serial chip select timing operating clock *3: tcsds = SCSTR:CSDS15-0 Serial chip select timing operating clock Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take at least five peripheral bus clock cycles to be active again Please see the hardware manual for details of above-mentioned *1,*2, and *3. Document Number: Rev. *F Page 171 of 280

172 tcsdi SCS output tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) When Serial chip select is used, Serial clock output mark level "L", Serial chip select Inactive level "L" Master mode tcsde SCS input tcsse tcshe SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) When Serial chip select is used, Serial clock output mark level "L", Serial chip select Inactive level "L" Slave mode Document Number: Rev. *F Page 172 of 280

173 SCSx output tscc SCSy output SCK output When Serial chip select is used, Serial clock output mark level "L", Serial chip select Inactive level "L" Master mode, Example of switching clock by round operation (x,y=0,1,2,3) Document Number: Rev. *F Page 173 of 280

174 (4-2) UART (Asynchronous serial interface) timing Bit setting: SMR : MD2 = 0, SMR:MD1 = 0, SMR : MD0 = 0 Bit setting: SMR : MD2 = 0, SMR:MD1 = 0, SMR : MD0 = 1 When external clock is selected (BGR:EXT = 1) (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Serial clock "L" pulse width tslsh tcpp+10 - ns Serial clock "H"pulse width tshsl tcpp+10 - ns SCK0 to SCK11 - SCK fall time tf - 5 ns output pin: CL = 50 pf SCK rise time tr - 5 ns tr tshsl tf tslsh SCK VIL VIH VIH VIL VIL VIH When external clock is selected Document Number: Rev. *F Page 174 of 280

175 (4-3) LIN Interface (v2.1)( Asynchronous Serial Interface for LIN (v2.1)) timing Bit setting: SMR : MD2 = 0, SMR:MD1 = 1, SMR : MD0 = 1 (TA:-40 C to +125 C, VCC = AVCC = 5.0 V±10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Serial clock "L" pulse width tslsh tcpp+10 - ns Serial clock "H"pulse width tshsl tcpp+10 - ns SCK0 to SCK11 - SCK fall time tf - 5 ns output pin: CL = 50 pf SCK rise time tr - 5 ns tr tshsl tf tslsh SCK VIL VIH VIH VIL VIL VIH When external clock is selected Document Number: Rev. *F Page 175 of 280

176 (4-4) I 2 C timing (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions SCL clock frequency Repeat "start" condition hold time SDA SCL Period of "L" for SCL clock Period of "H" for SCL clock Repeat "start" condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL "Stop" condition setup time SCL SDA Bus-free time between "stop" condition and "start" condition fscl thdsta tlow thigh tsusta thddat tsudat tsusto SCK3 to SCK11 SOT3 to SOT11, (SDA) SCK3 to SCK11, (SCL) SCK3 to SCK11, (SCL) SCK3 to SCK11, (SCL) SCK3 to SCK11, (SCL) SOT3 to SOT11, (SDA) SCK3 to SCK11, (SCL) SOT3 to SOT11, (SDA) SCK3 to SCK11, (SCL) SOT3 to SOT11, (SDA) SCK3 to SCK11, (SCL) CL = 50 pf R = (VP/IOL) *1 Standard Mode Fast Mode* 3 Min Max Min Max Unit khz μs μs μs μs * *3 μs ns μs tbuf μs Remarks Noise filter tsp 2tCPP *4 2tCPP *4 ns Notes: Only ch.3 and ch.4 are standard mode/fast mode correspondence. In ch.5-ch.8, ch.10, and ch.11, only a standard mode is correspondences. *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively. Vp shows that the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current. *2: The maximum thddat only has to be met if the device does not extend the "L" width (tlow) of the SCL signal. *3: A fast mode I 2 C bus device can be used on a standard mode I 2 C bus system as long as the device satisfies the requirement of Document Number: Rev. *F Page 176 of 280

177 "tsudat 250 ns". *4: tcpp is the peripheral clock cycle time. Adjust the clock of the bus in the surrounding to 8 MHz or more when use I 2 C. I 2 C timing SDA t LOW t SUDAT t SUSTA t BUF SCL t HDSTA t HDDAT t HIGH t HDSTA t SP t SUSTO Document Number: Rev. *F Page 177 of 280

178 (5) Timer input timing (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions Input pulse width ttiwh, ttiwl TIN0 to TIN7 ICU0 to ICU9 FRCK0 to FRCK5 TIOA0, TIOA1, TIOB0, TIOB1, AIN0, AIN1, BIN0, BIN1, ZIN0, ZIN1 Min Value Max Unit 4tCPP ns Remarks Timer input timing TINx, ICUx, FRCKx, TIOAx,TIOBx AINx,BINx,ZINx V IH t TIWH V IH V IL t TIWL V IL (6) Trigger input timing (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions Input pulse width ttrgh, ttrgl INT0 to INT15, ADTG, RX0, RX1, RX2 Min Value Max Unit 5tCPP ns Remarks 1 μs At stop mode Trigger input timing t TRGH t TRGL INTx ADTG RXx V IH V IH V IL V IL Document Number: Rev. *F Page 178 of 280

179 (7) NMI input timing (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Input pulse width tnmil NMIX 4tCPP ns NMIX input timing t NMIL NMIX V IH5 V IH5 V IL5 V IL5 (8) Low voltage detection (External low-voltage detection) (TA: -40 C to +125 C, VSS = AVSS = 0.0 V) Parameter Power supply voltage range Detection voltage *3 Hysteresis width Low voltage detection time Power supply voltage regulation Symbol VDP5 Pin Name Conditions VDL VCC *1-8% VHYS Value Min Typ Max Unit V LVD5F _SEL [3:0] +8% V V - Td µs - VCC V/ms *2 Remarks LVD5F_SEL[3:0] are programmable. Refer to the hardware manual. When power-supply voltage rises *1: If the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: Please suppress the change of the power supply within the range of the power-supply voltage regulation to do a low voltage detection by detecting voltage (VDL). *3: The initial detection voltage of the external low voltage detection is 2.8 V ± 8 % (2.576 V to V). This LVD setting cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as this detection level is below the minimum guaranteed MCU operation voltage (2.7 V). Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD. Document Number: Rev. *F Page 179 of 280

180 (9) Low voltage detection (Internal low-voltage detection) (TA: -40 C to +125 C, VSS = AVSS = 0.0 V) Parameter Power supply voltage range Detection voltage *2 Hysteresis width Symbol VRDP5 Pin Name Conditions Value Min Typ Max Unit V *1 VRDL V - VRHYS V Remarks When power-supply voltage falls When power-supply voltage rises Low voltage µs detection time *1: If the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2: The detection voltage of the internal low voltage detection is 0.9 V ± 0.1 V. This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage, as this detection level is below the minimum guaranteed MCU operation voltage. Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD. (10) External bus I/F (synchronous mode) timing (TA: -40 C to +105 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) (external load capacitance 50 pf) Parameter Symbol Pin Name Min Value Max Unit Remarks Cycle time tcyc SYSCLK 25 VCC = 5.0 V ± 10 % *1 - ns VCC = 3.3 V ± 0.3 V ASX delay time tchasl, tchash SYSCLK ASX ns CS0X to CS3X delay time tchcsl, tchcsh SYSCLK CS0X to CS3X ns A00 to A21 delay time tchav, tchax SYSCLK A00 to A ns RDX delay time tchrl, tchrh SYSCLK RDX ns RDX minimum pulse trlrh RDX tcyc ns RWT = 1, set RWT to 1 or more. *2 Data setup RDX time RDX data hold tdsrh 18+tCYC - ns Same as above RDX D16 to D31 trhdh 0 - ns Document Number: Rev. *F Page 180 of 280

181 Parameter Symbol Pin Name Min Value Max Unit Remarks WRnX delay time tchwl, tchwh SYSCLK WR0X, WR1X ns WRnX minimum pulse twlwh WR0X, WR1X tcyc ns WWT = 0 *2 SYSCLK data output time SYSCLK data hold time tchdv SYSCLK D16 to D ns tchdx - 18 ns Set WRCS to 1 or more. SYSCLK address output time tchmav ns SYSCLK address hold time SYSCLK D16 to D31 tchmax - 18 ns In multiplex mode, set as follows: Set CSWR and CSRD to 2 or more. ASCY must satisfy the following conditions because of setting ADCY > ASCY and protocol violation prevention. ADCY +1 ACS + CSRD ADCY +1 ACS + CSWR ASCY + 1 ACS + CSRD ASCY + 1 ACS + CSWR See Hardware Manual for details. *1: Please use it with external load capacity 12 pf or less for VCC = 3.3 V ± 0.3 V (40 MHz operation). *2: If the bus is expanded by automatic wait insertion or RDY input, add time (tcyc the number of expanded cycles) to the rated value. Document Number: Rev. *F Page 181 of 280

182 External bus I/F (synchronous mode, read operation, and multiplex mode) timing t1 t2 t3 t4 tcyc SYSCLK tchasl tchash ASX ASCY=0 tchcsl tchcsh CS0X CS0X~CS3X to CS3X ACS=0 RDCS=0 tchrl tchrh RDX CSRD=2 RWT=1 trlrh tchmav ADCY=1 tchmax D16 D16~D31 to D31 Valid Address Read Data tdsrh trhdh External bus I/F (synchronous mode, read operation, and split mode) timing t1 t2 t3 t4 tcyc SYSCLK ASX tchasl ASCY=0 tchash tchcsl tchcsh CS0X CS0X~CS3X to CS3X ACS=0 RDCS=0 RDX CSRD=0 tchrl RWT=1 trlrh tchrh A00~A21 to A21 tchav Valid Address tchax D16 D16~D31 to D31 Read Data tdsrh trhdh Document Number: Rev. *F Page 182 of 280

183 External bus I/F (synchronous mode, write operation, and multiplex mode) timing t1 t2 t3 t4 tcyc SYSCLK tchasl tchash ASX ASCY=0 CS0X CS0X~CS3X to CS3X ACS=0 tchcsl WRCS=1 tchcsh WR0X WR0X~WR1X to WR1X CSWR=2 WWT=0 tchwl twlwh tchwh tchmav ADCY=1 tchdv tchdx D16 D16~D31 to D31 Valid Address Write Data External bus I/F (synchronous mode, write operation, and split mode) timing t1 t2 t3 t4 tcyc SYSCLK tchasl tchash ASX ASCY=0 CS0X CS0X~CS3X to CS3X ACS=0 tchcsl WRCS=1 tchcsh WR0X~WR1X to WR1X CSWR=0 WWT=0 tchwl twlwh tchwh tchav tchax A00 A00~A21 to A21 Valid Address tchdv tchdx D16 D16~D31 to D31 Write Data Document Number: Rev. *F Page 183 of 280

184 (11) External bus I/F (asynchronous mode) timing (TA: -40 C to +105 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) (external load capacitance 50pF) Parameter Symbol Pin Name Min Value Max Unit Remarks Cycle time tcyc SYSCLK VCC = 5.0 V ± 10 % 25 *1 - ns VCC = 3.3 V ± 0.3 V Address setup RDX time RDX Address hold 2 tcyc + RWT = 1, tasrh 2 tcyc - 12 ns RDX 12 set RWT to 1 or more. *2 A00 to A21 trhah tcyc - 12 tcyc + 12 ns Set RDCS to 1 or more. Data setup RDX time RDX Data hold tdsrh 18 + tcyc RDX - ns D16 to D31 trhdh 0 - ns RWT = 1, set RWT to 1 or more. Address setup WRnX time WRnX Address hold Data setup WRnX time WRnX Data hold taswh WR0X to tcyc - 12 tcyc + 12 ns WWT = 0 *2 WR1X twhah A00 to A21 tcyc - 12 tcyc + 12 ns Set WRCS to 1 or more. tdswh WR0X to WR1X twhdh D16 to D31 tcyc - 16 tcyc - 16 tcyc + 16 ns WWT = 0 *2 tcyc + 16 ns Set WRCS to 1 or more. Address setup ASX time tmasash tcyc-16 tcyc+ 16 ns ASCY = 0 ASX Address hold ASX D16 to D31 tmashah tcyc-16 tcyc + 16 ns In multiplex mode, set as follows: Set CSWR and CSRD to 2 or more. ASCY must satisfy the following conditions because of setting ADCY > ASCY and protocol violation prevention. ADCY +1 ACS + CSRD ADCY +1 ACS + CSWR ASCY + 1 ACS + CSRD ASCY + 1 ACS + CSWR See Hardware Manual for details. *1: Please use it with external load capacity 12 pf or less for VCC = 3.3 V ± 0.3 V (40 MHz operation). *2: If the bus is expanded by automatic wait insertion or RDY input, add time (tcyc the number of expanded cycles) to the rated value. Document Number: Rev. *F Page 184 of 280

185 External bus I/F (asynchronous mode, read operation, and multiplex mode) Timing t1 t2 t3 t4 t5 tcyc SYSCLK ASX ASCY=0 CS0X~CS3X to CS3X ACS=0 RDCS=1 RDX CSRD=2 RWT=1 ADCY=1 D16~D31 to D31 Valid Address Read Data tmasash tmashah tdsrh trhdh External bus I/F (asynchronous mode, read operation, and split mode) Timing t1 t2 t3 t4 t5 tcyc SYSCLK ASX ASCY=0 CS0X CS0X~CS3X to CS3X ACS=0 RDCS=1 RDX CSRD=0 RWT=1 A00 A00~A21 to A21 D16 D16~D31 to D31 Valid Address tasrh Read Data tdsrh trhah trhdh Document Number: Rev. *F Page 185 of 280

186 External bus I/F (asynchronous mode, write operation, and multiplex mode) Timing t1 t2 t3 t4 tcyc SYSCLK ASX ASCY=0 CS0X CS0X~CS3X to CS3X ACS=0 WRCS=1 WR0X WR0X~WR1X to WR1X CSWR=2 WWT=0 D16~D31 to D31 Valid Address ADCY=1 Write Data tmasash tmashah tdswh twhdh External bus I/F (Asynchronous mode, write operation, and split mode) Timing t1 t2 t3 t4 tcyc SYSCLK ASX ASCY=0 CS0X~CS3X to CS3X ACS=0 WRCS=1 WR0X WR0X~WR1X to WR1X CSWR=0 WWT=0 A00 A00~A21 to A21 Valid Address taswh twhah D16 D16~D31 to D31 Write Data tdswh twhdh Document Number: Rev. *F Page 186 of 280

187 (12) External bus I/F (ready) Timing (TA: -40 C to +105 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) (external load capacitance 50 pf) Parameter Symbol Pin Name Min Value Max Unit Remarks Cycle time tcyc SYSCLK 50 - ns If using RDY, set SYSCLK to 20 MHz or less. RDY setup time SYSCLK trdys SYSCLK, RDY 28 - ns SYSCLK RDY hold time trdyh SYSCLK, RDY 0 - ns External bus I/F (ready) Timing t1 t2 t3 t4 t5 t6 tcyc SYSCLK ASX ASCY=0 CS0X~CS3X ACS=0 RDCS=0 RDX CSRD=2 RWT=2 Auto wait cycle RDY trdys trdyh Added cycle by RDY Document Number: Rev. *F Page 187 of 280

188 A/D Converter (1) 12-bit A/D Converter Electrical Characteristics (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Parameter Symbol Pin Name Value Min Typ Max Unit Remarks Resolution bit Total error ±12 LSB Linearity error ± 4.0 LSB Differential linearity error Zero transition voltage VOT AN0 to AN47 Full-scale transition voltage ± 1.9 LSB VFST AN0 to AN47 AVRL- 11.5LSB AVRH- 13.5LSB - - AVRL+ 12.5LSB AVRH+ 10.5LSB Sampling time tsmp µs *1 Compare time tcmp µs *1 A/D conversion time tcnv µs *1 Analog port input current IAIN AN0 to AN µa Analog input voltage VAIN AN0 to AN47 AVRL - AVRH V Reference voltage Power supply current AVRH AVRH V AVRL IA AVSS/ AVRL AVCC* V ma ma IAH µa *2 V 1LSB = (VFST-VOT)/ V 4094 VAVSS VAIN VAVCC Per unit TA: +105 C Per unit TA: +125 C IR ma Per unit AVRH IRH µa *2 Variation between channels - AN0 to AN LSB *1: Time for each channel. *2: Power supply current (VCC = AVCC = 5.0 V) is specified if A/D converter is not operating and CPU is stopped. *3: The power supply current described only current value on A/D converter. The total AVcc current value must be calculated the power supply current for A/D converter and D/A converter. (Note) Please use the clock of 0.5 MHz-20 MHz for the output clock of A/D converter to guarantee accuracy. Document Number: Rev. *F Page 188 of 280

189 (2) Definition of A/D Converter Terms Resolution Linearity error Differential linearity error : Analog variation that is recognized by an A/D converter. : Deviation of the actual conversion characteristics from a straight line that connects the zero transition point (" " " ") to the full-scale transition point (" " " "). : Deviation of the input voltage from the ideal value that is required to change the output code by LSB. Linearity error of digital output N = VNT - {1LSB (N - 1) + VOT} 1LSB [LSB] Differential linearity error of digital output N = V(N + 1) T - VNT 1LSB - 1 LSB [LSB] 1LSB = VFST - VOT 4094 [V] VOT VFST : Voltage at which the digital output changes from 000H to 001 H. : Voltage at which the digital output changes from FFE H to FFF H. Document Number: Rev. *F Page 189 of 280

190 (3) Notes on Using A/D Converter <About the output impedance of the analog input of external circuit> When the external impedance is too high, the sampling period for analog voltages may not be sufficient. In this case, it is recommended to connect the capacitor (approx. 0.1 μf) to the analog input pin. Analog input circuit model R Comparator Analog input During sampling: ON C R C 12-bit A/D 1.9 kω (Max) 8.30 pf (Max) (4.5 V AVCC 5.5 V) 4.3 kω (Max) 8.30 pf (Max) (3.0 V AVCC 3.6 V) Note: Listed values must be considered as reference values. Document Number: Rev. *F Page 190 of 280

191 Flash Memory (1) Electrical Characteristics Value Parameter Min Typ Max Sector erase time Unit ms ms ms ms 8-bit writing time µs 16-bit writing time µs ECC writing time µs Erase cycle* 2 / Data retain time 1,000 cycles/ 20 years, 10,000 cycles/ 10 years, 100,000 cycles/ 5 years Remarks 8 Kbytes sector* 1, excluding internal preprogramming time 8 Kbytes sector* 1, including internal preprogramming time 64 Kbytes sector* 1, excluding internal preprogramming time 64 Kbytes sector* 1, including internal preprogramming time Exclusive of overhead time at system level* 1 Exclusive of overhead time at system level* 1 Exclusive of overhead time at system level* 1 Average TA = +85 C* 3 *1: The guaranteed value for erasure up to 100,000 cycles. *2: Number of erase cycles for each sector. *3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 C). (2) Notes While the Flash memory is written or erased, shutdown of the external power (Vcc) is prohibited. In the application system where Vcc might be shut down while writing or erasing, be sure to turn the power off by using an external voltage detection function. To put it concretely, after the external power supply voltage falls below the detection voltage (VDL * ), hold Vcc at 2.7 V or more within the duration calculated by the following expression: Td * [µs] + (period of PCLK [µs] 257) + 50 [µs] *: See 4.AC Characteristics (8) Low-voltage detection (External low-voltage detection) Document Number: Rev. *F Page 191 of 280

192 D/A Converter (TA: -40 C to +125 C, VCC = AVCC = 5.0 V ± 10 %/VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V) Pin Value Parameter Symbol Condition Unit Name Min Typ Max Remarks Resolution bit Differential linearity error - - ± 3.0 LSB Conversion time µs CL = µs CL = 100 Output impedance Ro DA0, DA kω IA AVCC µa Each channel Power supply current When * 1 powerdown IAH AVCC 7.5 µa Each channel *1: The power supply current described only current value on D/A converter. The total AVcc current value must be calculated the power supply current for D/A converter and A/D converter. Document Number: Rev. *F Page 192 of 280

193 12. Example Characteristics This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value. MB91F526 Document Number: Rev. *F Page 193 of 280

194 MB91F526 Document Number: Rev. *F Page 194 of 280

195 MB91F526 Document Number: Rev. *F Page 195 of 280

196 13. Ordering Information MB91F52xxxB *1 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* 2 MB91F526LWBPMC Yes ON ON MB91F526LYBPMC MB91F526LJBPMC ON MB91F526LLBPMC MB91F525LWBPMC ON ON MB91F525LYBPMC MB91F525LJBPMC ON MB91F525LLBPMC MB91F524LWBPMC ON ON MB91F524LYBPMC MB91F524LJBPMC ON MB91F524LLBPMC MB91F523LWBPMC ON ON MB91F523LYBPMC MB91F523LJBPMC ON MB91F523LLBPMC MB91F522LWBPMC ON ON MB91F522LYBPMC MB91F522LJBPMC ON MB91F522LLBPMC MB91F526LSBPMC None ON ON MB91F526LUBPMC MB91F526LHBPMC ON MB91F526LKBPMC MB91F525LSBPMC ON ON MB91F525LUBPMC MB91F525LHBPMC ON MB91F525LKBPMC MB91F524LSBPMC ON ON MB91F524LUBPMC MB91F524LHBPMC ON MB91F524LKBPMC MB91F523LSBPMC ON ON MB91F523LUBPMC MB91F523LHBPMC ON MB91F523LKBPMC MB91F522LSBPMC ON ON MB91F522LUBPMC MB91F522LHBPMC ON MB91F522LKBPMC LQP 176 pin, Plastic Document Number: Rev. *F Page 196 of 280

197 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* 2 MB91F526KWBPMC Yes ON ON MB91F526KYBPMC MB91F526KJBPMC ON MB91F526KLBPMC MB91F525KWBPMC ON ON MB91F525KYBPMC MB91F525KJBPMC ON MB91F525KLBPMC MB91F524KWBPMC ON ON MB91F524KYBPMC MB91F524KJBPMC ON MB91F524KLBPMC MB91F523KWBPMC ON ON MB91F523KYBPMC MB91F523KJBPMC ON MB91F523KLBPMC MB91F522KWBPMC ON ON MB91F522KYBPMC MB91F522KJBPMC ON MB91F522KLBPMC MB91F526KSBPMC None ON ON MB91F526KUBPMC MB91F526KHBPMC ON MB91F526KKBPMC MB91F525KSBPMC ON ON MB91F525KUBPMC MB91F525KHBPMC ON MB91F525KKBPMC MB91F524KSBPMC ON ON MB91F524KUBPMC MB91F524KHBPMC ON MB91F524KKBPMC MB91F523KSBPMC ON ON MB91F523KUBPMC MB91F523KHBPMC ON MB91F523KKBPMC MB91F522KSBPMC ON ON MB91F522KUBPMC MB91F522KHBPMC ON MB91F522KKBPMC LQS 144 pin, (Lead pitch 0.5 mm) Plastic Document Number: Rev. *F Page 197 of 280

198 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* 2 MB91F526KWBPMC1 Yes ON ON MB91F526KYBPMC1 MB91F526KJBPMC1 ON MB91F526KLBPMC1 MB91F525KWBPMC1 ON ON MB91F525KYBPMC1 MB91F525KJBPMC1 ON MB91F525KLBPMC1 MB91F524KWBPMC1 ON ON MB91F524KYBPMC1 MB91F524KJBPMC1 ON MB91F524KLBPMC1 MB91F523KWBPMC1 ON ON MB91F523KYBPMC1 MB91F523KJBPMC1 ON MB91F523KLBPMC1 MB91F522KWBPMC1 ON ON MB91F522KYBPMC1 MB91F522KJBPMC1 ON MB91F522KLBPMC1 MB91F526KSBPMC1 None ON ON MB91F526KUBPMC1 MB91F526KHBPMC1 ON MB91F526KKBPMC1 MB91F525KSBPMC1 ON ON MB91F525KUBPMC1 MB91F525KHBPMC1 ON MB91F525KKBPMC1 MB91F524KSBPMC1 ON ON MB91F524KUBPMC1 MB91F524KHBPMC1 ON MB91F524KKBPMC1 MB91F523KSBPMC1 ON ON MB91F523KUBPMC1 MB91F523KHBPMC1 ON MB91F523KKBPMC1 MB91F522KSBPMC1 ON ON MB91F522KUBPMC1 MB91F522KHBPMC1 ON MB91F522KKBPMC1 LQN 144 pin, (Lead pitch 0.4 mm) Plastic Document Number: Rev. *F Page 198 of 280

199 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* 2 MB91F526JWBPMC Yes ON ON MB91F526JYBPMC MB91F526JJBPMC ON MB91F526JLBPMC MB91F525JWBPMC ON ON MB91F525JYBPMC MB91F525JJBPMC ON MB91F525JLBPMC MB91F524JWBPMC ON ON MB91F524JYBPMC MB91F524JJBPMC ON MB91F524JLBPMC MB91F523JWBPMC ON ON MB91F523JYBPMC MB91F523JJBPMC ON MB91F523JLBPMC MB91F522JWBPMC ON ON MB91F522JYBPMC MB91F522JJBPMC ON MB91F522JLBPMC MB91F526JSBPMC None ON ON MB91F526JUBPMC MB91F526JHBPMC ON MB91F526JKBPMC MB91F525JSBPMC ON ON MB91F525JUBPMC MB91F525JHBPMC ON MB91F525JKBPMC MB91F524JSBPMC ON ON MB91F524JUBPMC MB91F524JHBPMC ON MB91F524JKBPMC MB91F523JSBPMC ON ON MB91F523JUBPMC MB91F523JHBPMC ON MB91F523JKBPMC MB91F522JSBPMC ON ON MB91F522JUBPMC MB91F522JHBPMC ON MB91F522JKBPMC LQM 120 pin, Plastic Document Number: Rev. *F Page 199 of 280

200 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* 2 MB91F526FWBPMC Yes ON ON MB91F526FYBPMC MB91F526FJBPMC ON MB91F526FLBPMC MB91F525FWBPMC ON ON MB91F525FYBPMC MB91F525FJBPMC ON MB91F525FLBPMC MB91F524FWBPMC ON ON MB91F524FYBPMC MB91F524FJBPMC ON MB91F524FLBPMC MB91F523FWBPMC ON ON MB91F523FYBPMC MB91F523FJBPMC ON MB91F523FLBPMC MB91F522FWBPMC ON ON MB91F522FYBPMC MB91F522FJBPMC ON MB91F522FLBPMC MB91F526FSBPMC None ON ON MB91F526FUBPMC MB91F526FHBPMC ON MB91F526FKBPMC MB91F525FSBPMC ON ON MB91F525FUBPMC MB91F525FHBPMC ON MB91F525FKBPMC MB91F524FSBPMC ON ON MB91F524FUBPMC MB91F524FHBPMC ON MB91F524FKBPMC MB91F523FSBPMC ON ON MB91F523FUBPMC MB91F523FHBPMC ON MB91F523FKBPMC MB91F522FSBPMC ON ON MB91F522FUBPMC MB91F522FHBPMC ON MB91F522FKBPMC LQI 100 pin, Plastic Document Number: Rev. *F Page 200 of 280

201 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* 2 MB91F526DWBPMC Yes ON ON MB91F526DYBPMC MB91F526DJBPMC ON MB91F526DLBPMC MB91F525DWBPMC ON ON MB91F525DYBPMC MB91F525DJBPMC ON MB91F525DLBPMC MB91F524DWBPMC ON ON MB91F524DYBPMC MB91F524DJBPMC ON MB91F524DLBPMC MB91F523DWBPMC ON ON MB91F523DYBPMC MB91F523DJBPMC ON MB91F523DLBPMC MB91F522DWBPMC ON ON MB91F522DYBPMC MB91F522DJBPMC ON MB91F522DLBPMC MB91F526DSBPMC None ON ON MB91F526DUBPMC MB91F526DHBPMC ON MB91F526DKBPMC MB91F525DSBPMC ON ON MB91F525DUBPMC MB91F525DHBPMC ON MB91F525DKBPMC MB91F524DSBPMC ON ON MB91F524DUBPMC MB91F524DHBPMC ON MB91F524DKBPMC MB91F523DSBPMC ON ON MB91F523DUBPMC MB91F523DHBPMC ON MB91F523DKBPMC MB91F522DSBPMC ON ON MB91F522DUBPMC MB91F522DHBPMC ON MB91F522DKBPMC LQH 80 pin, Plastic Document Number: Rev. *F Page 201 of 280

202 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* 2 MB91F526BWBPMC1 Yes ON ON MB91F526BYBPMC1 MB91F526BJBPMC1 ON MB91F526BLBPMC1 MB91F525BWBPMC1 ON ON MB91F525BYBPMC1 MB91F525BJBPMC1 ON MB91F525BLBPMC1 MB91F524BWBPMC1 ON ON MB91F524BYBPMC1 MB91F524BJBPMC1 ON MB91F524BLBPMC1 MB91F523BWBPMC1 ON ON MB91F523BYBPMC1 MB91F523BJBPMC1 ON MB91F523BLBPMC1 MB91F522BWBPMC1 ON ON MB91F522BYBPMC1 MB91F522BJBPMC1 ON MB91F522BLBPMC1 MB91F526BSBPMC1 None ON ON MB91F526BUBPMC1 MB91F526BHBPMC1 ON MB91F526BKBPMC1 MB91F525BSBPMC1 ON ON MB91F525BUBPMC1 MB91F525BHBPMC1 ON MB91F525BKBPMC1 MB91F524BSBPMC1 ON ON MB91F524BUBPMC1 MB91F524BHBPMC1 ON MB91F524BKBPMC1 MB91F523BSBPMC1 ON ON MB91F523BUBPMC1 MB91F523BHBPMC1 ON MB91F523BKBPMC1 MB91F522BSBPMC1 ON ON MB91F522BUBPMC1 MB91F522BHBPMC1 ON MB91F522BKBPMC1 LQD 64 pin, Plastic * 1 : It is only supported for customers who have already adopted it now. We do not recommend adopting new products. * 2 : For details of the package, see Package Dimensions. Document Number: Rev. *F Page 202 of 280

203 14. Ordering Information MB91F52xxxC *1 Part Number Sub Clock CSV Initial Value LVD Initial Value Package *2 MB91F526LWCPMC Yes ON ON MB91F526LYCPMC MB91F526LJCPMC ON MB91F526LLCPMC MB91F525LWCPMC ON ON MB91F525LYCPMC MB91F525LJCPMC ON MB91F525LLCPMC MB91F524LWCPMC ON ON MB91F524LYCPMC MB91F524LJCPMC ON MB91F524LLCPMC MB91F523LWCPMC ON ON MB91F523LYCPMC MB91F523LJCPMC ON MB91F523LLCPMC MB91F522LWCPMC ON ON MB91F522LYCPMC MB91F522LJCPMC ON MB91F522LLCPMC MB91F526LSCPMC None ON ON MB91F526LUCPMC MB91F526LHCPMC ON MB91F526LKCPMC MB91F525LSCPMC ON ON MB91F525LUCPMC MB91F525LHCPMC ON MB91F525LKCPMC MB91F524LSCPMC ON ON MB91F524LUCPMC MB91F524LHCPMC ON MB91F524LKCPMC MB91F523LSCPMC ON ON MB91F523LUCPMC MB91F523LHCPMC ON MB91F523LKCPMC MB91F522LSCPMC ON ON MB91F522LUCPMC MB91F522LHCPMC ON MB91F522LKCPMC LQP 176 pin, Plastic Document Number: Rev. *F Page 203 of 280

204 Part Number Sub Clock CSV Initial Value LVD Initial Value Package *2 MB91F526KWCPMC Yes ON ON MB91F526KYCPMC MB91F526KJCPMC ON MB91F526KLCPMC MB91F525KWCPMC ON ON MB91F525KYCPMC MB91F525KJCPMC ON MB91F525KLCPMC MB91F524KWCPMC ON ON MB91F524KYCPMC MB91F524KJCPMC ON MB91F524KLCPMC MB91F523KWCPMC ON ON MB91F523KYCPMC MB91F523KJCPMC ON MB91F523KLCPMC MB91F522KWCPMC ON ON MB91F522KYCPMC MB91F522KJCPMC ON MB91F522KLCPMC MB91F526KSCPMC None ON ON MB91F526KUCPMC MB91F526KHCPMC ON MB91F526KKCPMC MB91F525KSCPMC ON ON MB91F525KUCPMC MB91F525KHCPMC ON MB91F525KKCPMC MB91F524KSCPMC ON ON MB91F524KUCPMC MB91F524KHCPMC ON MB91F524KKCPMC MB91F523KSCPMC ON ON MB91F523KUCPMC MB91F523KHCPMC ON MB91F523KKCPMC MB91F522KSCPMC ON ON MB91F522KUCPMC MB91F522KHCPMC ON MB91F522KKCPMC LQS 144 pin, (Lead pitch 0.5 mm) Plastic Document Number: Rev. *F Page 204 of 280

205 Part Number Sub Clock CSV Initial Value LVD Initial Value Package *2 MB91F526KWCPMC1 Yes ON ON MB91F526KYCPMC1 MB91F526KJCPMC1 ON MB91F526KLCPMC1 MB91F525KWCPMC1 ON ON MB91F525KYCPMC1 MB91F525KJCPMC1 ON MB91F525KLCPMC1 MB91F524KWCPMC1 ON ON MB91F524KYCPMC1 MB91F524KJCPMC1 ON MB91F524KLCPMC1 MB91F523KWCPMC1 ON ON MB91F523KYCPMC1 MB91F523KJCPMC1 ON MB91F523KLCPMC1 MB91F522KWCPMC1 ON ON MB91F522KYCPMC1 MB91F522KJCPMC1 ON MB91F522KLCPMC1 MB91F526KSCPMC1 None ON ON MB91F526KUCPMC1 MB91F526KHCPMC1 ON MB91F526KKCPMC1 MB91F525KSCPMC1 ON ON MB91F525KUCPMC1 MB91F525KHCPMC1 ON MB91F525KKCPMC1 MB91F524KSCPMC1 ON ON MB91F524KUCPMC1 MB91F524KHCPMC1 ON MB91F524KKCPMC1 MB91F523KSCPMC1 ON ON MB91F523KUCPMC1 MB91F523KHCPMC1 ON MB91F523KKCPMC1 MB91F522KSCPMC1 ON ON MB91F522KUCPMC1 MB91F522KHCPMC1 ON MB91F522KKCPMC1 LQN 144 pin, (Lead pitch 0.4 mm) Plastic Document Number: Rev. *F Page 205 of 280

206 Part Number Sub Clock CSV Initial Value LVD Initial Value Package *2 MB91F526JWCPMC Yes ON ON MB91F526JYCPMC MB91F526JJCPMC ON MB91F526JLCPMC MB91F525JWCPMC ON ON MB91F525JYCPMC MB91F525JJCPMC ON MB91F525JLCPMC MB91F524JWCPMC ON ON MB91F524JYCPMC MB91F524JJCPMC ON MB91F524JLCPMC MB91F523JWCPMC ON ON MB91F523JYCPMC MB91F523JJCPMC ON MB91F523JLCPMC MB91F522JWCPMC ON ON MB91F522JYCPMC MB91F522JJCPMC ON MB91F522JLCPMC MB91F526JSCPMC None ON ON MB91F526JUCPMC MB91F526JHCPMC ON MB91F526JKCPMC MB91F525JSCPMC ON ON MB91F525JUCPMC MB91F525JHCPMC ON MB91F525JKCPMC MB91F524JSCPMC ON ON MB91F524JUCPMC MB91F524JHCPMC ON MB91F524JKCPMC MB91F523JSCPMC ON ON MB91F523JUCPMC MB91F523JHCPMC ON MB91F523JKCPMC MB91F522JSCPMC ON ON MB91F522JUCPMC MB91F522JHCPMC ON MB91F522JKCPMC LQM 120 pin, Plastic Document Number: Rev. *F Page 206 of 280

207 Part Number Sub Clock CSV Initial Value LVD Initial Value Package *2 MB91F526FWCPMC Yes ON ON MB91F526FYCPMC MB91F526FJCPMC ON MB91F526FLCPMC MB91F525FWCPMC ON ON MB91F525FYCPMC MB91F525FJCPMC ON MB91F525FLCPMC MB91F524FWCPMC ON ON MB91F524FYCPMC MB91F524FJCPMC ON MB91F524FLCPMC MB91F523FWCPMC ON ON MB91F523FYCPMC MB91F523FJCPMC ON MB91F523FLCPMC MB91F522FWCPMC ON ON MB91F522FYCPMC MB91F522FJCPMC ON MB91F522FLCPMC MB91F526FSCPMC None ON ON MB91F526FUCPMC MB91F526FHCPMC ON MB91F526FKCPMC MB91F525FSCPMC ON ON MB91F525FUCPMC MB91F525FHCPMC ON MB91F525FKCPMC MB91F524FSCPMC ON ON MB91F524FUCPMC MB91F524FHCPMC ON MB91F524FKCPMC MB91F523FSCPMC ON ON MB91F523FUCPMC MB91F523FHCPMC ON MB91F523FKCPMC MB91F522FSCPMC ON ON MB91F522FUCPMC MB91F522FHCPMC ON MB91F522FKCPMC LQI 100 pin, Plastic Document Number: Rev. *F Page 207 of 280

208 Part Number Sub Clock CSV Initial Value LVD Initial Value Package *2 MB91F526DWCPMC Yes ON ON MB91F526DYCPMC MB91F526DJCPMC ON MB91F526DLCPMC MB91F525DWCPMC ON ON MB91F525DYCPMC MB91F525DJCPMC ON MB91F525DLCPMC MB91F524DWCPMC ON ON MB91F524DYCPMC MB91F524DJCPMC ON MB91F524DLCPMC MB91F523DWCPMC ON ON MB91F523DYCPMC MB91F523DJCPMC ON MB91F523DLCPMC MB91F522DWCPMC ON ON MB91F522DYCPMC MB91F522DJCPMC ON MB91F522DLCPMC MB91F526DSCPMC None ON ON MB91F526DUCPMC MB91F526DHCPMC ON MB91F526DKCPMC MB91F525DSCPMC ON ON MB91F525DUCPMC MB91F525DHCPMC ON MB91F525DKCPMC MB91F524DSCPMC ON ON MB91F524DUCPMC MB91F524DHCPMC ON MB91F524DKCPMC MB91F523DSCPMC ON ON MB91F523DUCPMC MB91F523DHCPMC ON MB91F523DKCPMC MB91F522DSCPMC ON ON MB91F522DUCPMC MB91F522DHCPMC ON MB91F522DKCPMC LQH 80 pin, Plastic Document Number: Rev. *F Page 208 of 280

209 Part Number Sub Clock CSV Initial Value LVD Initial Value Package *2 MB91F526BWCPMC1 Yes ON ON MB91F526BYCPMC1 MB91F526BJCPMC1 ON MB91F526BLCPMC1 MB91F525BWCPMC1 ON ON MB91F525BYCPMC1 MB91F525BJCPMC1 ON MB91F525BLCPMC1 MB91F524BWCPMC1 ON ON MB91F524BYCPMC1 MB91F524BJCPMC1 ON MB91F524BLCPMC1 MB91F523BWCPMC1 ON ON MB91F523BYCPMC1 MB91F523BJCPMC1 ON MB91F523BLCPMC1 MB91F522BWCPMC1 ON ON MB91F522BYCPMC1 MB91F522BJCPMC1 ON MB91F522BLCPMC1 MB91F526BSCPMC1 None ON ON MB91F526BUCPMC1 MB91F526BHCPMC1 ON MB91F526BKCPMC1 MB91F525BSCPMC1 ON ON MB91F525BUCPMC1 MB91F525BHCPMC1 ON MB91F525BKCPMC1 MB91F524BSCPMC1 ON ON MB91F524BUCPMC1 MB91F524BHCPMC1 ON MB91F524BKCPMC1 MB91F523BSCPMC1 ON ON MB91F523BUCPMC1 MB91F523BHCPMC1 ON MB91F523BKCPMC1 MB91F522BSCPMC1 ON ON MB91F522BUCPMC1 MB91F522BHCPMC1 ON MB91F522BKCPMC1 LQD 64 pin, Plastic * 1 : It is only supported for customers who have already adopted it now. We do not recommend adopting new products. * 2 : For details of the package, see Package Dimensions. Document Number: Rev. *F Page 209 of 280

210 15. Ordering Information MB91F52xxxD Part Number Sub Clock CSV Initial Value LVD Initial Value Package* MB91F526LWDPMC Yes ON ON MB91F526LJDPMC ON MB91F525LWDPMC ON ON MB91F525LJDPMC ON MB91F524LWDPMC ON ON MB91F524LJDPMC ON MB91F523LWDPMC ON ON MB91F523LJDPMC ON MB91F522LWDPMC ON ON MB91F522LJDPMC ON MB91F526LSDPMC None ON ON MB91F526LHDPMC ON MB91F525LSDPMC ON ON MB91F525LHDPMC ON MB91F524LSDPMC ON ON MB91F524LHDPMC ON MB91F523LSDPMC ON ON MB91F523LHDPMC ON MB91F522LSDPMC ON ON MB91F522LHDPMC ON MB91F526KWDPMC Yes ON ON MB91F526KJDPMC ON MB91F525KWDPMC ON ON MB91F525KJDPMC ON MB91F524KWDPMC ON ON MB91F524KJDPMC ON MB91F523KWDPMC ON ON MB91F523KJDPMC ON MB91F522KWDPMC ON ON MB91F522KJDPMC ON MB91F526KSDPMC None ON ON MB91F526KHDPMC ON MB91F525KSDPMC ON ON MB91F525KHDPMC ON MB91F524KSDPMC ON ON MB91F524KHDPMC ON MB91F523KSDPMC ON ON MB91F523KHDPMC ON MB91F522KSDPMC ON ON MB91F522KHDPMC ON LQP 176 pin, Plastic LQS 144 pin, (Lead pitch 0.5 mm) Plastic Document Number: Rev. *F Page 210 of 280

211 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* MB91F526KWDPMC1 Yes ON ON MB91F526KJDPMC1 ON MB91F525KWDPMC1 ON ON MB91F525KJDPMC1 ON MB91F524KWDPMC1 ON ON MB91F524KJDPMC1 ON MB91F523KWDPMC1 ON ON MB91F523KJDPMC1 ON MB91F522KWDPMC1 ON ON MB91F522KJDPMC1 ON MB91F526KSDPMC1 None ON ON MB91F526KHDPMC1 ON MB91F525KSDPMC1 ON ON MB91F525KHDPMC1 ON MB91F524KSDPMC1 ON ON MB91F524KHDPMC1 ON MB91F523KSDPMC1 ON ON MB91F523KHDPMC1 ON MB91F522KSDPMC1 ON ON MB91F522KHDPMC1 ON MB91F526JWDPMC Yes ON ON MB91F526JJDPMC ON MB91F525JWDPMC ON ON MB91F525JJDPMC ON MB91F524JWDPMC ON ON MB91F524JJDPMC ON MB91F523JWDPMC ON ON MB91F523JJDPMC ON MB91F522JWDPMC ON ON MB91F522JJDPMC ON MB91F526JSDPMC None ON ON MB91F526JHDPMC ON MB91F525JSDPMC ON ON MB91F525JHDPMC ON MB91F524JSDPMC ON ON MB91F524JHDPMC ON MB91F523JSDPMC ON ON MB91F523JHDPMC ON MB91F522JSDPMC ON ON MB91F522JHDPMC ON LQN 144 pin, (Lead pitch 0.4 mm) Plastic LQM 120 pin, Plastic Document Number: Rev. *F Page 211 of 280

212 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* MB91F526FWDPMC Yes ON ON MB91F526FJDPMC ON MB91F525FWDPMC ON ON MB91F525FJDPMC ON MB91F524FWDPMC ON ON MB91F524FJDPMC ON MB91F523FWDPMC ON ON MB91F523FJDPMC ON MB91F522FWDPMC ON ON MB91F522FJDPMC ON MB91F526FSDPMC None ON ON MB91F526FHDPMC ON MB91F525FSDPMC ON ON MB91F525FHDPMC ON MB91F524FSDPMC ON ON MB91F524FHDPMC ON MB91F523FSDPMC ON ON MB91F523FHDPMC ON MB91F522FSDPMC ON ON MB91F522FHDPMC ON MB91F526DWDPMC Yes ON ON MB91F526DJDPMC ON MB91F525DWDPMC ON ON MB91F525DJDPMC ON MB91F524DWDPMC ON ON MB91F524DJDPMC ON MB91F523DWDPMC ON ON MB91F523DJDPMC ON MB91F522DWDPMC ON ON MB91F522DJDPMC ON MB91F526DSDPMC None ON ON MB91F526DHDPMC ON MB91F525DSDPMC ON ON MB91F525DHDPMC ON MB91F524DSDPMC ON ON MB91F524DHDPMC ON MB91F523DSDPMC ON ON MB91F523DHDPMC ON MB91F522DSDPMC ON ON MB91F522DHDPMC ON LQI 100 pin, Plastic LQH 80 pin, Plastic Document Number: Rev. *F Page 212 of 280

213 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* MB91F526BWDPMC1 Yes ON ON MB91F526BJDPMC1 ON MB91F525BWDPMC1 ON ON MB91F525BJDPMC1 ON MB91F524BWDPMC1 ON ON MB91F524BJDPMC1 ON MB91F523BWDPMC1 ON ON MB91F523BJDPMC1 ON MB91F522BWDPMC1 ON ON MB91F522BJDPMC1 ON MB91F526BSDPMC1 None ON ON MB91F526BHDPMC1 ON MB91F525BSDPMC1 ON ON MB91F525BHDPMC1 ON MB91F524BSDPMC1 ON ON MB91F524BHDPMC1 ON MB91F523BSDPMC1 ON ON MB91F523BHDPMC1 ON MB91F522BSDPMC1 ON ON MB91F522BHDPMC1 ON LQD 64 pin, Plastic *: For details of the package, see Package Dimensions. Document Number: Rev. *F Page 213 of 280

214 16. Ordering Information MB91F52xxxE Part Number Sub Clock CSV Initial Value LVD Initial Value Package* MB91F526LWEPMC Yes ON ON MB91F526LJEPMC ON MB91F525LWEPMC ON ON MB91F525LJEPMC ON MB91F524LWEPMC ON ON MB91F524LJEPMC ON MB91F523LWEPMC ON ON MB91F523LJEPMC ON MB91F522LWEPMC ON ON MB91F522LJEPMC ON MB91F526LSEPMC None ON ON MB91F526LHEPMC ON MB91F526LKEPMC MB91F525LSEPMC ON ON MB91F525LHEPMC ON MB91F524LSEPMC ON ON MB91F524LHEPMC ON MB91F523LSEPMC ON ON MB91F523LHEPMC ON MB91F522LSEPMC ON ON MB91F522LHEPMC ON MB91F526KWEPMC Yes ON ON MB91F526KJEPMC ON MB91F525KWEPMC ON ON MB91F525KJEPMC ON MB91F524KWEPMC ON ON MB91F524KJEPMC ON MB91F523KWEPMC ON ON MB91F523KJEPMC ON MB91F522KWEPMC ON ON MB91F522KJEPMC ON MB91F526KSEPMC None ON ON MB91F526KHEPMC ON MB91F525KSEPMC ON ON MB91F525KHEPMC ON MB91F524KSEPMC ON ON MB91F524KHEPMC ON MB91F523KSEPMC ON ON MB91F523KHEPMC ON MB91F522KSEPMC ON ON MB91F522KHEPMC ON LQP 176 pin, Plastic LQS 144 pin, (Lead pitch 0.5 mm) Plastic Document Number: Rev. *F Page 214 of 280

215 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* MB91F526KWEPMC1 Yes ON ON MB91F526KJEPMC1 ON MB91F525KWEPMC1 ON ON MB91F525KJEPMC1 ON MB91F524KWEPMC1 ON ON MB91F524KJEPMC1 ON MB91F523KWEPMC1 ON ON MB91F523KJEPMC1 ON MB91F522KWEPMC1 ON ON MB91F522KJEPMC1 ON MB91F526KSEPMC1 None ON ON MB91F526KHEPMC1 ON MB91F525KSEPMC1 ON ON MB91F525KHEPMC1 ON MB91F524KSEPMC1 ON ON MB91F524KHEPMC1 ON MB91F523KSEPMC1 ON ON MB91F523KHEPMC1 ON MB91F522KSEPMC1 ON ON MB91F522KHEPMC1 ON MB91F526JWEPMC Yes ON ON MB91F526JJEPMC ON MB91F525JWEPMC ON ON MB91F525JJEPMC ON MB91F524JWEPMC ON ON MB91F524JJEPMC ON MB91F523JWEPMC ON ON MB91F523JJEPMC ON MB91F522JWEPMC ON ON MB91F522JJEPMC ON MB91F526JSEPMC None ON ON MB91F526JHEPMC ON MB91F525JSEPMC ON ON MB91F525JHEPMC ON MB91F524JSEPMC ON ON MB91F524JHEPMC ON MB91F523JSEPMC ON ON MB91F523JHEPMC ON MB91F522JSEPMC ON ON MB91F522JHEPMC ON LQN 144 pin, (LeaE pitch 0.4 mm) Plastic LQM 120 pin, Plastic Document Number: Rev. *F Page 215 of 280

216 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* MB91F526FWEPMC Yes ON ON MB91F526FJEPMC ON MB91F525FWEPMC ON ON MB91F525FJEPMC ON MB91F524FWEPMC ON ON MB91F524FJEPMC ON MB91F523FWEPMC ON ON MB91F523FJEPMC ON MB91F522FWEPMC ON ON MB91F522FJEPMC ON MB91F526FSEPMC None ON ON MB91F526FHEPMC ON MB91F525FSEPMC ON ON MB91F525FHEPMC ON MB91F524FSEPMC ON ON MB91F524FHEPMC ON MB91F523FSEPMC ON ON MB91F523FHEPMC ON MB91F522FSEPMC ON ON MB91F522FHEPMC ON MB91F526DWEPMC Yes ON ON MB91F526DJEPMC ON MB91F525DWEPMC ON ON MB91F525DJEPMC ON MB91F524DWEPMC ON ON MB91F524DJEPMC ON MB91F523DWEPMC ON ON MB91F523DJEPMC ON MB91F522DWEPMC ON ON MB91F522DJEPMC ON MB91F526DSEPMC None ON ON MB91F526DHEPMC ON MB91F525DSEPMC ON ON MB91F525DHEPMC ON MB91F524DSEPMC ON ON MB91F524DHEPMC ON MB91F523DSEPMC ON ON MB91F523DHEPMC ON MB91F522DSEPMC ON ON MB91F522DHEPMC ON LQI 100 pin, Plastic LQH 80 pin, Plastic Document Number: Rev. *F Page 216 of 280

217 Part Number Sub Clock CSV Initial Value LVD Initial Value Package* MB91F526BWEPMC1 Yes ON ON MB91F526BJEPMC1 ON MB91F525BWEPMC1 ON ON MB91F525BJEPMC1 ON MB91F524BWEPMC1 ON ON MB91F524BJEPMC1 ON MB91F523BWEPMC1 ON ON MB91F523BJEPMC1 ON MB91F522BWEPMC1 ON ON MB91F522BJEPMC1 ON MB91F526BSEPMC1 None ON ON MB91F526BHEPMC1 ON MB91F525BSEPMC1 ON ON MB91F525BHEPMC1 ON MB91F524BSEPMC1 ON ON MB91F524BHEPMC1 ON MB91F523BSEPMC1 ON ON MB91F523BHEPMC1 ON MB91F522BSEPMC1 ON ON MB91F522BHEPMC1 ON LQE 64 pin, Plastic *: For details of the package, see Package Dimensions. Document Number: Rev. *F Page 217 of 280

218 17. Package Dimensions Document Number: Rev. *F Page 218 of 280

219 Document Number: Rev. *F Page 219 of 280

220 Document Number: Rev. *F Page 220 of 280

221 Document Number: Rev. *F Page 221 of 280

222 Document Number: Rev. *F Page 222 of 280

223 Document Number: Rev. *F Page 223 of 280

224 Document Number: Rev. *F Page 224 of 280

225 18. Errata This section describes the errata for the MB91520 Series. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number MB91F522B/D/F/J/K/L MB91F523B/D/F/J/K/L MB91F524B/D/F/J/K/L MB91F525B/D/F/J/K/L MB91F526B/D/F/J/K/L MB91F522/3/4/5/6 Qualification Status Product Status: Production Errata Summary The following table defines the errata applicability to available MB91520 Series devices. Items Part Number Silicon Revision Fix Status [1]. Power-on Conditions is not enough in the Datasheet Specification [2]. Limitation for Watch mode (power off) MB91F522B/D/F/J/K/L MB91F523B/D/F/J/K/L MB91F524B/D/F/J/K/L MB91F525B/D/F/J/K/L MB91F526B/D/F/J/K/L B, C B, C, D, E - Will be fixed in production silicon version D, E 1. Power-on Conditions is not enough in the Datasheet Specification Problem Definition If the Power-On-Reset and Internal Low Voltage Detection are not generated, some port functions will not be available. Parameters Affected t for Power off time on Power-on Conditions VCC Power ramp rate on Power-on Conditions Trigger Condition When the power supply voltage to the MCU has been turned off but has not reached 0 V when the power supply voltage is turned on again, MCU does not generate an internal power-on-reset signal (Power-On reset or Internal LVD reset). Then, some port functions will not be available. If below condition (1) or (2) or (3) is satisfied, Power-On Reset (Initialization-Reset signal) is generated and no problem occurs. (1) The VCC voltage is less than 200 mv for 50 ms or longer (t) (2) VCC Power ramp rate less than 4 mv/µs (dv/dt) until a voltage level for a safe Power-On detection is reached (3) C-pin voltage is below 60 mv when VCC is turned on again Document Number: Rev. *F Page 225 of 280

226 Scope of Impact For the affected parts, when the Power-On Reset and Internal Low Voltage Detection are not generated, the MCU may set invalid package and sub clock option information. Therefore, the MCU may operate with an invalid pin configuration. Workaround For the affected parts, it is necessary to satisfy at least one of the Power-On Reset requirements for any Power-On event as given below: (1) The VCC voltage is less than 200 mv for 50 ms or longer (t) (2) VCC Power ramp rate is less than 4 mv/µs (dv/dt) until a voltage level for a safe Power-On detection is reached (3) C-pin voltage is below 60 mv when VCC is turned on again If the customer system does not satisfy the condition above-mentioned, Cypress will releases new version D, so Cypress recommends the version D for MB91F52x. The new version prevents the limitation when an external reset signal is asserted at pin RSTX anytime the supply voltage (VCC) is turned on. Fix Status Will be fixed in production silicon version D, E 2. Limitation for Watch mode (power off) Problem Definition If the below all trigger conditions (1) to (3) are satisfied, the below registers will be initialized after MCU recovers from watch mode (power off). Trigger Conditions (1) Using the watch mode (power off) (2) Interrupt levels that are used as sources for recovering from the watch mode (power off) are 16 to 30, or using NMIX pin as source for recovering from the watch mode (power off) (3) The sources for recovering from the watch mode (power off) are generated between PCLK 1 cycle and PMUCLK 3 cycles (*), after CPU state changes to the watch mode (power off) (*): In case of PCLK = 0.5 MHz and PMUCLK = 32 khz, it is approx. 2 µs to 100 µs Scope of Impact If the all trigger conditions (1) to (3) are satisfied, the below registers will be initialized after MCU recovers from watch mode (power off). WTCRH, WTCRM, WTCRL CSELR.SCEN CMONR.SCRDY CCRTSELR.CST CCRTSELR.CSC Document Number: Rev. *F Page 226 of 280

227 Workaround It is necessary to satisfy the below both conditions of (1) and (2). (1) Interrupt levels that are used as sources for recovering from the watch mode (power off) are 31, before CPU state changes to the watch mode (power off) (2) Don t use NMIX pin as source for recovering from the watch mode (power off) Fix Status Will not be planned Document Number: Rev. *F Page 227 of 280

228 19. Major Changes Spansion Publication Number: MB91F526L_DS Page Section Change Results Revision Initial release Revision 2.0 Corrected the following description. 3 FEATURES 5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 Automotive input 5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 CMOS hysteresis input Corrected the following description to "Type F, G, I, J, K, M". 33 to 36 I/O CIRCUIT TYPE Schmitt input CMOS hysteresis input Corrected the following description to "Type D, E". I 2 C Schmitt input I 2 C hysteresis input 44 to 49 BLOCK DIAGRAM Corrected the following description. MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L , , ELECTRICAL CHARACTERISTICS 2. Recommended operating conditions ELECTRICAL CHARACTERISTICS 3.DC characteristics ELECTRICAL CHARACTERISTICS 3.DC characteristics ELECTRICAL CHARACTERISTICS 3.DC characteristics ELECTRICAL CHARACTERISTICS 3.DC characteristics ELECTRICAL CHARACTERISTICS 3.DC characteristics ELECTRICAL CHARACTERISTICS 3.DC characteristics ELECTRICAL CHARACTERISTICS 3.DC characteristics Added the following description. *1:When it is used outside recommended operation guarantee range (range of the operation guarantee),contact your sales representative. Moreover, minimum value with an effective external low-voltage detection reset becomes a voltage until generating low-voltage detection reset Corrected the value of "ICCT5 When using sub clock 32kHz TA=+25 C ". Max 1420µA Max 2000µA Corrected the value of "Power supply voltage range". (TA:-40 C to +105 C,Vcc=AVcc=2.7V to 5.5V,VSS=AVSS=0.0V) (TA:-40 C to +105 C,Vcc=AVcc=5.0V±10%/3.3V±0.3V,VSS=AVSS=0.0V) Corrected the value of "Power supply voltage range". (TA:-40 C to +125 C,Vcc=AVcc=2.7V to 5.5V,VSS=AVSS=0.0V) (TA:-40 C to +125 C,Vcc=AVcc=5.0V±10%/3.3V±0.3V,VSS=AVSS=0.0V) Corrected the value of " Pull-up resistance RUP1". Vcc=3.3V±0.3V Min 49 Max 140 Min 45 Max 140 Corrected the following description. Pull-up resistance RUP2 Port pin other than P035,041,093,122 P073,074,076,077 Corrected the value of " Pull-up resistance RUP2". VCC=5.0V±10% Min 25 Max 100 Min 25 Max 60 VCC=3.3V±0.3V Min 49 Max 140 Min 33 Max 90 Added the value of " Pull-up resistance RUP3". Pin name : Port pin other than P035,041,073,074,076,077,093,122 VCC=5.0V±10% Min 25 Max 100 VCC=3.3V±0.3V Min 45 Max 140 Document Number: Rev. *F Page 228 of 280

229 Page Section Change Results 150,152, 154, ,152, 154, ,152, 154, ,152, 154,156 ELECTRICAL CHARACTERISTICS 4. AC characteristics (4) Multi-function Serial (4-1) CSIO timing (4-1-1),(4-1-2),(4-1-3),(4-1-4) ELECTRICAL CHARACTERISTICS 4. AC characteristics (4) Multi-function Serial (4-1) CSIO timing (4-1-1),(4-1-2),(4-1-3),(4-1-4) ELECTRICAL CHARACTERISTICS 4. AC characteristics (4) Multi-function Serial (4-1) CSIO timing (4-1-1),(4-1-2),(4-1-3),(4-1-4) ELECTRICAL CHARACTERISTICS 4. AC characteristics (4) Multi-function Serial (4-1) CSIO timing (4-1-1),(4-1-2),(4-1-3),(4-1-4) (4-1-1),(4-1-4)SCK SOT delay time tslovi (4-1-2),(4-1-3)SCK SOT delay time tshovi Corrected the following description. Pin name: SCK0 to SCK11 SOT0 to SOT11 Value: Min -30 Max 30 Pin name: SCK0 to SCK2,SCK5 to SCK11 SOT0 to SOT2,SOT5 to SOT11 Value: Min -30 Max 30 Pin name: SCK3,SCK4 SOT3,SOT4 Value: Min -300 Max 300 (4-1-1),(4-1-4)Valid SIN SCK setup time tivshi (4-1-2),(4-1-3)Valid SIN SCK setup time tivsli Corrected the following description. Pin name: SCK0 to SCK11 SIN0 to SIN11 Value: Min 34 Max - Pin name: SCK0 to SCK2,SCK5 to SCK11 SIN0 to SIN2,SIN5 to SIN11 Value: Min 34 Max - Pin name: SCK3,SCK4,SIN3,SIN4 Value: Min 300 Max - (4-1-1),(4-1-4)SCK SOT delay time tslove (4-1-2),(4-1-3)SCK SOT delay time tshove Corrected the following description. Pin name: SCK0 to SCK11 SOT0 to SOT11 Value: Min - Max 33 Pin name: SCK0 to SCK2,SCK5 to SCK11 SOT0 to SOT2,SOT5 to SOT11 Value: Min - Max 33 Pin name: SCK3,SCK4 SOT3,SOT4 Value: Min - Max 300 (4-1-1),(4-1-2),(4-1-3),(4-1-4)SCK fall time tf Corrected the following description. Pin name: SCK0 to SCK2,SCK5 to SCK11 Value: Min - Max 5 Pin name: SCK3,SCK4 Value: Min - Max 250 Pin name: SCK0 to SCK11 Value: Min - Max 5 Document Number: Rev. *F Page 229 of 280

230 Page Section Change Results 158,161, 164, ,161, 164, ,161, 164,167 ELECTRICAL CHARACTERISTICS 4. AC characteristics (4) Multi-function Serial (4-1) CSIO timing (4-1-5),(4-1-6),(4-1-7),(4-1-8) ELECTRICAL CHARACTERISTICS 4. AC characteristics (4) Multi-function Serial (4-1) CSIO timing (4-1-5),(4-1-6),(4-1-7),(4-1-8) ELECTRICAL CHARACTERISTICS 4. AC characteristics (4) Multi-function Serial (4-1) CSIO timing (4-1-5),(4-1-6),(4-1-7),(4-1-8) (4-1-5)SCS SCK setup time tcssi (4-1-6)SCS SCK setup time tcssi (4-1-7)SCS SCK setup time tcssi (4-1-8)SCS SCK setup time tcssi Corrected the following description. Pin name: SCK1 to SCK11 SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to SCS11 Value: Min tcssu+0 Max tcssu+50 Pin name: SCK1,SCK2,SCK5 to SCK11 SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to SCS11 Value: Min tcssu-50 Max tcssu+0 Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43 Value: Min tcssu-50 Max tcssu+300 (4-1-5)SCK SCS hold time tcshi (4-1-6)SCK SCS hold time tcshi (4-1-7)SCK SCS hold time tcshi (4-1-8)SCK SCS hold time tcshi Corrected the following description. Pin name: SCK1 to SCK11 SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to SCS11 Value: Min tcshd-50 Max tcshd+0 Pin name: SCK1,SCK2,SCK5 to SCK11 SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to SCS11 Value: Min tcshd-10 Max tcshd+50 Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43 Value: Min tcshd-300 Max tcshd+50 (4-1-5),(4-1-6)SCS SOT delay time tdse (4-1-7),(4-1-8)SCS SOT delay time tdse Corrected the following description. Pin name: SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to SCS11 SOT1 to SOT11 Value: Min - Max 40 Pin name: SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73, SCS8 to SCS11 SOT1,SOT2,SOT5 to SOT11 Value: Min - Max 40 Pin name: SCS3,SCS40 to SCS43 SOT3,SOT4 Value: Min - Max 300 Document Number: Rev. *F Page 230 of 280

231 Page Section Change Results 159,162, 165, ,162, 165, ELECTRICAL CHARACTERISTICS 4. AC characteristics (4) Multi-function Serial (4-1) CSIO timing (4-1-5),(4-1-6),(4-1-7),(4-1-8) ELECTRICAL CHARACTERISTICS 4. AC characteristics (4) Multi-function Serial (4-1) CSIO timing (4-1-5),(4-1-6),(4-1-7),(4-1-8) ELECTRICAL CHARACTERISTICS 5.A/D Converter (1) 12-bit A/D Converter Electrical Characteristics ELECTRICAL CHARACTERISTICS 5.A/D Converter (1) 12-bit A/D Converter Electrical Characteristics ELECTRICAL CHARACTERISTICS 5.A/D Converter (1) 12-bit A/D Converter Electrical Characteristics ELECTRICAL CHARACTERISTICS 5.A/D Converter (1) 12-bit A/D Converter Electrical Characteristics ELECTRICAL CHARACTERISTICS 7.D/A Converter ELECTRICAL CHARACTERISTICS 6.Flash memory (4-1-5)SCK SCS clock switch time tscc (4-1-6)SCK SCS clock switch time tscc (4-1-7)SCK SCS clock switch time tscc (4-1-8)SCK SCS clock switch time tscc Corrected the following description. Pin name: SCK1 to SCK11 SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to SCS11 Value: Min 3tCPP+0 Max 3tCPP+50 Pin name: SCK1,SCK2,SCK5 to SCK11 SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to SCS11 Value: Min 3tCPP-10 Max 3tCPP+50 Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43 Value: Min 3tCPP-300 Max 3tCPP+50 Added the following description. Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take at least five peripheral bus clock cycles to be active again Added the value of "Total error". Total error value Min Typ Max ±12 LSB Corrected the value of "Zero transition voltage". Min AVRL+0.5LSB-20mV Max AVRL+0.5LSB+20mV Min AVRL-11.5LSB Max AVRL+12.5LSB Corrected the value of "Full-scale transition voltage". Min AVRH-1.5LSB-20mV Max AVRH-1.5LSB+20mV Min AVRH-13.5LSB Max AVRH+10.5LSB Added the following description. Parameter : Power supply current IA AVCC*3 *3: The power supply current described only current value on A/D converter. The total AVcc current value must be calculated the power supply current for A/D converter and D/A converter. Added the following description. Parameter : Power supply current *1 *1: The power supply current described only current value on D/A converter.the total Avcc current value must be calculated the power supply current for D/A converter and A/D converter. Parameter: Erase cycle*2/data retain time Deleted the following description. Remarks : "Temperature at writing/erasing Tj<+105 C" Document Number: Rev. *F Page 231 of 280

232 Page Section Change Results ELECTRICAL CHARACTERISTICS 7.D/A Converter EXAMPLE CHARACTERISTICS 192 ORDERING INFORMATION 198 ORDERING INFORMATION 198 ORDERING INFORMATION 199 to 205 ORDERING INFORMATION Corrected the following description. Parameter : Power supply current Symbol IA Pin name AVCC Symbol IAH Pin name AVCC Symbol IA Pin name AVCC Symbol IAH Pin name AVCC Corrected the following description. Watch mode Corrected the following description. ORDERING INFORMATION ORDERING INFORMATION MB91F52xxxB *1 Package Package* 2 Added the following description. * 1 : It is only supported for customers who have already adopted it now. We do not recommend adopting new products. Corrected the following description. For details of the package, see " PACKAGE DIMENSIONS ". * 2 : For details of the package, see " PACKAGE DIMENSIONS ". Added the following description. ORDERING INFORMATION MB91F52xxxC - - Company name and layout design change Document Number: Rev. *F Page 232 of 280

233 Page Section Change Results Cypress Document Number: Rev *B 1 Features 2 Features 6 Product Lineup 6 Product Lineup 7 Product Lineup 7 Product Lineup 8 Product Lineup 8 Product Lineup Corrected the following description. Clock generation (equipped with SSCG function) Main oscillation (4MHz to 16MHz) Sub oscillation (32kHz to 100kHz) or none sub oscillation PLL multiplication rate : 1 to 20 times Clock generation (equipped with SSCG function) Main oscillation (4MHz to 16MHz) Sub oscillation (32kHz) or no sub oscillation PLL multiplication rate : 1 to 20 times Equipped with a 100kHz CR oscillator Corrected the following description. Base timer : Max. 2 channels 16-bit timer Any of four PWM/PPG/PWC/reload timer functions can be selected and used A 32-bit timer can be used in 2 channels of cascade mode Base timer : Max. 2 channels 16-bit timer Any of four PWM/PPG/PWC/reload timer functions can be selected and used As for the PWC function and the reload timer function, a pair of 16-bit timers can be used as one 32-bit timer in the cascaded mode Corrected the following description for Product lineup comparison(64 pin). Multi-Function 8ch Serial Interface Multi-Function 8ch Serial Interface *1 Added the following sentences under Product lineup comparison(64 pin) *1: Only channel 5, channel 6 and channel 11 support the I 2 C (standard mode). Corrected the following description for Product lineup comparison(80 pin). Multi-Function 9ch Serial Interface Multi-Function 9ch Serial Interface *1 Added the following sentences under Product lineup comparison(80 pin) *1: Only channel 5, channel 6 and channel 11 support the I 2 C (standard mode). Corrected the following description for Product lineup comparison(100 pin). Multi-Function 12ch Serial Interface Multi-Function 12ch Serial Interface *1 Added the following sentences under Product lineup comparison(100 pin) *1: Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I 2 C (standard mode). Document Number: Rev. *F Page 233 of 280

234 Page Section Change Results 9 Product Lineup 9 Product Lineup 10 Product Lineup 10 Product Lineup 11 Product Lineup 11 Product Lineup Corrected the following description for Product lineup comparison(120 pin). Multi-Function 12ch Serial Interface Multi-Function 12ch Serial Interface *1 Added the following sentences under Product lineup comparison(120 pin) *1: Only channel 3 and channel 4 support the I 2 C (high-speed mode/standard mode). Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I 2 C (standard mode). Corrected the following description for Product lineup comparison(144 pin). Multi-Function 12ch Serial Interface Multi-Function 12ch Serial Interface *1 Added the following sentences under Product lineup comparison(144 pin) *1: Only channel 3 and channel 4 support the I 2 C (high-speed mode/standard mode). Only channel 5, channel 6, channel 7, channel 8, channel 10 and channel 11 support the I 2 C (standard mode). Corrected the following description for Product lineup comparison(176 pin). Multi-Function 12ch Serial Interface Multi-Function 12ch Serial Interface *1 Added the following sentences under Product lineup comparison(176 pin) *1: Only channel 3 and channel 4 support the I 2 C (high-speed mode/standard mode). Only channel 5, channel 6, channel 7, channel 8, channel 10 and channel 11 support the I 2 C (standard mode). Document Number: Rev. *F Page 234 of 280

235 Page Section Change Results Signals indicated by the shading below deleted in Figure. - Left side 13 Pin Assignment MB91F52xB VSS 1 P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1 2 P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0 3 P027/SCS40_1/PPG27_0/TOT0_0/RTO3_1 4 P032/SCS43_1/PPG30_0/TOT3_0/RTO2_1 5 P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2 6 P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2 7 P151/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1 8 P035/OCU8_1/TOT4_0/AIN0_0/INT11_0 9 P036/OCU7_1/TOT5_0/BIN0_0 10 P040/PPG23_1/TOT7_0/AIN1_0/SIN0_1 11 P041/SIN9_0/ICU9_1/BIN1_0/INT12_0 12 P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0 13 P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2 14 P047/AN45/TRG8_0/TIN3_2/SOT0_1 15 P053/AN44/PPG35_0/INT14_1/SCK0_1 16 Document Number: Rev. *F Page 235 of 280

236 Page Section Change Results - Right side 13 Pin Assignment MB91F52xB 48 P122/SIN6_0/AN31/OCU8_0/INT9_1 47 P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0 46 P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1 45 P110/TX1(64)/SCS63_0/AN22 44 NMIX 43 P105/AN17/PPG13_0 42 P104/AN16/PPG12_0 41 P103/AN15/PPG11_0 40 P102/AN14/PPG10_0/INT10_0 39 AVCC0 38 AVRH0 37 AVSS0/AVRL0 36 P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1 35 P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0 34 P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0 33 VSS Document Number: Rev. *F Page 236 of 280