DRAM Tutorial Lecture. Vivek Seshadri

Transcription

1 DRAM Tutorial Lecture Vivek Seshadri

2 DRAM Module and Chip 2

3 Goals Cost Latency Bandwidth Parallelism Power Energy 3

4 DRAM Chip Bank I/O 4

5 Sense Amplifier top enable Inverter bottom 5

6 Sense Amplifier Two Stable States V DD V DD Logical 1 Logical 0 6

7 Sense Amplifier Operation V TDD 01 V T > V B V0 B 7

8 DRAM Cell Capacitor Empty State Fully Charged State Logical 0 Logical Small Cannot drive circuits Reading destroys the state 8

9 Capacitor to Sense Amplifier 0 V DD 1 1 V DD 0 9

10 DRAM Cell Operation ½V DD +δ ½VV DD 01 0 ½V DD 10

11 DRAM Subarray Building Block for DRAM Chip (Row Buffer) 8Kb 11

12 Address DRAM Bank (8Kb) Bank I/O (64b) Address Data 12

13 Bank I/O Bank I/O Bank I/O Bank I/O DRAM Chip Shared internal bus Bank I/O Bank I/O Bank I/O Bank I/O Memory channel - 8bits 13

14 Row Address DRAM Operation 1 ACTIVATE Row 2 READ/WRITE Column Bank I/O 3 PRECHARGE Column Address Data 14

15 RowClone Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization Vivek Seshadri Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. B. Gibbons, M. A. Kozuch, T. C. Mowry

16 Cache Memory Memory Channel Bottleneck Limited Bandwidth Core Core MC Channel High Energy

17 Cache Memory Goal: Reduce Memory Bandwidth Demand Core Core MC Channel Reduce unnecessary data movement

18 Bulk Data Copy and Initialization Bulk Data Copy src dst Bulk Data Initialization val dst

19 Bulk Data Copy and Initialization Bulk Data Copy src dst Bulk Data Initialization val dst

20 Bulk Copy and Initialization Applications Forking Zero initialization (e.g., security) Checkpointing VM Cloning Deduplication Page Migration Many more

21 Cache Shortcomings of Existing Approach High Energy (3600nJ to copy 4KB) Core Core MC Channel dst src High latency (1046ns to copy 4KB) Interference

22 Cache Our Approach: In-DRAM Copy with Low Cost X High Energy Core Core MC Channel dst? src X High latency X Interference

23 RowClone: In-DRAM Copy 23

24 Two Key Observations 2 Many DRAM cells share the same sense amplifier 1 Any operation on one sense amplifier can be easily performed in bulk 24

25 Bulk Copy in DRAM RowClone ½VV DD ½V DD +δ Data gets copied 01 0 ½V DD 25

26 Fast Parallel Mode Benefits Bulk Data Copy (4KB across a module) Latency 11X Energy 74X 1046ns to 90ns 3600nJ to 40nJ No bandwidth consumption Very little changes to the DRAM chip 26

27 Fast Parallel Mode Constraints Location constraint Source and destination in same subarray Size constraint Entire row gets copied (no partial copy) 1 2 Can still accelerate many existing primitives (copy-on-write, bulk zeroing) Alternate mechanism to copy data across banks (pipelined serial mode lower benefits than Fast Parallel) 27

28 End-to-end System Design Software interface memcpy and meminit instructions Managing cache coherence Use existing DMA support! Maximizing use of Fast Parallel Mode Smart OS page allocation 28

29 Fraction of Memory Traffic Applications Summary 1 Zero Copy Write Read bootup compile forkbench mcached mysql shell 29

30 Compared to Baseline Results Summary 70% 60% 50% 40% 30% 20% 10% IPC Improvement Memory Energy Reduction 0% bootup compile forkbench mcached mysql shell 30