Nonblocking Memory Refresh. Kate Nguyen, Kehan Lyu, Xianze Meng, Vilas Sridharan, Xun Jian
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1 Nonblocking Memory Refresh Kate Nguyen, Kehan Lyu, Xianze Meng, Vilas Sridharan, Xun Jian
2 Latency (ns) History of DRAM 2 Refresh Latency Bus Cycle Time Min. Read Latency DRAM is patented 2000 DDR 2003 DDR DDR DDR th Anniversary of DRAM patent Skipping Refresh (ISCA 12, HPCA 13 HPCA 14, ISCA 15, ISCA 17, MICRO 17 )
3 Issues with Skipping Refresh Tested DRAM chips from different manufacturers 3 Memory Cell Refresh Interval (ms) Y. Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, and O. Mutlu, Flipping bits in memory without accessing them: An experimental study of dram disturbance errors, in 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), pp , June Skipping refresh reduces memory security
4 Why DRAM Refresh Hurts Performance 4 DRAM SRAM address line transistor T1 T3 T4 T2 storage capacitor T5 T6 bit line word line bit bit Blocking Refresh Nonblocking Refresh
5 Our Proposal: Nonblocking Refresh 5 Improve performance while retaining the same level of security as the conventional baseline. Transform DRAM refresh into the static/background refresh in SRAM at the system level. Refresh DRAM in the background without stalling read accesses to refreshing memory blocks.
6 How Nonblocking Refresh Works 6 Nonblocking Refresh Refreshing Memory Block Conventional Refresh Refreshing Memory Block Refreshing Data Calculate Data Pending read requests to the block are stalled
7 Year of operation Leveraging Existing Data for Free 7 Each memory block in server memory Program Data Data (12.5% %) For hardware failure protection Avg % 0% 20% 40% 60% 80% 100% % of pages that remain fault-free, on average For server systems, Nonblocking Refresh can leverage existing underutilized redundant data without storage overheads.
8 Primer on Server Memory Organization 8 Data chip1 Data chip 2 Data chip 3 Example Memory Rank Data chip 4 Chip 1 Chip 2 Fetched Memory Block from Rank
9 Nonblocking Refresh for Server Memory 9 Inaccessible data due to refresh Data chip1 Data chip 2 Data chip 3 Example Memory Rank Data chip 4 Accessible data Chip 1 Chip 2 Fetched Memory Block from Rank Calculate
10 Chip ID Challenge 1: Ensuring Same Amount of Refresh Conventional (blocking) refresh Refreshing (inaccessible) Not refreshing (accessible) Time Refreshing Memory Rank Data chip1 Data chip 2 Data chip 3 Data chip 4 Chip 1 Chip 2
11 Chip ID Challenge 1: Ensuring Same Amount of Refresh Nonblocking Refresh Refreshing (inaccessible) Not refreshing (accessible) Time Refreshing Memory Rank Data chip1 Data chip 2 Data chip 3 Data chip 4 Chip 1 Chip 2
12 Chip ID Challenge 1: Ensuring Same Amount of Refresh Refresh Interval Nonblocking Refresh 1 Time Refreshing (inaccessible) Not refreshing (accessible) 12 Refreshing Memory Rank Data chip1 Data chip 2 Data chip 3 Data chip 4 Chip 1 Chip 2
13 Chip ID Challenge 1: Ensuring Same Amount of Refresh Refresh Interval Nonblocking Refresh Refreshing (inaccessible) Not refreshing (accessible) Time Refreshing Memory Rank Data chip1 Data chip 2 Data chip 3 Data chip 4 Chip 1 Chip 2
14 Challenge 2: Ensuring Memory Write Bandwidth 14 Conventional Systems Nonblocking Refresh Shared Memory Bus 100%/N Rank 1 Shared Memory Bus 0% Refreshing Rank 1 Write Queue 100% 100%/N Rank 2 36 KB/Channel Writeback Cache Write Queue 100% 100% Rank 2 Processor Processor %/N Rank N 0% Rank N
15 Challenge 3: Preserving Baseline Hardware Failure Protection 15 Read a block from a refreshing rank Use the block s existing redundant data: to calculate inaccessible data stored in refreshing chips + to detect unknown hardware errors Hardware Error detected? NO YES Wait for refresh to complete Re-read block from memory Read completes Perform error correction
16 Methodology 16 Two Memory Systems: Intel/AMD Server Memory Systems IBM Server Memory System Baseline: Conventional Refresh: fully compliance with manufacturer specification Insecure Refresh: skips 75% of refresh operations Evaluated 7 multi-threaded and 7 multi-program workloads 16gb and future 32gb DRAM 4 memory channels with 4 ranks per channel
17 Performance Improvement vs. Conventional Refresh Performance Improvement 17 40% 35% 30% 25% 20% 15% 10% 5% 0% -5% -10% Intel/AMD Server Mem IBM Server Mem Intel/AMD Server Mem IBM Server Mem 16Gb 32Gb
18 Performance Improvement vs. Insecure Refresh Performance Improvement 18 10% 8% 6% 4% 2% 0% -2% -4% -6% -8% -10% Intel/AMD Server Mem IBM Server Mem Intel/AMD Server Mem IBM Server Mem 16Gb 32Gb
19 Power Power Consumption 19 9% 7% 5% vs. Conventional Refresh vs. Insecure Refresh 3% 1% -1% -3% -5% Intel/AMD Server Mem IBM Server Mem Intel/AMD Server Mem IBM Server Mem 16Gb 32Gb
20 Nonblocking Refresh on faulty systems vs. on fault-free systems Performance of Systems with Faulty Chips 20 3 Faulty Ranks/Channel 2 Faulty Ranks/Channel 1 Faulty Rank/Channel Average 100% 98% 96% 94% 92% 90% 88% 86% 84% 82% 80% Intel/AMD Server Mem IBM Server Mem Intel/AMD Server Mem IBM Server Mem 16GB 32GB
21 Conclusion 21 Since its invention 50 years ago, DRAM has always required expensive refresh operations that stall accesses to refreshing data. We propose Nonblocking Refresh to refresh data in DRAM without stalling read accesses to refreshing data. For server memory systems, Nonblocking Refresh improves average performance by 16.2% and 30.3% for 16gb and 32gb chips, respectively. Nonblocking Refresh preserves conventional baseline level of security by ensuring the same amount of refresh.
22 Questions? 22
Nonblocking Memory Refresh
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture Nonblocking Memory Refresh Kate Nguyen, Kehan Lyu, Xianze Meng Department of Computer Science Virginia Tech Blacksburg, Virginia
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