Hummingbird: A Low-Cost Superscalar PA-RISC Processor

Transcription

1 Hummingbird: A LowCost Superscalar PARISC Processor Stephen Undy HewlettPackard Hot Chips V Flin HEWLETT Presentation Outline Introduction Design Goals Processor Overview Cost Reduction Performance Scalability Power Reduction and Test Summary r/l"3 HEWLETT 1.3.1

2 Design Goals Minimize System Cost Meet or Exceed Current MidRange Workstation Performance in an EntryLevel System Integer Graphics Multimedia Scalability Low Power Consumption Fully Compliant with PARISC Architecture Design for Manufacturability rj,,, HEWLETT セエZN Processor General Features Core Technologies and Features From PA71 00 High Integration Floating Point and Integer Processors Onchip Instruction Cache Offchip Cache Controller Memory and I/O Controller 2Way Superscalar 2 Integer ALUs Architectural Extensions rj,,, HEWLETT セエZN 13.2

3 Architectural Features Support for LittleEndian Processes PC Emulation and Other Software Support for Uncacheable Memory Pages Enhances Performance of 1/0 Subsystems Support for Multimedia Processing Improves Most Multimedia Applications Addition I Subtraction with Saturation Arithmetic Averaging ShiftandAdd for Multiplication by Constant Pixels, Audio Samples, Text 4X Speed Up L イセ HEWLETT Technology HP's CMOS26B Process 0.8 micron FET's 3level Metal Interconnect 075+ MHz 900,000 Transistors 14mm x 14mm Die Size 432 Pin CostReduced PGA 1.8" x 1.8" 50 mil Interstitial PinGrid HighSpeed Operation wlo Bypass Caps. 5V Vdd, TTL Compatible 1/0 Levels rll:' HEWLETT N セ 1.3.3

4 セ ェセ セ N セ lm System Block Diagram buff8rs(opt) ECC Memory Array LAdO'CI DIIIIi f77b Hummingbird PA7100LC CPU I FPU I MIU U '1,r Bus ConYerter or Expansion 110 (optional) Input! Output Subsystem r/,;;. HEWLETT iizセ Hummingbird (PA7100LC) Memory and 1/0 Interface Instr _ i TLB Level 1 ICache addr instr FP Unit Integer Unit #1 T セL ' data '1 addr External Cache セ data Interface. Integer Unit #2 ' r/,;;. HEWLETT iizセ 1.3.4

5 セ Cache Organization Internal Instr addr. Level 1 ICache TLB Data addr t L.. T, Instr addr InstrucUon Hit Tag RPN Compare External Level 2 ICache DCache PP.l HEWLETT PA7100LC Die Photograph (To Be Completed) イLLセセエZN HEWLETT 1.3.5

6 PARISC Integration Trend D rltiil HEWLETT セエZNi System Cost Reduction Integrated Memory and I/O Controller Direct Connection to DRAMs Single, Combined External Cache Uses Standard SRAMS, DRAMS, and SIMMs Requires Only 12 SRAM's Using x8 Technology With 12ns parts can run to 66MHz Low Power Mature VLSI Technology Reduced Cost Packaging r/,:w HEWLETT 1.3.6

7 イ LL セ System Cost Reduction (Continued) Reduced Multiplier Array with No Degradation to Single Precision Flops Reduced Complexity for LongLatency Flops 64 Entry FullyAssociative TLB Unified TLB with Lookaside Buffer Multimedia Improvements without Dedicated Hardware HEWLETT Superscalar Instruction Bundling Instruction Classes A: Integer ALU Operation Shift/Merge Operation Branch L: Int or FP Load/Store.E: Floating Point Operation Rules Any 2 from sparate classes or 2 integer ALU operation LL bundles for Idw or stw pairs to same doubleword address Dynamic dependency checking rli3 HEWLETT 1.3.7

8 FP Latency and Issue Rates Single Precision Double Precision Add / Sub 2/1 2/1 MUltiply 2/1 3/2 MPYADD / MPYSUB 2/1 3/2 Divide 8/8 15/15 Square Root 8/8 15/15 r/,,:. HEWLETT Virtual Memory Performance 8 Block TLB Entries, Each Map 512K 64MBytes Hardware TLBMiss Handler "Fast" TLB Insert Instructions GR Shadow Registers rltiji HEWLETT セエZii J..3.8

9 セ セ セ セエ ZN Cache Performance External Cache Runs at Processor Frequency Pipelined Stores Address Hashing Cache Miss Optimizations Instruction Streaming StallonUse HitUnderMiss StoreUnderMiss MissUnderMiss Cache Hints Aggressive Instruction Prefetching イ LL セ HEWLETT Instrue Ion re e e Ing + r... Q) (.) ュ ュッセ cache (') prefetc prefetch Q) (')..., Q) セ CD ::::s r 1 DRAM f4...5 セ Level CD 0 E 1 i(') Q) E ICache CD SRAM "",r data Execution Units, I " / instr 'It. HEWL A 1.3.9

10 Memory and I/O Performance Dedicated 54bit Memory Bus + 8 ECC Bits Tightly Coupled to CPU Early Address Issue Critical Doubleword First Uses DRAM Fast Page Mode Supports Extended Data Out Mode DRAMs Dedicated 32bit I/O connection DMA Concurrent with Cache Misses 50MB/sec Sustained CPUControlled Memory to I/O Transfer r".. HEWLETT ':1:. Scalability Wide Range of Processor Frequency 48 Bit Virtual Addressing 8K to 2MBytes of External Cache 4M to 2GBytes of Main Memory Programmable DRAM latency and timing Programmable I/O Bus Frequency r/,,:. HEWLETT GZ セ packard L3.10

11 Low Power Design Limited Use of Dynamic Circuits Elimination of PLAts Automatic PowerUp States TLB FP Megacells Register Files Gating of NonOverlapping Clock Nets r".. HEWLETT セiZN Design for Testability IEEE (JTAG) Compliant Parallel and Serial Block Tests Extensive Scannability SingleStep Capability IDDQ Static Current Testing r,,::. HEWLETT

12 Summary Optimized For Low Cost Systems Performance Was Not Sacrificed Highly Configurable New Features Low Power Low Manufacturing Costs r,,;;. HEWLETT ':1: