Power Reduction Techniques in the Memory System. Typical Memory Hierarchy

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1 Power Reduction Techniques in the Memory System Low Power Design for SoCs ASIC Tutorial Memories.1 Typical Memory Hierarchy On-Chip Components Control edram Datapath RegFile ITLB DTLB Instr Data Cache Cache Second Level Cache (SRAM) Main Memory (DRAM) Secondary Storage (Disk) DEC 21164a (2.0V dd, 0.35µ, 400MHz, 30W max) caches dissipate 25% of the total chip power DEC SA-110 (2.0V dd, 0.35µ, 233MHz, 1W typ) no L2 on-chip I$ (D$) dissipate 27% (16%) of the total chip power Low Power Design for SoCs ASIC Tutorial Memories.2 1

2 Structure of an SRAM 2 L-K Bit Line Storage (RAM) Cell Row Address A K A K+1 A L-1 Row Decoder Word Line Sense Amplifiers Read/Write Circuits M.2 K Amplify swing to rail-to-rail amplitude Local read/write circuitry Column Address A 0 A K-1 Column Decoder Input-Output (M bits) Selects appropriate word from memory row Low Power Design for SoCs ASIC Tutorial Memories.3 SRAM Power Budget 60 Average mw Decoders Word line BL+SA+Cell Write ckt Read ckt 0 128x x64 64x256 Array Size 16K bits 0.5µ technology 10ns cycle time 4.05ns access time 3.3V V dd From Chang, 1997 Low Power Design for SoCs ASIC Tutorial Memories.4 2

3 Low Power SRAM Techniques Standby power reduction Operating power reduction» memory bank partitioning» SRAM cell design» divided word line» bit line segmentation» reduced bit line swing» pulsed word line and bit line isolation Can use the above in combination! Low Power Design for SoCs ASIC Tutorial Memories.5 Memory Bank Partitioning Partition the memory array into smaller banks so that only the addressed bank is activated» improves speed and lowers power» word line capacitance reduced» number of bit cells activated reduced At some point the delay and power overhead associated with the bank decoding circuit dominates (2 to 8 banks typical) Low Power Design for SoCs ASIC Tutorial Memories.6 3

4 Partitioned Memory Structure Row Address Column Address Block Address Block Selector Global Amp/Driver Global Data Bus Advantages: 1. Shorter wires within blocks (both WL and BL pairs) 2. Block address activates only 1 block -> power savings Low Power Design for SoCs ASIC Tutorial Memories.7 I/O SRAM Cell 6-T SRAMs cells reduce static current (leakage) but take more area Reduction of Vth in very low Vdd RAMs suffer from large leakage currents» use multiple threshold devices (memory cells with higher Vth to reduce leakage while peripheral circuits use low Vth to improve speed) BL Q WL Q BL Low Power Design for SoCs ASIC Tutorial Memories.8 4

5 Divided Word Line RAM cells in each row are organized into blocks, memory cells in each block are accessed by a local decoder Only the memory cells in the activated block have their bit line pairs driven» improves speed (by decreasing word line delay)» lowers power dissipation (by decreasing the number of BL pairs activated) Low Power Design for SoCs ASIC Tutorial Memories.9 Divided Word Line Structure Row block WL i Local decoder WL i+1 LWL i LD RAM cell LWL i+1 BL j BL j+1 BL j+m LD BSL Block select line Load capacitance on word line determined by number/size of local decoder» faster word line (since smaller capacitance)» now have to wait for local decoder delay Low Power Design for SoCs ASIC Tutorial Memories.10 5

6 Cells/Block How many cells to put in one block?» Power savings best with 2 cells/block fewest number of bit lines activated» Area penalty worst with 2 cells/block more local decoders and BSL buffers» BSL logic need buffers to drive each BSL 4 and 16 cells/block BSLs are the enable inputs of the column decoder s last stage of 2x4 decoders 2 (8) cells/block need a NOR gate with 2 (8) inputs from the output of the column decoder Low Power Design for SoCs ASIC Tutorial Memories.11 DWL Power Reduction Write Operations Read Operations Cells/block 128x x64 64x x x64 64x % 68.5% 78.4% 80.1% 71.6% 82.9% % 65.5% 77.2% 79.1% 68.3% 82.0% % 60.3% 75.8% 76.6% 62.9% 80.3% % 49.8% 72.6% 70.2% 51.9% 76.7% From Chang, 1997 Low Power Design for SoCs ASIC Tutorial Memories.12 6

7 DWL Area Penalty Cells/block 128x x64 64x % 24.6% 24.8% % 18.5% 18.4% % 16.5% 16.2% % 14.8% 14.5% Low Power Design for SoCs ASIC Tutorial Memories.13 Bit Line Segmentation RAM cells in each column are organized into blocks selected by word lines Only the memory cells in the activated block present a load on the bit line» lowers power dissipation (by decreasing bit line capacitance)» can use smaller sense amps Low Power Design for SoCs ASIC Tutorial Memories.14 7

8 Bit Line Segmented Structure SWL i,j Switch to isolate segment SWL i+n,j BL j LBL i,j LBL i+n,j WL i Address decoder identifies the segment targeted by the row address and isolates all but the targeted segment from the common bit line Has minimal effect on performance Low Power Design for SoCs ASIC Tutorial Memories.15 Reduced Bit Line Swing Limit voltage swing on bit lines to improve both speed and power» need sense amp for each column to sense/restore signal» isolate memory cells from the bit lines after sensing (to prevent the cells from changing the bit line voltage further) - pulsed word line» isolate sense amps from bit lines after sensing (to prevent bit lines from having large voltage swings) - bit line isolation Low Power Design for SoCs ASIC Tutorial Memories.16 8

9 Pulsed Word Line Generation of word line pulses very critical» too short - sense amp operation may fail» too long - power efficiency degraded (because bit line swing size depends on duration of the word line pulse) Word line pulse generation» delay lines (susceptible to process, temp, etc.)» use feedback from bit lines Low Power Design for SoCs ASIC Tutorial Memories.17 Pulsed Word Line Structure Read Word line Dummy bit lines Bit lines Complete Dummy column 10% populated» height set to 10% of a regular column and its cells are tied to a fixed value» capacitance is only 10% of a regular column Low Power Design for SoCs ASIC Tutorial Memories.18 9

10 Pulsed Word Line Timing Read Complete Word line Bit line Dummy bit line V = 0.1V dd V = V dd Dummy bit lines have reached full swing and trigger pulse shut off when regular bit lines reach 10% swing Low Power Design for SoCs ASIC Tutorial Memories.19 Bit Line Isolation bit lines V = 0.1V dd isolate sense Read sense amplifier sense amplifier outputs V = V dd Low Power Design for SoCs ASIC Tutorial Memories.20 10

11 Low Power DRAMs Conventional DRAMs refresh all rows with a fixed single time interval» read/write stalled while refreshing» refresh period -> t ref» refresh rate -> R ref = #rows + t ref» DRAM power = k * (#read/writes + #ref) So have to worry about optimizing refresh operation as well Low Power Design for SoCs ASIC Tutorial Memories.21 Optimizing Refresh Selective refresh architecture (SRA)» add a valid bit to each memory row and only refresh rows with valid bit set» reduces refresh 5% to 80% Variable refresh architecture (VRA)» data retention time of each cell is different» add a refresh period table and refresh counter to each row and refresh with the appropriate period to each row» reduces refresh about 75% From From Ohsawa,, 1995 Low Power Design for SoCs ASIC Tutorial Memories.22 11

12 Cache Power On-chip I$ and D$ (high speed SRAM)» DEC 21164a (2.0V dd, 0.35µ, 400MHz, 30W max) I/D/L2 of 8/8/96KB and 1/1/? associativity caches dissipate 25% of the total chip power» DEC SA-110 (2.0V dd, 0.35µ, 233MHz, 1W typ) I/D of 16/16KB and 32/32 associativity (no L2 on-chip) I$ (D$) dissipate 27% (16%) of the total chip power Improving the power efficiency of caches is critical to the overall system power Low Power Design for SoCs ASIC Tutorial Memories.23 Cache Power Distribution Power in milliwatts ijpeg perl fppp avg Base Configuration: 4-way superscalar 32KB DM L1 I$ 32KB, 4-way SA L1 D$ 32B blocks, write back 128KB, 4-way SA L2 64B blocks, write back 1MB, 8-way SA off-chip L3 128B blocks, write thru L1 I$ L1 D$ L2 Interconnect widths 16B between L1 and L2 32B between L2 and L3 64B between L3 and MM From Ghosh,, 1999 Low Power Design for SoCs ASIC Tutorial Memories.24 12

13 Low Power Cache Techniques SRAM power reduction Cache block buffering Cache subbanking Divided word line Multidivided module (MDM) Modifications to CAM cell (for FA cache and FA TLB) Low Power Design for SoCs ASIC Tutorial Memories.25 Cache Block Buffering Check to see if data desired is in the data output latch from the last cache access (i.e., in the same cache block) Saves energy since not accessing tag and data arrays» minimal overhead hardware Can maintain performance of normal set associative cache Low Power Design for SoCs ASIC Tutorial Memories.26 13

14 Block Buffer Cache Structure disable sensing Address issued by CPU Tag Data Tag Data = = = last_set_# Hit Desired word Low Power Design for SoCs ASIC Tutorial Memories.27 Block Buffering Performance Power in milliwatts L1 I$ L1 D$ L2 Total Same base configuration 4-way superscalar 32KB DM L1 I$... 0 buffers 1 buffer 2 buffers From Ghosh,, 1999 Low Power Design for SoCs ASIC Tutorial Memories.28 14

15 Cache Subbanking Address issued by CPU Tag Tag Data Tag Tag Data subbank 0 subbank 1 Only read from one subbank = = Similar to column multiplexing in SRAMs columns can share precharge and sense amps each subbank has its own decoder Low Power Design for SoCs ASIC Tutorial Memories.29 Hit Desired word Subbanking Performance Power in milliwatts L1 I$ L1 D$ L2 Total Same base configuration 4-way superscalar 32KB DM L1 I$ 4B subbank width conv 16B subbank 16B conv 32B subbank 32B From Ghosh,, 1999 Low Power Design for SoCs ASIC Tutorial Memories.30 15

16 Divided Word Line Cache Same goals as subbanking from byte select bit<0> reduce # of active bit lines WL i LD LD reduce capacitive loading on word and bit lines WL i+1 word<1> word<1> LD word<0> word<0> LD Low Power Design for SoCs ASIC Tutorial Memories.31 Multidivided Module Cache Address issued by CPU With M modules and only one module activated per cycle, load capacitance is reduced by a factor of M (reduces both latency and power) s0-s15 s16-s31 Can combine multidivided module, buffering, and subbanking or divided word line to get the savings of all three Low Power Design for SoCs ASIC Tutorial Memories.32 16

17 Translation Lookaside Buffers Small caches to speed up address translation in processors with virtual memory All addresses have to be translated before cache access» DEC SA-110 (2.0V dd, 0.35µ, 233MHz, 1W typ) I$ (D$) dissipate 27% (16%) of the total chip power TLB 17% of total chip power I$ can be virtually indexed/virtually tagged Low Power Design for SoCs ASIC Tutorial Memories.33 TLB Structure Address issued by CPU (page size = index bits + byte select bits) VA Tag PA Tag Data Tag Data Hit Most TLBs are small (<= 256 entries) and thus fully associative = Hit = Desired word Low Power Design for SoCs ASIC Tutorial Memories.34 17

18 TLB Power Power in milliwatts DM 2 SA 4 SA 8 SA FA From Juan, 1997 Low Power Design for SoCs ASIC Tutorial Memories.35 CAM Design WL<0> Hit WL<1> match<0> word line<0> of data array WL<2> match<1> WL<3> match<2> match<3> bit WL bit Read/Write Circuitry match/write data precharge/match match Low Power Design for SoCs ASIC Tutorial Memories.36 18

19 Low Power CAM Cell bit WL bit bit WL bit match match control Low Power Design for SoCs ASIC Tutorial Memories.37 Key References, Memories Amrutur, Techniques to Reduce Power in Fast Wide Memories, Proc. of SLPE, pp , Angel, Survey of Low Power Techniques for ROMs, Proc. of SLPED, pp. 7-11, Aug Chang, Power-Area Trade-Offs in Divided Word Line Memory Arrays, Journal of Circuits, Systems, Computers, 7(1):49-57, Evans, Energy Consumption Modeling and Optimization for SRAMs, IEEE Journal of SSC, 30(5): , May Itoh, Low Power Memory Design, in Low Power Design Methodologies, pp , KAP, Ohsawa, Optimizing the DRAM Refresh Count, Proc. Of SLPED, pp , Aug Shimazaki, An Automatic Power-Save Cache Memory, Proc. Of SLPE, pp , Yoshimoto, A Divided Word Line Structure in SRAMs, IEEE Journal of SSC, 18: , Low Power Design for SoCs ASIC Tutorial Memories.38 19

20 Key References, Caches Ghose, A 0.5 micron Cache and Its Low Power Variants, Proc. of ISLPED, pp , Juan, Reducing TLB Power Requirements, Proc. of ISLPED, pp , Aug Kin, The Filter Cache: An Energy-Efficient Memory Structure, Proc. of MICRO, pp , Dec Ko, Energy Optimization of Multilevel Cache Architectures, IEEE Trans. On VLSI Systems, 6(2): , June Panwar, Reducing the Frequency of Tag Compares for Low Power I$ Designs, Proc. of ISLPD, pp , Shimazaki, An Automatic Power-Save Cache Memory, Proc. of SLPE, pp , Su, Cache Design Tradeoffs for Power and Performance Optimization, Proc. of ISLPD, pp , Low Power Design for SoCs ASIC Tutorial Memories.39 20