Topics in computer architecture

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1 Topics in computer architecture Sun Microsystems SPARC P.J. Drongowski SandSoftwareSound.net Copyright Paul J. Drongowski

2 Sun Microsystems SPARC Scalable Processor Architecture Computer family sharing same ISA Adaptable (scalable) to different technologies SPARC Application Binary Interface (ABI) General characteristics Integer, floating and coprocessor registers Processor state and status registers 69 basic instructions Linear, 32-bit virtual address space What SPARC does not include I/O registers Cache memories Memory management units (MMU) Design goals High and low-density circuit technologies Outperform CISC competitors on: Performance Cost Time to market High performance floating point Architectural queue Register scoreboarding in FP unit Concurrent execution of integer and floating ops HLL programming with simple compilers Extended Berkeley RISC ISA Multiprocessing Special instructions for multiprocessor systems Fewer data references! suitable for tight

3 Integer unit registers Register windows Number of windows can vary across implementations IU may contain 40 to 520 general registers 8 global registers (always accessible) 8 ins (procedure actual parameters) 8 locals (procedure working storage) 8 outs (which are the 8 ins of the adjacent window) Global register 0 always returns the constant value 0 Window behavior Current Window Pointer CWP is a 5-bit field in Processor Status Word (PSW) save instruction decrements CWP (call) restore instruction increments CWP (return) Overflow trap before save Underflow trap before restore SunOS saves (16) registers on memory stack Observations Windows act like a intraprocedural data cache Reduce number of load and store instructions Decreases chip/cache and cache/memory bandwidth Interprocedural register allocation (IRA) is possible Avoid allocating another window save/restore separated from call/return Management (by OS) Window Invalid Mask (WIM) register Mark window causing under/overflow trap Context switch Save only valid (used) registers Fast trap handling by decrementing CWP Context switch timing (16.67 MHz model 200) Three windows saved (average) 15 microseconds

4 IU state registers Processor Status Register (PSR) User/supervisor bit compatible condition codes 4-bit Processor Interrupt Level (PIL) FPU and CP disable bits Current Window Pointer (CWP) 8-bit version number Window Invalid Mask (WIM) register Trap Base Register (TBR) Base address for trap table 8-bit field identifying type of current trap Data types Byte (8 bits, signed and unsigned) Halfword (16 bits, signed and unsigned) Words (32 bits, signed and unsigned) Single floating (32 bits) Doublewords (64 bits, double floating) Memory Byte addressable (4-gigabytes) Byte 0 is the MSB; Byte 3 is the LSB Words, halfwords, doublewords must align

5 SPARC instructions All instructions are 32 bits long 55 basic integer instructions 14 floating point instructions 2 coprocessor formats Format 1 call instruction 30-bit word displacement Format 2 sethi loads high order 22-bits of register 22-bit branch displacement (PC ± 8Mbytes) Format 3 i = 0! second register specifier i = 1! 13-bit, sign-extended immediate Format 1 op displacement Format 2 (sethi) op op op rd op immediate Format 2 (branch instructions) a cc op displacement Format 3 (Remaining instructions, i = 0) rd op rs1 i rs2 asi Format 3 (Remaining instructions, i = 1) op rd op rs1 i immediate

6 SPARC instructions Load and store Two general addressing modes reg1 + reg2 reg + signed_13-bit_constant Register-indirect and absolute via global register 0 Load and store to alternate address space Limited to operating system use 8-bit Address Space Indentifier (ASI) Integer computational instructions Two source operands and one destination register Second register can be replaced by a 13-bit constant Corresponding instructions (do not) set condition codes Shift over arbitrary number of places Multiply step (mulscc) sethi to construct 32-bit constant values Tagged instructions Tag bits are the two LSB's of the operand Tagged add (taddcc) and subtract (tsubcc) Use overflow bit to decode tag type Control transfer instructions Register indirect jump (jmpl) Software trap on condition code (tlcc) "Annul bit" to cancel instruction execution in delay slot Multiprocessor instructions Atomic load and store unsigned byte (ldstub) Reads a byte from memory Writes back all one's to the location swap instruction exchanges register and memory

7 SPARC implementations SF9010IU Fujitsu 1.5 micron CMOS gate-array technology 20,000 gates per chip! 3 layers of metalization! Full scan design (97% coverage) 1.2 nanosecond gate delay 156 input/output signals 256-pin pin grid array (PGA) package Cycle time of 60 nanoseconds (16.6 MHz clock) 10 MIPS (with cache) Floating point units! Floating point controller chip! Weitek W1164 multiplier! Weitek W1165 adder Cycles per instruction: 1.47 CYC 601 Cypress Semiconductor Inc. Custom 0.8 micron CMOS technology 30 to 40 nanosecond cycle time MHz clock bit registers (eight windows) Cycles per instruction: 1.54

8 Processor pipeline Fetch stage Address of instruction is sent out Instruction enters pipe at completion of this stage Decode stage Decode and read source operands from register file Send both to Execution Unit and Instruction Fetch Unit Generate next instruction address Decode I n, compute adress of instruction I n+1 Execute stage Perform arithmetic and logical operation Save result in temporary registers Write stage Decide to write result into register file, or Prohibit change to processor state Abort if exeception was raised Fetch Decode Execute Write Fetch Decode Execute Write Fetch Decode Execute Write Fetch Decode Execute Write

9 Main memory Address low I/O Tag Data Cache Address high Compare 32-bit data bus (D) CPU FPC W1164 W1165

10 Processor chip!register file unit bit registers Eight registers are global Seven overlapped frames of 24 registers each Number of windows is implementation dependent Current Window Pointer (CWP) in PSR Execution unit 32-bit carry look-ahead ALU!32-bit barrel shifter Condition code generation logic Load and store alignment logic Pipeline registers for operands and intermediate results Single clock cycle execution ALU bypass for operand forwarding Instruction fetch unit Four program counters " One for each stage " Take exceptions as late as last stage Special registers " Trap Base Register (TBR) " Trap Type Register (TT) " Multiply step register (Y) " Window Invalid Mask (WIM) Control unit Main state machine Instruction pipeline Instruction decoder Processor Status Register (PSR) Exception and trap handling Interface to cache and floating point unit

11 Register file ALU Shift Result

12 Data bus Instruction registers Control From register file Address Generation Address low Address high Program Counters ALU result Special registers To floating point unit

Chapter 13 Reduced Instruction Set Computers

Chapter 13 Reduced Instruction Set Computers Contents Instruction execution characteristics Use of a large register file Compiler-based register optimization Reduced instruction set architecture RISC pipelining