Selection Information FAST/LS TTL FAST AND LS TTL

Transcription

1 election Information FT/L TTL 1 FT ND L TTL

2 GENERL INFORMTION TTL in Perspective ince its introduction, TTL has become the most popular form of digital logic. It has evolved from the original gold-doped saturated 700 logic, to chottky-clamped logic, and finally to the modern advanced families of TTL logic. The popularity of these TTL families stem from their ease of use, low cost, medium-to-high speed operation, and good output drive capability. Motorola offers two modern TTL logic families L and FT. They are pin and functionally compatible and can easily be combined in a system to achieve maximum performance at minimum cost. L (Low Power chottky) is currently the more popular and commands by far the largest share of the total TTL logic market. It is low-cost and provides moderate performance at low power. FT, the state-of-the-art, high-performance TTL family, is growing rapidly and gaining a significant share of the total TTL logic market. FT offers a percent improvement in performance over the older tandard chottky family (7) with a 75 0 percent reduction in power. When compared with the dvanced chottky family (7), FT offers nearly equal performance at a percent savings in power. FT is manufactured on Motorola s MOIC (oxideisolated) process.this process provides FT with inherent speed/power advantages over the older junction-isolated 7 and 7L families, allowing the FT family to be designed and specified with improved noise margins, reduced input currents, and superior line driving capabilities in comparison to these earlier families. dditionally, FT designs incorporate power-down circuitry on all three-state outputs, and buffered outputs on all storage devices. Two further advantages of FT are the load specifications and power supply specifications. FT ac characteristics are specified at a heavier capacitive load than the earlier families (50 pf versus 15 pf) to more accurately reflect actual in-circuit performance. Motorola s dc and ac characteristics for FT are specified over a full 10% supply voltage range a significant improvement over the industry standard specifications for the earlier families (5% for dc, 0% for ac). These design and specification improvements offered by the Motorola FT family provide the user with better system performance, enhanced design flexibility, and more reliable system operation. TTL Family Comparisons General Characteristics for chottky TTL Logic (LL MIMUM RTING) L FT Characteristic ymbol 5Lxxx 7Lxxx 5Fxxx 7Fxxx Unit Operating Voltage Range VCC 5 ± 10% 5 ± 5% 5 ± 10% 5 ± 10% Vdc Operating Temperature Range T 55 to to to to 70 C Input Current IIN IIH IIL Output Drive IOH m tandard Output IOL m IC 20 to to to to 150 m IOH m Buffer Output IOL m IC 0 to to to to 225 m µ peed/power Characteristics for chottky TTL Logic(1) (LL TYPICL RTING) Characteristic ymbol L FT Unit Quiescent upply Current/Gate IG m Power/Gate (Quiescent) PG mw Propagation Delay tp ns peed Power Product pj Clock Frequency (D-F/F) fmax MHz Clock Frequency (Counter) fmax MHz NOTE: 1. pecifications are shown for the following conditions: NOTE: 1. a) V CC = 5.0 Vdc (C); NOTE: 1. b) T = 25 C NOTE: 1. C) C L = 50 pf for FT; 15 pf for L FT ND L TTL DT 1-2

3 Functional election bbreviations = ynchronous = synchronous B = Both ynchronous and synchronous = 2-tate Output 3 = 3-tate Output OC = Open-Collector Output P = Planned (ee FT/L elector Guide, G-60 for latest availability status) = vailable Inverters Hex 0 OC 05 ND Gates Quad 2-Input 0 OC 09 Triple 3-Input 11 OC 15 Dual -Input 21 NND Gates Quad 2-Input 00 OC 01 OC 03 Quad 2-Input, High Voltage OC 26 Triple 3-Input 10 OC 12 Dual -Input 20 OC 22 -Input Input 133 OR Gates Quad 2-Input 32 NOR Gates Quad 2-Input 02 Triple 3-Input 27 Dual 5-Input 260 Exclusive OR Gates Quad 2-Input 6 OC Exclusive NOR Gates Quad 2-Input OC 266 ND-OR-INVERT Gates Dual 2-Wide, 2-Input 3-Input 51 -Wide, Input 5 2-Wide, -Input 55 -Wide, Input 6 chmitt Triggers Dual -Input NND Gate 13 Hex, Inverting 1 Quad 2-Input NND Gate 132 I Flip-Flops Clock Edge No. L FT Dual D w/et & Clear Pos 7 Dual D w/et & Clear Pos 7 Dual JK w/et Neg 113 Dual JK w/clear Neg 73 ame as 73 with Different Pinout Neg 107 Dual JK w/et & Clear Individual J, K, CP, D, CD Inputs Neg 76 ame as 76 with Different Pinout Neg 112 ame as 76 with Different Pinout Neg 112 ame as 112 with Different Pinout Neg 11 Dual JK w/et & Clear Pos 109 Dual JK w/et & Clear Pos 109 FT ND L TTL DT 1-3

4 Multiplexers Quad 2-to-1, Non-Inverting B Quad 2-to-1, Inverting B Dual -to-1, Non-Inverting Dual -to-1, Inverting to Quad 2-to-1 with Output Register 39 Positive edge triggered, 39 Q/O Outputs 399 Positive edge triggered, Q Output Only 399 Encoders 10-to--Line BCD 17 -to-3-line Priority Encoder Decoders/Demultiplexers Dual 1-of OC of of- with Latch of Latches No. of Bits Transparent, Non-Inverting Octal, Non-Inverting Transparent, Inverting Transparent, Q and Q Outputs Quad et-reset Latch 279 ddressable 259 Dual -Bit ddressable 256 Register Files x OC hift Registers No. of Bits Mode* Output R L Hold Reset No. L FT erial In-Parallel Out 16 Parallel In-erial Out Parallel In-Parallel Out 95B Parallel In-Parallel Out, Bidirectional ign Extended Bidirectional * R = hift Right * L = hift Left FT ND L TTL DT 1-

5 synchronous Counters Negative Edge-Triggered Load et Reset No. L FT Decade (2/5) Dual Decade (2/5) Dual Decade Modulo 12 (2/6) -Bit Binary (2/) Dual -Bit Binary * The 716 and 71 are positive edge-triggered. 90* 196* 290* 390* 90* 92* 93* 197* 293* 393* Display Decoders/Drivers with Open-Collector Outputs No. L FT 1-of-10 BCD-to-7 egment 15* 7* * 27* 2* 29* * The and 2 have internal pull up resistors to V CC on their outputs. Cascadable ynchronous Counters Positive Edge-Triggered Decade Decade, Up/Down -Bit Binary -Bit Binary, Up/Down Bit Binary, Up/Down Output Load Reset No. L FT B B B * * * The 192 and 193 do not provide a clock enable for synchronous cascading. MI Flip-Flops/Registers No. of Bits Output et or Reset Clock Enable No. L FT D-Type, Non-Inverting 6 6 Quad 2-Port D-Type, Inverting D-Type, Q and Q Outputs FT ND L TTL DT 1-5

6 rithmetic Operators No. L FT -Bit dder Bit LU Look-head Carry Generator 12 -Bit Barrel hifter 350 Magnitude Comparators Output P = Q P>Q P<Q No. L FT -Bit 5 -Bit Bit with Output Enable 6 Parity Generators/Checkers No. L FT 9-Bit Odd Even Parity Generator Checker VCOs and Multivibrators 20 No. L FT Retriggerable Monostable 122 Multivibrator Dual Precision Non-Retriggerable Monostable Multivibrator 221 Buffers/Line Drivers Quad 2-Input NOR 2 OC 33 Quad 2-Input NND 37 OC 3 Dual -Input NND 0 Quad, Non-Inverting Hex, Non-Inverting Hex, Inverting Octal, Non-Inverting Bus Pinout Octal, Inverting 3 20 Bus Pinout Bit Transceivers Quad, Non-Inverting 3 23 Quad, FutureBus Quad, Inverting 3 22 Octal, Non-Inverting OC Octal, Inverting OC 62 Octal, Non-Inverting 3 66 Register Latch 3 53 Octal, Inverting Register 3 5 Octal w/ Parity Gen/Checker B Clock Drivers No. L FT Quad Matched 03 Propagation Delays Clock Driver 103 FT ND L TTL DT 1-6