74ALVC132 Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and. and Outputs. General Description.

Transcription

1 74ALC132 Low oltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6 Tolerant Inputs and General Description The ALC132 contains four 2-input NAND gates with Schmitt Trigger Inputs. The pin configuration and function are the same as the ALC00 except the inputs have hysteresis between the positive-going and negative-going input thresholds. This hysteresis is useful for transforming slowly switching input signals into sharply defined, jitterfree output signals. This product should be used where noise margin greater than that of conventional gates is required. The ALC132 is designed for low voltage (1.65 to 3.6) CC applications with I/O compatibility up to 3.6. This product is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power dissipation. Ordering Code: Features 1.65 to 3.6 CC supply operation 3.6 tolerant inputs and outputs t PD 3.8 ns max for 3.0 to 3.6 CC December 2001 Revised February ns max for 2.3 to 2.7 CC 8.2 ns max for 1.65 to 1.95 CC Power-off high impedance inputs and outputs Uses patented Quiet Series noise/emi reduction circuitry Latchup conforms to JEDEC JED78 ESD performance: Human body model! 2000 Machine model! 250 Order Number Package Number Package Description 74ALC132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74ALC132MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Logic Diagram Pin Descriptions Pin Name A n, B n O n Description Inputs Connection Diagram 74ALC132 Low oltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6 Tolerant Inputs and Quiet Series is a trademark of Fairchild Semiconductor Corporation Fairchild Semiconductor Corporation DS

2 74ALC132 Absolute Maximum Ratings(Note 1) Supply oltage ( CC ) 0.5 to 4.6 DC Input oltage ( I ) 0.5 to 4.6 Output oltage ( O ) (Note 2) 0.5 to CC 0.5 DC Input Diode Current (I IK ) I 0 50 ma DC Output Diode Current (I OK ) O 0 50 ma DC Output Source/Sink Current (I OH /I OL ) r50 ma DC CC or GND Current per Supply Pin (I CC or GND) r100 ma Storage Temperature Range (T STG ) 65qC to 150qC DC Electrical Characteristics Recommended Operating Conditions (Note 3) Power Supply Operating 1.65 to 3.6 Input oltage ( I ) 0 to CC Output oltage ( O ) 0 to CC Free Air Operating Temperature (T A ) 40qC to 85qC Minimum Input Edge Rate ('t/') IN 0.8 to 2.0, CC ns/ Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. Note 2: I O Absolute Maximum Rating must be observed. Note 3: Floating or unused inputs must be held HIGH or LOW. Symbol Parameter Conditions CC Min Max Units () t Positive Threshold t Negative Threshold H Input Hysteresis OH HIGH Level Output oltage I OH 100 PA CC I OH 4 ma I OH 6 ma I OH 12 ma I OH 24 ma OL LOW Level Output oltage I OL 100 PA I OL 4 ma I OL 6 ma I OL 12mA I OL 24 ma I I Input Leakage Current 0 d I d r5.0 PA I OZ 3-STATE Output Leakage 0 d O d r10 PA I CC Quiescent Supply Current I CC or GND, I O PA 'I CC Increase in I CC per Input IH CC PA 2

3 AC Electrical Characteristics T A 40qC to 85qC, R L 500: C L 50 pf C L 30 pf Symbol Parameter Units CC 3.3 r 0.3 CC 2.7 CC 2.5 r 0.2 CC 1.8 r 0.15 Min Max Min Max Min Max Min Max t PHL, t PLH Propagation Delay Bus to Bus ns 74ALC132 Capacitance T A 25qC Symbol Parameter Conditions CC Typical Units C IN Input Capacitance I 0 or CC pf C OUT Output Capacitance I 0 or CC pf C PD Power Dissipation Capacitance Enabled f 10 MHz, C L 50 pf pf AC Loading and Waveforms TABLE 1. alues for Figure 1 TEST SWITCH t PLH, t PHL Open FIGURE 1. AC Test Circuit TABLE 2. ariable Matrix (Input Characteristics: f 1MHz; t r t f 2ns; Z 0 50:) Symbol CC 3.3 r r r 0.15 mi CC /2 CC /2 mo CC /2 CC /2 FIGURE 2. Waveform for Inverting and Non-inverting Functions 3

4 74ALC132 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 4

5 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 74ALC132 Low oltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6 Tolerant Inputs and 5