Chapter 4: Combinational Logic

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1 Chapter 4: Combinational Logic Combinational Circuit Design Analysis Procedure (Find out nature of O/P) Boolean Expression Approach Truth Table Approach Design Procedure Example : BCD to Excess-3 code convertor Example 2: even egment Decoder tandard and Canonical Terms BCD to Excess-3 Code Convertor even egment Decoder Binary Adder Binary Adder ( 4-bits) with carry propagation Cascading Multiple Adders Reducing Carry Propagation Delay (Parallel Adder, Carry Look Ahead Adder) Binary Coded Decimal (BCD) Adder Eastern Mediterranean University / 65

2 BCD Adder (Using two binary Adder) Err x 3 x 2 x x y 3 y 2 y y A 3 A 2 A A B 3 B 2 B B C y Binary Adder C i 3 2 BCD Operands: X= (x3 x2 x x) = (y3 y2 y y) um = 3,2,, X + x 3 x 2 x x y 3 y 2 y y um Cy 3 2 Required BCD Output Value 9 + = 9 = = = = 5 = = 8 = 24 A 3 A 2 A A B 3 B 2 B B C y Binary Adder C i 3 2 C y 3 2 Question : Design a magnitude comparator to compare two variables A and B.Assume that the input numbers A and B are of two bits each. Generate three output as A>B, A=B, A<B Eastern Mediterranean University / 65

3 Magnitude Comparator Compare 2-bit number to 2-bit number A A B B Magnitude Comparator A<B A=B A>B Generate Truth Table for all possible combination of AA and BB. Get K map for all three output. Design hardware. Eastern Mediterranean University 2 / 65

4 Magnitude Comparator Compare 2-bit number to 2-bit number A A B B A B A>B A=B A<B A A B B Magnitude Comparator A<B A=B A>B Eastern Mediterranean University 3 / 65

5 Decoders. Concept and pecification 2. Application 3. Designing 2x4 Decoders 4. Decoders with Enable input 5. Designing 3x8 Decoders 6. Expanding (3x8 using 2x4 decoders) 7. Active High / Active Low output 8. Implementation using Decoders Eastern Mediterranean University 4 / 65

6 Concept and Application Binary Decoder. It is capable to identify combination of input bits and generate unique output, say for, For two bit input it will generate 4 bit out put 3. pecification is nxm, means it is n input bits and m output bits. 4. Example specification are 2x4, 3x8 etc. y 3 y 2 y y Eastern Mediterranean University 5 / 65

7 Decoders (Concepts and Applications) Extract Information from the code Binary Decoder (2x4) Example: 2-bit Binary Number Only one lamp will turn on x x Binary Decoder Eastern Mediterranean University 6 / 65

8 Binary Decoder Decoders (2x4 Truth Table and hardware ) 2-to-4 Line Decoder y 3 y 2 y y 3 I I 2 I I I I I I Eastern Mediterranean University 7 / 65

9 Decoders (With Enable Input) Binary Decoder Binary Decoder y 3 y y y E x x E E Eastern Mediterranean University 8 / 65

10 Decoders Binary Decoder 3-to-8 Line Decoder (Give Hardware Diagram) 7 I 2 I I 6 I I 2 I I I I I I I I 2 I I 2 I I 2 I 2 I I I 2 I 2 I I Eastern Mediterranean University 9 / 65

11 MI Circuit Design cale of Integration (I,MI,LI,VLI,oC.) Decoders: (Cascading Decoders, olving Boolean Expressions using Decoders) Encoders (Concept, Design, Cascading, olving Expressions using Encoders) Octal Encoder, Priority Encoder, Interfacing Application) Multiplexers (Concept, Design, Cascading, olving Expression usinf MUX) Eastern Mediterranean University / 65

12 cale of Integration I: mall-scale Integration : Gates< Ml: Medium-scale Integration : <Gates< Ll: Large-scale Integration : Gates> VLI: Very Large-scale Integration : Gates> oc: ystems on Chip :Million Gate, oftware & Hardware. Eastern Mediterranean University / 65

13 MI (Medium cale Integration) Example MI (Medium cale Integration) Decoders Encoders Multiplexers De-multiplexers PLA PAL etc. Eastern Mediterranean University 2 / 65

14 Decoders (3x8 decoders using 2x4 decoders) Binary Decoder Binary Decoder Expansion E E Eastern Mediterranean University 3 / 65

15 Decoders Binary Decoder Binary Decoder Active-High / Active-Low output (Give H/W) Eastern Mediterranean University 4 / 65

16 Implementation Using Decoders I2 I I I2 I I 2 I I I I I I et of minterms available at o/p of decoder 4 I2 I I 5 I2 I I 6 I2 I I 7 I I I Each output is a minterm All minterms are produced um the required minterms 2 x y z Binary Decoder Eastern Mediterranean University 5 / 65

17 Implementation Using Decoders What is the meaning of implementation using MI Implement OP f (a, b, c) = m2, m5, m6, m7 Binary Decoder x y z I I I I I I 2 5 I I I 2 4 I I I 2 3 I I I 2 2 I I I I2 I I I I I 2 Eastern Mediterranean University 6 / 65

18 Use Decoder IC to Implementation Full Adder (x, y, z) = (, 2, 4, 7) I I I 2 I I I 2 2 x y z C C(x, y, z) = (3, 5, 6, 7) 3 I I I 2 5 I I I 2 4 I I I 2 6 I I I 2 7 I I I x y z Eastern Mediterranean University 2 7 I I I 2 Binary Decoder C 7 / 6

19 Implementation Active Low Active High How do we go for Active Low and Active High output.? As we know OR gate = Negative NAND Gate Binary Decoder Put ve NAND gate on behalf of OR gate x y z Eastern Mediterranean University 8 / 65 C

20 Implementation Active Low Active High Binary Decoder Binary Decoder x y z x y z C C Eastern Mediterranean University 9 / 65

21 Encoders Example MI (Medium cale Integration) Decoders Encoders Multiplexers Demultiplexers PLA PAL etc. Eastern Mediterranean University 2 / 65

22 Encoders Put Information into code Binary Encoder Example: 4-to-2 Binary Encoder Only one switch should be activated at a time x x 2 x 3 Binary Encoder y y x 3 x 2 x y y Eastern Mediterranean University 2 / 65

23 Encoders Binary Encoder Design Octal-to-Binary Encoder (8-to-3) I 7 I 6 I 5 I 4 I 3 I 7 I 6 I 5 I 4 I 3 Eastern Mediterranean University 22 / 65

24 Binary Encoder Design Equation for Octal to Binary Encoder I 7 I 6 I 5 I 4 I 3 I 7 I 6 I 5 I 4 I 3 2 I I I I I I I I I I I I 4 2 I 7 I 6 I 5 I 4 I 3 Eastern Mediterranean University 23 / 65

Digital ystems. Designing Priority Encoder Multiplexers. Concept and Block Diagram and pecification 2. Designing 2x, 4x MUX 3. Designing Quad 2x MUX 4. MUX with Enable input 5.

25 Digital ystems. Designing Priority Encoder Multiplexers. Concept and Block Diagram and pecification 2. Designing 2x, 4x MUX 3. Designing Quad 2x MUX 4. MUX with Enable input 5. Implement Boolean function using MUX f(x,y)=σ m(,,3) using 4x MUX f(x,y,z)=σ m(,2,6,7) using 8x MUX f(x,y,z)=σ m(,2,6,7) using 4x MUX f(a,b,c,d)=σm(,3,4,,2,3,4,5) using 8x MUX 6. Realizing larger size MUX using small size MUX 24 / 65

26 Priority Encoder Design a Priority Encoders for 4 bit input I3 I2 I I V Four I/P I3,I2,I,I I3 Highest Priority (Assumed) I Lowest Priority (Assumed) I3 I2 I I I 3 V 25 / 65

27 Priority Encoders of 4 bit input I3 I2 I I V I 3 V I I I I I I I I I I 3 V Eastern Mediterranean University 26 / 65

28 MULTIPLEXER Circuit (MUX) Eastern Mediterranean University 27 / 65

29 MULTIPLEXER Circuit (MUX) Concepts and Block Diagram:. MUX is used to transfer large number of data over small unit. 2. It is a combinational circuit that select one input, out of many and directs into single output, hence called as Many into One. 3. election of one input line is controlled by set of selection input, also called as control input. 4. For N input lines we need log 2N selection lines. Eastern Mediterranean University 28 / 65

30 Multiplexers 4x Concepts and Block Diagram: Block Diagram Truth Table MUX I 3 I 3 MUX pecification pecification of MUX is Nx, that means Examples are 4x,8x.etc N: Number of Input Bits : Out put bit Eastern Mediterranean University 29 / 65

31 Design 2x Multiplexers Block Diagram MUX Truth Table Give Circuit Diagram Eastern Mediterranean University 3 / 65

32 Design 4x Multiplexers Truth Table Give Circuit Diagram I 3 Block Diagram I 3 MUX I 3

33 Design Quad 2-to- MUX What is Quad 2-to- MUX..? We have two input numbers A and B, of 4 bits each. If we want to fetch all 4 bits of A i.e. a3,a2,a,a at one time and all 4 bits of B i.e. b3,b2,b,b at another time, then we need quad 2x MUX It is done via selection input. Define value of = means all bits of A i.e. a3,a2,a,a will pass to the output = All bits of B i.e. b3,b2,b,b will pass to the output. Find out the number of output bits.? Block Diagram Input bits are four Output bits are four a3,a2,a,a b3,b2,b,b 3,2,, A 3 A 2 A A B 3 B 2 B B MUX

34 Design Quad 2-to- MUX Variable Planning (i.e. Input Output) Give Truth Table a 3 b 3 3, 2,, a 2 a b 2 b A 3 A 2 A A B 3 B 2 B B MUX a3 a2 a a b3 b2 b b a b Question : Can we design above MUX using 4 number of 2x MUX..?

35 Design Quad 2-to- MUX using 4 no of 2x MUX a 3 a 2 a a b 3 b 2 b b MUX3 MUX2 MUX MUX A 3 A 2 A A B 3 B 2 B B MUX MUX Give complete Circuit diagram of above design..

36 Design Quad 2-to- MUX a 3 b 3 MUX3 A 3 A 2 A a 2 b 2 MUX2 A B 3 a a b b MUX MUX A 3 A 2 A A B 3 B 2 B B MUX E B 2 B B E Give complete Circuit diagram of above circuit diagram..

37 Design Quad 2-to- MUX (Identify 2x MUX) a 3 b 3 MUX3 A 3 I,3 a 2 b 2 MUX2 A 2 A A I,2 I, I, a b MUX B 3 B 2 B I,3 I,2 I, a b MUX A 3 A 2 A A B 3 B 2 B B MUX E B E I,

38 Multiplexers with Enable input If E is defined at logic HIGH then E= will generate all output bits. If E is defined at logic LOW then E= will generate all output bits. Circuit Diagram Block Diagram A 3 A 2 A A B 3 B 2 B B Extra Buffers A 3 A 2 A A B 3 B 2 B B MUX E E 37 / 65

39 Multiplexers with Enable input If E is defined at logic HIGH then E= will generate all output bits. If E is defined at logic LOW then E= will generate all output bits. A 3 A 2 A A B 3 B 2 B B A 3 A 2 A A B 3 B 2 B B MUX E E If = and E = what is the output? =A or =B If = and E = what is the output..? =A or =B If E = what is the output..? 38 / 65

40 Implementation Using Multiplexers Question : Design Combinational circuit using 4x MUX. Boolean exp of 2 variable and MUX of 2 pow 2 = 4 input, so the design in simple. Realize following function using MUX F(x, y) = (,, 3) using 4x MUX Mean term means x y Mean term means x y Mean term 2 means x y Mean term 3 means x y If we connect with y literal with x literal I 3 This would lead to I = x y I = x y I2 = x y I3 = x y MUX I 3 Eastern Mediterranean University 39 / 65

41 Implementation Using Multiplexers Question : Design Combinational circuit using 4x MUX. Boolean exp of 2 variable and MUX of 2 pow 2 = 4 input, so the design in simple. x y F F(x, y) = (,, 3) using 4x MUX Block Diagram MUX I 3 x y F Eastern Mediterranean University 4 / 65

42 Implementation Using Multiplexers Question 2: Implement following Boolean expression using 8x MUX F(x, y, z) = (, 2, 6, 7) using 8x MUX Expression of three variable and number of selection input of 8x MUX is calculated as log 2 8 = 3 input, so the design is simple. x y z F I 3 I MUX 4 I 5 I 6 I 7 2 x y z F Eastern Mediterranean University 4 / 65

43 Implementation Using Multiplexers Question 3: Implement following Boolean function using MUX F(x, y, z) = (, 2, 6, 7), do not use 8x MUX but 4x MUX is available. Function given is of three variable, and 4x MUX is available. Given 4x Mux will have log 2 4 = 2 selection input. Three input variable and two selection input are not simple, hence the design steps will be different MUX I 3 F x y Eastern Mediterranean University 42 / 65

44 Implementation Using Multiplexers Question 3: Implement following Boolean function using MUX F(x, y, z) = (, 2, 6, 7), do not use 8x MUX but 4x MUX is available. x y z F F = z F = z F = F = z z MUX I 3 x y F Eastern Mediterranean University 43 / 65

45 Implementation Using Multiplexers Question 4: Implement following function using 8x MUX F(A, B, C, D) = (, 3, 4,, 2, 3, 4, 5) Given function is of 4 variable, selection input of available 8x MUX is calculated as log 2 8 =3, hence design is not simple. A B C D F F = D F = D F = D F = F = F = D F = F = I 3 I MUX 4 I 5 I 6 I 7 2 A B C D D D D F Eastern Mediterranean University 44 / 65

46 Multiplexer Expansion (Design 8x using dual 4x and single 2x) Block Diagram Truth Table I 3 I 4 I 5 I 6 I 7 8x MUX 2 I I I2 I3 I4 I5 I6 I7 2 Eastern Mediterranean University 45 / 65

47 Multiplexer Expansion (Design 8x using dual 4x and single 2x) I 3 I 4 I 5 I 6 I 7 I MUX I 3 MUX I 3 MUX 2 I I I2 I3 I4 I5 I6 I / 65

48 DeMultiplexers I DeMUX I I Eastern Mediterranean University 47 / 65

49 Multiplexer / DeMultiplexer Pairs MUX DeMUX I 7 I 6 I 5 I 4 I 3 I ynchronize x 2 x x y 2 y y Eastern Mediterranean University 48 / 65

50 Compare DeMultiplexers / Decoders Binary Decoder I DeMUX E I E x x Eastern Mediterranean University 49 / 65

51 Three-tate Gates (Tristate Inventor and Buffer) Tri-tate Buffer A C Tri-tate Inverter A C A C x Hi-Z Eastern Mediterranean University 5 / 65

52 Three-tate Gates A B C C D Hi-Z B A? D A Not Allowed C B = A if C = B if C = Eastern Mediterranean University 5 / 65

53 Three-tate Gates Binary Decoder I 3 E E Eastern Mediterranean University 52 / 65

54 Design Encoder / Decoder Pairs Question : Design a switching circuit to interface eight ON/OFF switch (,,,2 7)to operate 8 LED (,,2 7). Assuming that if switch will operate LED, and switch 7 will operate LED7. Eastern Mediterranean University 53 / 65

55 Encoder / Decoder Pairs Binary Encoder Binary Decoder I 7 I 6 I 5 I 4 I Eastern Mediterranean University 54 / 65

1. Mark the correct statement(s)

1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another