3.3V CMOS OCTAL BIDIRECTIONAL TRANSCEIVER
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1 . CMOS OCTAL IDIRECTIONAL TRANSCEIVER. CMOS OCTAL IDIRECTIONAL TRANSCEIVER IDT7FCT/A FEATURES: 0. MICRON CMOS Technology ESD > 00 per MIL-STD-, Method 0; > 0 using machine model (C = 00pF, R = 0) VCC =. ±0., Normal Range VCC =.7V to.v, Extended Range CMOS power levels (0.μW typ. static) Rail-to-Rail output swing for increased noise margin Available in QSOP and TSSOP packages DESCRIPTION: The FCT/A octal transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power transceivers are ideal for asynchronous communication between two buses (A and ). The direction control pin (DIR) controls the direction of data flow. The output enable pin (OE) overrides the direction control and disables both ports. All inputs are designed with hysteresis for improved noise margin. The FCT/A has series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors. FUNCTIONAL LOCK DIAGRAM DIR A A A A A A A7 A OE 7 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. MAY 0 0 Integrated Device Technology, Inc. DSC-0/
2 . CMOS OCTAL IDIRECTIONAL TRANSCEIVER PIN CONFIGURATION ASOLUTE MAXIMUM RATINGS () Symbol Description Max Unit VTERM () Terminal Voltage with Respect to 0. to +. V DIR A 0 9 Vcc OE VTERM () Terminal Voltage with Respect to 0. to +7 V VTERM () Terminal Voltage with Respect to 0. to VCC+0. V TSTG Storage Temperature to +0 C A A A A A A7 A IOUT DC Output Current 0 to +0 ma. Stresses greater than those listed under ASOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.. VCC terminals.. Input terminals.. Outputs and I/O terminals. QSOP/ TSSOP TOP VIEW CAPACITANCE (TA = + C, F =.0MHz) Symbol Parameter () Conditions Typ. Max. Unit CIN Input Capacitance VIN =. pf COUT Output Capacitance VOUT = pf NOTE:. This parameter is measured at characterization but not tested. PIN DESCRIPTION Pin Names Description OE State Output Enable Inputs (Active LOW) DIR Direction Control Output A x Side A Inputs or -State Outputs x Side Inputs or -State Outputs FUNCTION TALE () Inputs OE DIR Outputs L L us Data to us A L H us A Data to us H X High Z State NOTE:. H = HIGH Voltage Level X = Don t Care L = LOW Voltage Level Z = High Impedance
3 . CMOS OCTAL IDIRECTIONAL TRANSCEIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -0 C to + C, VCC =.7V to.v Symbol Parameter Test Conditions () Min. Typ. () Max. Unit VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level. V Input HIGH Level (I/O pins) Vcc+0. VIL Input LOW Level Guaranteed Logic LOW Level V (Input and I/O pins) IIH Input HIGH Current (Input pins) VCC = Max. VI =.V ± µa Input HIGH Current (I/O pins) VI = VCC ± IIL Input LOW Current (Input pins) VI = ± Input LOW Current (I/O pins) VI = ± IOZH High Impedance Output Current VCC = Max. VO = VCC ± µa IOZL (-State Output pins) VO = ± VIK Clamp Diode Voltage VCC = Min., IIN = ma 0.7. V IODH Output HIGH Current VCC =., VIN = VIH or VIL, VO = () 0 0 ma IODL Output LOW Current VCC =., VIN = VIH or VIL, VO = () ma VOH Output HIGH Voltage VCC = Min. IOH = 0.mA VCC 0. V VIN = VIH or VIL IOH = ma. VCC = IOH = ma. () VIN = VIH or VIL VOL Output LOW Voltage VCC = Min. IOL = 0.mA 0. V VIN = VIH or VIL IOL = ma IOL = ma VCC = IOL = ma VIN = VIH or VIL IOS Short Circuit Current () VCC = Max., VO = () 0 0 ma VH Input Hysteresis 0 mv ICCL Quiescent Power Supply Current VCC = Max., or VCC 0. 0 µa ICCH ICCZ. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.. Typical values are at VCC =., + C ambient and maximum loading.. Not more than one output should be tested at one time. Duration of the test should not exceed one second.. This parameter is guaranteed but not tested.. VOH = VCC - 0.V at rated current.
4 . CMOS OCTAL IDIRECTIONAL TRANSCEIVER POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions () Min. Typ. () Max. Unit ICC Quiescent Power Supply Current VCC = Max. VIN = VCC - 0.V 0 μa ICCD Dynamic Power Supply VCC = Max. VIN = VCC 0 μa/ Current () Outputs Open MHz OE = DIR = One Input Toggling 0% Duty Cycle IC Total Power Supply Current () VCC = Max. VIN = VCC ma Outputs Open fi = 0MHz 0% Duty Cycle VIN = VCC - 0.V OE = DIR = One it Toggling VCC = Max. VIN = VCC..7 () Outputs Open fi =.MHz 0% Duty Cycle VIN = VCC - 0.V.. () OE = DIR = Eight its Toggling. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.. Typical values are at VCC =., + C ambient.. Per TTL driven input. All other inputs at VCC or.. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested.. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ΔICC DHNT + ICCD (fcpncp/ + fini) ICC = Quiescent Current (ICC, ICCH, and ICCZ) ΔICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fcp = Clock Frequency for register devices (zero for non-register devices) NCP = Number of clock inputs at fcp fi = Input Frequency Ni = Number of Inputs at fi SWITCHING CHARACTERISTICS OVER OPERATING RANGE () 7FCT 7FCTA Symbol Parameter Condition () Min. () Max. Min. () Max. Unit tplh Propagation Delay CL = 0pF. 7.. ns tphl A to, to A RL = 00Ω tpzh Output Enable Time ns tpzl OE to A or tphz Output Disable Time. 7.. ns tplz OE to A or tpzh Output Enable Time ns tpzl DIR to A or () tphz Output Disable Time. 7.. ns tplz DIR to A or (). Propagation Delays and Enable/Disable times are with VCC =. ±0., Normal Range. For VCC =.7V to.v, Extended Range, all Propagation Delays and Enable/ Disable times should be degraded by 0%.. See test circuit and waveforms.. Minimum limits are guaranteed but not tested on Propagation Delays.. This parameter is guaranteed but not tested.
5 . CMOS OCTAL IDIRECTIONAL TRANSCEIVER TEST CIRCUITS AND WAVEFORMS Pulse Generator VIN RT V CC D.U.T. VOUT 0pF CL 00Ω 00Ω v Open SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch V Open Test Circuits for All Outputs DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENALE ETC. tsu tsu trem th th LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tw Pulse Width Set-Up, Hold, and Release Times SAME PHASE INPUT TRANSITION OUTPUT OPPOSITE PHASE INPUT TRANSITION tplh tplh Propagation Delay tphl tphl VOH VOL CONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH ENALE tpzl SWITCH V tpzh SWITCH tphz DISALE tplz Enable and Disable Times VOL VOH. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.. Pulse Generator for All Pulses: Rate.0MHz; ZO 0Ω; tf.ns; tr.ns.. If Vcc is below, input voltage swings should be adjusted not to exceed Vcc.
6 . CMOS OCTAL IDIRECTIONAL TRANSCEIVER ORDERING INFORMATION XX Temp. Range FCT X Family XXXX Device Type XX Package X lank Tube Tape and Reel QG PGG Quarter-size Small Outline Package - Green Thin Shrink Small Outline Package - Green A Octal idirectional Transceiver. Volt 7-0 C to + C Datasheet Document History 0/0/009 Pg. Updated the ordering information by removing the "IDT" notation and non RoHS part. 0/0/0 Pg. Updated the ordering information by adding Tape and Reel. CORPORATE HEADQUARTERS for SALES: for Tech Support: 0 Silver Creek Valley Road or logichelp@idt.com San Jose, CA 9 fax:
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CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,024 X 9, 2,048 X 9, 4,096 x 9 and 8,192 x 9
Integrated Device Technology, Inc. CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,24 X 9, 2,48 X 9, 4,96 x 9 and 8,192 x 9 IDT72421 IDT7221 IDT72211 IDT72221 IDT72231 IDT72241 IDT72251 FEATURES: 64 x 9-bit
PAL22V10 Family, AmPAL22V10/A
FINAL COM L: -7//5 PAL22V Family, AmPAL22V/A 24-Pin TTL Versatile PAL Device Advanced Micro Devices DISTINCTIVE CHARACTERISTICS As fast as 7.5-ns propagation delay and 9 MHz fmax (external) Macrocells
SN54BCT760, SN74BCT760 OCTAL BUFFERS/DRIVERS WITH OPEN-COLLECTOR OUTPUTS
SNBCT0, SNBCT0 SCBS0B JULY REVISED NOVEMBER Open-Collector Version of BCT Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers ESD Protection Exceeds 000 V Per MIL-STD-C Method 0 Packages
MC74F620 MC74F623 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS (INVERTING AND NONINVERTING)
OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS (INVERTING AND NONINVERTING) The MC6 is an octal bus traceiver featuring inverting 3-state buscompatible outputs in both send and receive directio. The BN outputs
2.5 V/3.3 V, 1-Bit, 2-Port Level Translator Bus Switch in SOT-66 ADG3241
2. V/3.3 V, -Bit, 2-Port Level Translator Bus Switch in SOT-66 ADG324 FEATURES FUNCTIONAL BLOCK DIAGRAM 22 ps propagation delay through the switch A B 4. Ω switch connection between ports Data rate. Gbps
3.3V CMOS Static RAM for Automotive Applications 4 Meg (256K x 16-Bit)
.V CMOS Static RAM for Automotive Applicatio Meg (25K x -Bit) IDTVYS IDTVYL Features 25K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. Equal access and cycle
3.3 VOLT CMOS SyncBiFIFO TM 16,384 x 36 x 2 32,768 x 36 x 2 65,536 x 36 x 2. Mail 1. Register. RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36
FEATURES Memory storage capacity: IDT72V3682 16,384 x 36 x 2 IDT72V3692 32,768 x 36 x 2 IDT72V36102 65,536 x 36 x 2 Supports clock frequencies up to 100MHz Fast access times of 6.5ns Free-running and may
DATASHEET HCS109MS. Features. Pinouts. Description. Ordering Information. Radiation Hardened Dual JK Flip Flop. FN2466 Rev 2.
DATASHEET HCS109MS Radiation Hardened Dual JK Flip Flop FN2466 Rev 2.00 Features 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm 2 /mg Single Event
Rev. No. History Issue Date Remark
Preliminary 512K X 8 OTP CMOS EPROM Document Title 512K X 8 OTP CMOS EPROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 17, 1998 Preliminary 1.0 Change CE from VIL to VIH
SN54F38, SN74F38 QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS
SNF, SN7F SDFS0A MARCH 7 REVISED OCTOBER Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 00-mil DIPs description These devices contain four
2.5 V/3.3 V, 2-Bit Common Control Level Translator Bus Switch ADG3242
2.5 V/3.3 V, 2-Bit Common Control Level Translator Bus Switch ADG3242 FEATURES 225 ps propagation delay through the switch 4.5 Ω switch connection between ports Data rate 1.5 Gbps 2.5 V/3.3 V supply operation
CMOS SyncFIFO TM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 INPUT REGISTER WRITE CONTROL LOGIC
CMOS SyncFIFO TM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 IDT72205LB, IDT72215LB, IDT72225LB, IDT72235LB, IDT72245LB LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE
AT29C K (32K x 8) 5-volt Only CMOS Flash Memory. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns 5-Volt-Only Reprogramming Page Program Operation Single Cycle Reprogram (Erase and Program) Internal Address and Data Latches for 64-Bytes Internal Program Control
ICS548A-03 LOW SKEW CLOCK INVERTER AND DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS548A-03 Description The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two.
T1/E1 CLOCK MULTIPLIER. Features
DATASHEET ICS548-05 Description The ICS548-05 is a low-cost, low-jitter, high-performace clock synthesizer designed to produce x16 and x24 clocks from T1 and E1 frequencies. Using IDT s patented analog/digital
MC1488, SN55188, SN75188 QUADRUPLE LINE DRIVERS
Meet or Exceed the Requirements of ANSI EIA/ TIA--E and ITU Recommendation V. Designed to Be Interchangeable With Motorola MC1 Current-Limited Output: ma Typical Power-Off Output Impedance: Ω Minimum Slew
NOT RECOMMENDED FOR NEW DESIGNS SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
NOT RECOMMENDED FOR NEW DESIGNS Micrel, Inc. SINGLE SUPPLY QUAD PECL/TTL-TO-PECL FEATURES Quad PECL version of popular ECLinPS E Low skew Guaranteed skew spec TTL enable input Selectable TTL or PECL clock
DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR
DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR FEATURES DESCRIPTION 300ps typical propagation delay
ZLED7002. Toggle (Side-Step) Dual-Channel LED Driver. Datasheet. Features. Brief Description. Benefits. Available Support. Physical Characteristics
Toggle (Side-Step) Dual-Channel LED Driver ZLED7002 Datasheet Brief Description The ZLED7002 toggle (side-step) dual-channel LED driver is one of our ZLED family of LED control ICs. It operates in the
74AC11139 DUAL 2-LINE DECODER/DEMULTIPLEXER
Designed Specifically for High-Speed Memory Decoders and Data Tramission Systems Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception Center-Pin V CC and GND Configuratio Minimize
IDTVP386. General Description. Features. Block Diagram DATASHEET ADVANCE INFORMATION 8/28-BIT LVDS RECEIVER FOR VIDEO
DATASHEET ADVANCE INFORMATION IDTVP386 General Description The VP386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.8 Gbps
LP621024E-I Series 128K X 8 BIT CMOS SRAM. Document Title 128K X 8 BIT CMOS SRAM. Revision History. AMIC Technology, Corp.
128K X 8 BIT CMOS SRAM Document Title 128K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue January 14, 2008 Preliminary 1.0 Final version release September 21, 2010
128Kx8 CMOS MONOLITHIC EEPROM SMD
128Kx8 CMOS MONOLITHIC EEPROM SMD 5962-96796 WME128K8-XXX FEATURES Read Access Times of 125, 140, 150, 200, 250, 300ns JEDEC Approved Packages 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300) 32 lead,
AT28C16. 16K (2K x 8) CMOS E 2 PROM. Features. Description. Pin Configurations
Features Fast Read Access Time - 150 ns Fast Byte Write - 200 µs or 1 ms Self-Timed Byte Write Cycle Internal Address and Data Latches Internal Control Timer Automatic Clear Before Write Direct Microprocessor
1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
1.8V to 3.3V LVCMOS High Performance Clock Buffer Family 5PB11xx DATASHEET Description The 5PB11xx is a high-performance LVCMOS Clock Buffer Family. It has best-in-class Additive Phase Jitter of 50fsec
1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
.8V PLL DIFFERENTIAL :0 SDRAM CLOCK DRIVER.8V PHASE LOCKED LOOP DIFFERENTIAL :0 SDRAM CLOCK DRIVER IDTCSPU877 FEATURES: to 0 differential clock distribution Optimized for clock distribution in DDR2 (Double
DATASHEET HCTS139MS. Pinouts. Features. Description. Ordering Information. Radiation Hardened Dual 2-to-4 Line Decoder/Demultiplexer
DATASHEET HCTS139MS Radiation Hardened Dual 2-to-4 Line Decoder/Demultiplexer Rev X.00 Features Pinouts 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm
HIGH-SPEED 4K x 8 FourPort TM STATIC RAM
Features High-speed access Commercial: // (max.) Industrial: (max.) ow-power operation IDT754 Active: 75mW (typ.) tandby: 7.5mW (typ.) IDT754 Active: 75mW (typ.) tandby: mw (typ.) True FourPort memory
Low Voltage 1.65 V to 3.6 V, Bidirectional Logic Level Translation, Bypass Switch ADG3233
Data Sheet Low Voltage. V to. V, Bidirectional Logic Level Translation, Bypass Switch ADG FEATURES Operates from. V to. V supply rails Bidirectional level translation, unidirectional signal path -lead
Am27C128. Advanced Micro Devices. 128 Kilobit (16,384 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL
FINAL 128 Kilobit (16,384 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 45 ns Low power consumption 20 µa typical CMOS standby current JEDEC-approved pinout Single
Features. Applications
DATASHEET 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER ICS98UAE877A Description The PLL clock buffer, ICS98UAE877A, is designed for a of 1.5V, an AVDD of 1.5V and differential data input and output
PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic
FINAL COM L: H-5/7/10/15/25, -10/15/25 IND: H-10/15/25, -20/25 PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS Pin and function compatible with all 20-pin
PI2PCIE2214. PCI Express 2.0, 1-lane, 4:1 Mux/DeMux Switch. Features. Description. Application. Pin Description. Block Diagram.
Features 2 Differential Channel, 4:1 Mux/DeMux PCI Express 2.0 performance, 5.0 Gbps Low Bit-to-Bit Skew, 7ps Max. Low Crosstalk: -23dB@3GHz Low Off Isolation: -23dB@3GHz Operating Range: 1.8V ±10% ESD
2-Megabit (256K x 8) 5-volt Only CMOS Flash Memory AT29C020. Features. Description. Pin Configurations
Features Fast Read Access Time - 90 ns 5-Volt-Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (256 bytes/sector) Internal Address and Data Latches for
AS6C K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Rev. 1.1 Initial Issue Add package 48-ball 8mm 10mm TFBGA Revised ORDERING INFORMATION in page 11 Jan.09.2012 July.12.2013 0 FEATURES Fast access
CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
Integrated evice Technology, Inc. CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 124 X 9, 248 X 9 and 496 x 9 IT72421 IT7221 IT72211 IT72221 IT72231 IT72241 FEATURES: 64 x 9-bit organization (IT72421) 256 x 9-bit
COM L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/20/25. Programmable AND Array (44 x 132) OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL
FINAL COM L: H-5/7//5/25, -/5/25 IND: H-/5/2/25 PALCE22V Family 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS As fast as 5-ns propagation delay and 42.8 MHz fmax (external) Low-power
FST3257 Quad 2:1 Multiplexer / Demultiplexer Bus Switch
FST3257 Quad 2:1 Multiplexer / Demultiplexer Bus Switch Features 4Ω Switch Connection Between Two Ports Minimal Propagation Delay Through the Switch Low I CC Zero Bounce in Flow-Through Node Control Inputs
ATF16V8B. High Performance Flash PLD. Features. Block Diagram. Description. Pin Configurations
Features Industry Standard Architecture Emulates Many 20-Pin PALs Low Cost Easy-to-Use Software Tools High Speed Electrically Erasable Programmable Logic Devices 7.5 ns Maximum Pin-to-Pin Delay Several
IDT7134SA/LA. HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM
Features High-speed access : 5/45//7 (max.) Industrial: / (max.) Commercial: 2//5/45//7 (max.) Low-power operation IDT714 Active: 7mW (typ.) Standby: 5mW (typ.) IDT714 Active: 7mW (typ.) Standby: 1mW (typ.)