Computer System Architecture

Transcription

1 CSC Computer System Architecture Budditha Hettige Department of Statistics and Computer Science University of Sri Jayewardenepura

2 Microprocessors 2011 Budditha Hettige 2

3 Processor Instructions Intel (1985) x86 (IA-32) Intel (1989) x86 (IA-32) Intel Pentium I (1993) x86 (IA-32) Intel Pentium II (1997) IA-32, MMX 2011 Budditha Hettige 3

4 Processor Instructions(2) Intel Pentium III (1999) IA-32, MMX, SSE Intel Pentium IV (2000) x86 (i386), x86-64, MMX, SSE, SSE2, SSE3 Intel Core Duo MMX, SSE, SSE2, SSE3, EIST, XD bit Pentium Dual-Core MMX, SSE, SSE2, SSE3, SSSE3, x Budditha Hettige 4

5 Processor Modes 2011 Budditha Hettige 5

6 Processor modes Intel and Compatible processors are run in several modes Real Mode IA 32 Mode Protected Mode Virtual Real Mode IA 32e 64 bit mode 64-bit mode Compatibility mode 2011 Budditha Hettige 6

7 8086 Real Mode (x86) and later x86-compatible CPUs Execute 16 bit instructions Address only 1MB Memory Single task MS-Dos Programs are run in this mode Windows 1x, 3x 16 bit instructions No built in protection to keep one program overwriting another in memory 2011 Budditha Hettige 7

8 IA-32 - Protected Mode First implemented in the Intel as a 32- bit extension of x86 architecture Can run 32-bit instructions 32 bit OS and Application are Required Programs are protection to keep one program overwriting another in memory 2011 Budditha Hettige 8

9 Virtual Real mode (IA- 32 Mode) Backward compatibility (can run 16 bit apps) used to execute DOS programs in Windows/386, Windows 3.x, Windows 9x/Me 16 bit program run on the 32 bit protected mode Address only up to 1 Mb All Intel and Intel-supported processors power up in real mode 2011 Budditha Hettige 9

10 IA-32e 64 bit Exaction Mode Originally design by AMD, later adapted by Intel Processor can run Real mode IA 32 mode IA 32e mode IA -32e 64 bit is run 64 bit OS and 64 bit apps Need 64 bit OS and All 64 bit hardware 2011 Budditha Hettige 10

11 64-Bit Operating Systems Windows XP 64 bit Edition for Itanium (IA-64 bit processors) Windows XP professional x64( IA 32, Atholen 64) 32 bit Application can run without any probem 16 bit and Dos application does not run Problem? All 32-bit and 64 bit drivers are required 2011 Budditha Hettige 11

12 Physical memory limit 2011 Budditha Hettige 12

13 Features 2011 Budditha Hettige 13

14 Processors Features System Management Mode (SMM) MMX Technology SSE, SSE2, SSE3, SSE4 etc 3DNow!, Technology Math core processor Hyper Threading Dual core technology Quad core technology Intel Virtualization Execute Disable bit Intel Turbo Boost Technology 2011 Budditha Hettige 14

15 System Management Mode(SMM) is an operating mode is suspended, and special separate software is executed in high-privilege mode It is available in all later microprocessors in the x86 architecture Some uses of SMM are Handle system events like memory or chipset errors. Manage system safety functions, such as shutdown on high CPU temperature and turning the fans on and off. Control power management operations, such as managing the voltage regulator modules Budditha Hettige 15

16 MMX Technology Multimedia extension / Matrix math extension Improves audio/video compression MMX defined eight registers, known as MM0 through MM7 Each of the MMn registers holds 64 bits MMX provides only integer operations Used for both 2D and 3D calculations 57 new instructions + (SIMD- Single instruction multiple data) 2011 Budditha Hettige 16

17 SSE -Streaming SIMD Extensions Used to accelerate floating point and parallel calculations is a SIMD instruction set extension to the x86 architecture subsequently expanded by Intel to SSE2, SSE3, SSSE3, and SSE4 it supports floating point math SSE originally added eight new 128-bit registers known as XMM0 through XMM7 SSE Instructions Floating point instructions Integer instructions Other instructions 2011 Budditha Hettige 17

18 SSE2- Streaming SIMD Extensions 2 Introduce in Pentium IV Add 114 additional instructions Also include MMX and SSE instructions SSE2 is an extension of the IA-32 architecture 2011 Budditha Hettige 18

19 SSE3- Streaming SIMD Extensions 3 Introduce in PIV Prescott processor Code name Prescott New Instructions (PNI) Contains 13 new instructions Also include MMX, SSE, SSE Budditha Hettige 19

20 SSE3- Supple Introduce in xeon and Core 2 processors Add new 32 SIMD instructions to SSE Budditha Hettige 20

21 SSE4 (HD BOOT) Introduce by Intel in 2008 Adds 54 new instructions 47 of SSE4 instructions are referred to as SSE4.1 7 other instruction as SSE4.2 SSE4.1 is targeted to improve performance of media, imaging and 3D SSE4.2 improves string and text processing 2011 Budditha Hettige 21

22 SSE - Advantages Higher quality and high quality image resolution High quality audio and MPEG2 Video multi media application support Reduce CPU utilization for speech recognition software SSEx instructions are useful withmpeg2 decoding 2011 Budditha Hettige 22

23 3DNow! Technology AMD s alternative to SSE Uses 21 instructions uses SIMD technologies Enhanced 3DNow! ADDS 24 more instructions Professional 3DNow! Adds 51 SSE command to the Enhanced 3DNow! 2011 Budditha Hettige 23

24 Math coprocessor Provides hardware for plotting point Math Speed Computer Operations All Intel processors since 486DX include builtin floating point unit (FPU) Can performance high level mathematical operation Instruction set differ from main CPU 2011 Budditha Hettige 24

25 Hyper-Threading Technology Is an Intel-proprietary technology used to improve parallelization of computations doing multiple tasks at once The operating system addresses two virtual processors, and shares the workload between them when possible Allowing multiple threads to run simultaneously 2011 Budditha Hettige 25

26 Hyper-Threading Technology Originally introduce Xeon processor for Servers (2002) Available all PIV processor with bus speed 800 MHz HT enable processors has 2 set of general purpose registers, control registers Only Single Cache memory and Single Buses 2011 Budditha Hettige 26

27 HT - Requirements Processor with HT Technology Compatible MB (Chipset) BIOS support Compatible OS Software written to Support HT 2011 Budditha Hettige 27

28 Dual Core Technology Introduce in 2005 Consist of 2 CPU cores (Enable Single processors to work as 2 processors) Multi Tasking performance is improved 2011 Budditha Hettige 28

29 Quad-Core Technology Consist of 4 CPU cores (Enable Single processors to work as 4 processors) Less power consumption Design to provide multimedia and multi tasking experience 2011 Budditha Hettige 29

30 Intel Virtualization Allows hardware platform to run multiple platform Available in Core to Quad processors 2011 Budditha Hettige 30

31 Execute Disable Bit Is a hardware-based security feature Can reduce exposure to viruses and maliciouscode attacks and prevent harmful software from executing and propagating on the server or network. Help protect your customers' business assets and reduce the need for costly virus-related repairs by building systems with built-in Intel Execute Disable Bit Budditha Hettige 31

32 Intel Turbo Boost Technology Provides more performance when needed Automatically allows processor cores to run faster than the base operating frequency Depends on the workload and operating environment Processor frequency will dynamically increase until the upper limit of frequency is reached Has multiple algorithms operating in parallel to manage current, power, and temperature to maximize performance and energy efficiency 2011 Budditha Hettige 32

33 Bugs 2011 Budditha Hettige 33

34 Bugs Processor can contain defects or errors Only way to fix the bug Work around it or replace it with bugs free Now Many bugs to be fixed by altering the microcode Microcode gives set of information how processor works Incorporate Reprogrammable Microcode 2011 Budditha Hettige 34

35 Fixing the Bugs Microcode updates reside in ROM BIOS Each time the system rebooted fixed code is loaded These microcode is provided by Intel to motherboard manufacturers and they can incorporate it into ROM BIOS Need to install most recent BIOS every time 2011 Budditha Hettige 35

36 CPU Design Strategy CISC & RISC 2011 Budditha Hettige 36

37 What is CISC? CISC is an acronym for Complex Instruction Set Computer Most common microprocessor designs such as the Intel 80x86 and Motorola 68K series followed the CISC philosophy. But recent changes in software and hardware technology have forced a re-examination of CISC and many modern CISC processors are hybrids, implementing many RISC principles. CISC was developed to make compiler development simpler Budditha Hettige 37

38 CISC Characteristics 2-operand format, Variable length instructions where the length often varies according to the addressing mode Instructions which require multiple clock cycles to execute. E.g. Pentium is considered a modern CISC processor Complex instruction-decoding logic, driven by the need for a single instruction to support multiple addressing modes. A small number of general purpose registers Several special purpose registers. A 'Condition code" register which is set as a side-effect of most instructions Budditha Hettige 38

39 CISC Advantages Microprogramniing is as easy as assembly language to implement The ease of microcoding new instructions allowed designers to make CISC machines upwardly compatible: a new computer could run the same programs as earlier computers because the new computer would contain a superset of the instructions of the earlier computers. As each instruction became more capable, fewer instructions could be used to implement a given task. This made more efficient use of the relatively slow main memory Budditha Hettige 39

40 CISC Disadvantages Instruction set & chip hardware become more complex with each generation of computers. Many specialized instructions aren't used frequently enough to justify their existence - CISC instructions typically set the condition codes as a side effect of the instruction Budditha Hettige 40

41 What is RISC? RISC - Reduced Instruction Set Computer. is a type of microprocessor architecture utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. History The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC Budditha Hettige 41

42 RISC - Characteristic one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called PIPELINING pipelining: a techique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions; large number of registers: the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory 2011 Budditha Hettige 42

43 RISC Attributes The main characteristics of CISC microprocessors are: Extensive instructions. Complex and efficient machine instructions. Microencoding of the machine instructions. Extensive addressing capabilities for memory operations. Relatively few registers. In comparison, RISC processors are more or less the opposite of the above: Reduced instruction set. Less complex, simple instructions. Hardwired control unit and machine instructions. Few addressing schemes for memory operands with only two basic instructions, LOAD and STORE 2011 Budditha Hettige 43

44 CISC Vs RISC CISC Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Small code sizes, high cycles per second Transistors used for storing complex instructions RISC Emphasis on software Single-clock, reduced instruction only Register to register: "LOAD" and "STORE" are independent instructions Low cycles per second, large code sizes Spends more transistors on memory registers 2011 Budditha Hettige 44