COMPUTER STRUCTURE AND ORGANIZATION

Size: px

Start display at page:

Download "COMPUTER STRUCTURE AND ORGANIZATION"

Alexis Riley
5 years ago
Views:

1 COMPUTER STRUCTURE AND ORGANIZATION Course titular: DUMITRAŞCU Eugen

2 Chapter 4 COMPUTER ORGANIZATION FUNDAMENTAL CONCEPTS

3 CONTENT The scheme of 5 units von Neumann principles Functioning of a von Neumann computer Harvard Architecture Harvard vs von Neumann Modified Harvard Architecture CISC and RISC processors 15-Apr-18 CSO_

4 THE SCHEME OF 5 UNITS Definition: It's called computer system any system that is able to achieve the following objectives: 1. to accept inputs that representing a coded form of information (input data or operands); 2. to process data according to an algorithm; 3. to provide to the output information (output data or results) in a human or another computer accessible form. 15-Apr-18 CSO_

5 THE SCHEME OF 5 UNITS 15-Apr-18 CSO_

6 THE SCHEME OF 5 UNITS 15-Apr-18 CSO_

7 CONTENT The scheme of 5 units von Neumann principles Functioning of a von Neumann computer Harvard Architecture Harvard vs von Neumann Modified Harvard Architecture CISC and RISC processors 15-Apr-18 CSO_

8 VON NEUMANN PRINCIPLES P1. The information in computer is binary coded. P2. Binary coding rules are the same regardless of the information nature. P3. For binary coded data and programs the computer has a special block denoted memory block. 15-Apr-18 CSO_

9 VON NEUMANN PRINCIPLES P4. Binary coded commands have relatively rigid structure, composed mainly of two parts called fields (field operation code <<OPCODE>> and the address field). Such command is called machine code instruction. P5. All operations of computer are executed sequentially, ie one after another. It is not accepted any parallelism in the execution of various types of operations. 15-Apr-18 CSO_

10 CONTENT The scheme of 5 units von Neumann principles Functioning of a von Neumann computer Harvard Architecture Harvard vs von Neumann Modified Harvard Architecture CISC and RISC processors 15-Apr-18 CSO_

11 FUNCTIONING OF VON NEUMANN COMPUTER 15-Apr-18 CSO_

12 CONTENT The scheme of 5 units von Neumann principles Functioning of a von Neumann computer Harvard Architecture Harvard vs von Neumann Modified Harvard Architecture CISC and RISC processors 15-Apr-18 CSO_

13 HARVARD ARCHITECTURE The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape (24 bits wide) and data in electro-mechanical counters (relays) that allowed 23 digits. It is observed that each of the two memory blocks communicate with the CPU through an own bus set, which usually increases working speed of the processor. Instruction memory content can only be read by the processor, while in the data memory the processor can both read and write, depends on in the nature of executed instructions. It is not necessary that the two memory types have common parameters. Usually the capacity, width of a location, speed, can be very different. Thus, the instruction memory usually has a higher capacity and is ROM type and data memory is RAM type. Each of these has its own memory address space, so there is an instruction address 0 and address 0 for data. 15-Apr-18 CSO_

14 HARVARD ARCHITECTURE 15-Apr-18 CSO_

15 CONTENT The scheme of 5 units von Neumann principles Functioning of a von Neumann computer Harvard Architecture Harvard vs von Neumann Modified Harvard Architecture CISC and RISC processors 15-Apr-18 CSO_

16 HARVARD VS VON NEUMANN In pure von Neumann architecture at a time the processor is either in fetch phase and read the code of the instruction or in the execution phase and read/write data from/to memory. Any parallelism between the two phases is excluded because the memory and processor is connected to a single bus. This seriously affects the CPU performance because the memory access time is much greater than the time of processing. Currently there are memories with access time less than the usual ones but due to consumption and the cost can be used only in very small capacity. Therefore in applications which priority is the speed of calculation, is required to use Harvard architecture. Harvard structure allows a simple extension for SIMD processing using a single instruction memory and more memory for data. 15-Apr-18 CSO_

HARVARD VS VON NEUMANN On the other hand in von Neumann architecture the instructions can be processed like any other operand (principle P2) that increases the flexibility of use.

17 HARVARD VS VON NEUMANN On the other hand in von Neumann architecture the instructions can be processed like any other operand (principle P2) that increases the flexibility of use. Because of this, general computers use processor with von Neumann architecture. Keeping in memory the same data and executable code simplifies the implantation of some viruses introduced as a package of data, although in reality it's executable instructions. For this reason, were created different architectures that combines the advantages of both pure architecture above and at the same time to eliminate specific shortcomings. 15-Apr-18 CSO_

18 HARVARD VS VON NEUMANN Conclusion There are three criteria that distinguish the two architectures: Address space for data and instructions; The existence of one or more ways (buses) of access between processor and memory; Possibility to access different data and instructions. 15-Apr-18 CSO_

19 CONTENT The scheme of 5 units von Neumann principles Functioning of a von Neumann computer Harvard Architecture Harvard vs von Neumann Modified Harvard Architecture CISC and RISC processors 15-Apr-18 CSO_

20 MODIFIED HARVARD ARCHITECTURE Modified Harvard architecture is any variant of Harvard architecture that allows access instruction memory content as if it represents data. Changes may be made in various ways, for each time removing the strict barrier between code and data, without losing the advantage of parallel access to data and instructions specific for pure Harvard architecture. Some variants keep separate address spaces but provides special machine code instruction to access instruction memory as if it contains data. This allows maintenance of constants in instruction memory, freeing space in data memory. Also, initial data can also be transferred directly from instruction memory in data memory that at startup of computer has a random content. Currently Harvard architecture computers used increasingly more flash memory as instruction memory which allows reading and writing instructions as a RAM, but with slower speed. This is useful when it comes to change a program or changing a flash memory module. A frequently used solution is to introduce a cache mamory that separates instructions from data. 15-Apr-18 CSO_

21 CONTENT The scheme of 5 units von Neumann principles Functioning of a von Neumann computer Harvard Architecture Harvard vs von Neumann Modified Harvard Architecture CISC and RISC processors 15-Apr-18 CSO_

22 CISC AND RISC PROCESSORS It is considered that an instruction is simple if made a relatively simple operation that involves a small number of resources and can be generally performed during one clock pulse. Example: incrementing a register of the processor, reading a data from memory, writing a data memory, addition/subtraction operations between the contents of two registers, jump or branch instructions etc. It is considered that an instruction is complex if it can not be executed during a clock pulse, involving several different resuse (processor + memory) and can be replaced by a series of simple instructions. Example: arithmetic and logical operations with one operand from memory, subroutines calls, etc. 15-Apr-18 CSO_

23 CISC AND RISC PROCESSORS A simple instruction can be executed directly by the processor using a specialized unit (ALU). For complex instructions it is impossible because it would involve many specialized units, difficult or even impossible with current technologies. These instructions are initially converted into microinstructions executed by a microprogrammed processor. CISC - Complex Instruction Set Computer RISC - Reduced Instruction Set Computer 15-Apr-18 CSO_

24 CISC AND RISC PROCESSORS CISC processors advantages shortening application programs; simplifying compilers; possibility to change machine code language only through microprogram changing without changing the hardware structure of the processor; reducing the memory capacity occupied by code (essential for the years `60-`70). CISC processors disadvantages Many differences in length of different instructions; Great differences between execution times; Microcode unity realization occupies much space on the silicon chip; It was found that the instructions with the highest degree of complexity are the least used in practice. 15-Apr-18 CSO_

25 CISC AND RISC PROCESSORS 15-Apr-18 CSO_

26 CISC AND RISC PROCESSORS RISC processors advantages use a set of instructions with fewer simple instruction; eliminating microcode and increasing the speed of work; the possibility of executing an instruction on a single clock cycle; instructions with the same length; accessing the main memory by only two simple instructions - LOAD and STORE; simplifying memory addressing modes by internal architecture; increasing the number of internal registers which reduces the number of accesses to main memory; using a format of instruction that eliminate almost complete the instruction decoder, simplifying the structure of the processor (at the processors on 32 or 64 bits); facilitating parallelism in CPU activity (CPU pipeline); reducing energy consumption per processor. RISC processors disadvantages the need for sophisticated compiler to optimize code; the code obtained from the compiling is longer. 15-Apr-18 CSO_

27 QUESTIONS? 15-Apr-18 CSO_

Advanced Parallel Architecture Lesson 3. Annalisa Massini /2015

Advanced Parallel Architecture Lesson 3 Annalisa Massini - 2014/2015 Von Neumann Architecture 2 Summary of the traditional computer architecture: Von Neumann architecture http://williamstallings.com/coa/coa7e.html