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1 Today The Memory Hierarchy Storage technologies and trends Locality of reference Caching in the memory hierarchy /18-243: Introduc3on to Computer Systems 1 th Lecture, Feb. 13, 214 Instructors: Anthony Rowe, Seth Goldstein and Gregory Kesden 1 2 Random- Access Memory (RAM) SRAM vs DRAM Summary Key features RAM is tradi3onally packaged as a chip. Basic storage unit is normally a cell (one bit per cell). Mul3ple RAM chips form a memory. StaAc RAM (SRAM) Each cell stores a bit with a four or six- transistor circuit. Retains value indefinitely, as long as it is kept powered. Rela3vely insensi3ve to electrical noise (EMI), radia3on, etc. Faster and more expensive than DRAM. Dynamic RAM (DRAM) Each cell stores bit with a capacitor. One transistor is used for access Value must be refreshed every 1-1 ms. More sensi3ve to disturbances (EMI, radia3on, ) than SRAM. Slower and cheaper than SRAM. 3 Trans. Access Needs Needs per bit time refresh? EDC? Cost Applications SRAM 4 or 6 1X No Maybe 1x Cache memories DRAM 1 1X Yes Yes 1X Main memories, frame buffers 4 1
2 ConvenAonal DRAM OrganizaAon d x w DRAM: dw total bits organized as d supercells of size w bits Reading DRAM Supercell (2,1) Step 1(a): Row access strobe (RAS) selects row 2. Step 1(b): Row 2 copied from DRAM array to row buffer. 16 x 8 DRAM chip 16 x 8 DRAM chip (to/from CPU) Memory 2 bits / addr 8 bits / data rows cols supercell (2,1) Memory RAS = 2 2 / addr 8 / data 1 Rows 2 3 Cols Internal row buffer Internal row buffer 5 6 Reading DRAM Supercell (2,1) Step 2(a): Column access strobe (CAS) selects column 1. Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU. To CPU supercell (2,1) Memory CAS = 1 2 / addr 8 / data 16 x 8 DRAM chip 1 Rows 2 3 Cols Memory Modules addr (row = i, col = j) DRAM 7 bits bits bits bits bits bits DRAM bits bit doubleword at main memory address A bits -7 : supercell (i,j) 64 MB memory module consisting of eight 8Mx8 DRAMs Memory supercell (2,1) Internal row buffer 7 64-bit doubleword 8 2
3 Enhanced DRAMs NonvolaAle Memories Basic DRAM cell has not changed since its invenaon in Commercialized by Intel in 197. DRAM cores with bever interface logic and faster I/O : Synchronous DRAM (SDRAM) Uses a conven3onal clock signal instead of asynchronous control Allows reuse of the row addresses (e.g., RAS, CAS, CAS, CAS) Double data- rate synchronous DRAM (DDR SDRAM) Double edge clocking sends two bits per cycle per pin Different types dis3nguished by size of small prefetch buffer: DDR (2 bits), DDR2 (4 bits), DDR4 (8 bits) By 21, standard for most server and desktop systems Intel Core i7 supports only DDR3 SDRAM DRAM and SRAM are volaale memories Lose informa3on if powered off. NonvolaAle memories retain value even if powered off Read- only memory (ROM): programmed during produc3on Programmable ROM (PROM): can be programmed once Eraseable PROM (EPROM): can be bulk erased (UV, X- Ray) Electrically eraseable PROM (EEPROM): electronic erase capability Flash memory: EEPROMs with par3al (sector) erase capability Wears out aber about 1, erasings. Uses for NonvolaAle Memories Firmware programs stored in a ROM (BIOS, s for disks, network cards, graphics accelerators, security subsystems, ) Solid state disks (replace rota3ng disks in thumb drives, smart phones, mp3 players, tablets, laptops, ) caches 9 1 TradiAonal Bus Structure ConnecAng CPU and Memory A bus is a collecaon of parallel wires that carry address, data, and control signals. Buses are typically shared by mulaple devices. Memory Read TransacAon (1) CPU places address A on the memory bus. Load operation: movl A, %eax CPU chip %eax I/O bridge A Main memory x A System bus Memory bus I/O bridge Main memory
4 Memory Read TransacAon (2) Main memory reads A from the memory bus, retrieves word x, and places it on the bus. Memory Read TransacAon (3) CPU read word x from the bus and copies it into register %eax. Load operation: movl A, %eax Load operation: movl A, %eax %eax %eax x I/O bridge Main memory x I/O bridge Main memory x A x A Memory Write TransacAon (1) Memory Write TransacAon (2) CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive. CPU places data word y on the bus. Store operation: movl %eax, A Store operation: movl %eax, A %eax y %eax y I/O bridge A Main memory A I/O bridge y Main memory A
5 Memory Write TransacAon (3) What s Inside A Drive? Main memory reads data word y from the bus and stores it at address A. Arm Spindle Platters register file Store operation: movl %eax, A Actuator %eax y I/O bridge main memory bus interface y A SCSI connector Electronics (including a processor and memory!) Image courtesy of Seagate Technology Geometry Geometry (Muliple- PlaVer View) s consist of plavers, each with two surfaces. Aligned tracks form a cylinder. Each surface consists of concentric rings called tracks. Cylinder k Each track consists of sectors separated by gaps. Tracks Surface Track k Gaps Surface Surface 1 Surface 2 Surface 3 Surface 4 Surface 5 Platter Platter 1 Platter 2 Spindle Spindle Sectors
6 Capacity Capacity: maximum number of bits that can be stored. Vendors express capacity in units of gigabytes (GB), where 1 GB = 19 Bytes (Lawsuit pending! Claims decep3ve adver3sing). Capacity is determined by these technology factors: Recording density (bits/in): number of bits that can be squeezed into a 1 inch segment of a track. Track density (tracks/in): number of tracks that can be squeezed into a 1 inch radial segment. Areal density (bits/in2): product of recording and track density. Modern disks paraaon tracks into disjoint subsets called recording zones Each track in a zone has the same number of sectors, determined by the circumference of innermost track. Each zone has a different number of sectors/track CompuAng Capacity Capacity = (# bytes/sector) x (avg. # sectors/track) x (# tracks/surface) x (# surfaces/plaver) x (# plavers/disk) Example: 512 bytes/sector 3 sectors/track (on average) 2, tracks/surface 2 surfaces/plager 5 plagers/disk Capacity = 512 x 3 x 2 x 2 x 5 = 3,72,, = 3.72 GB OperaAon (Single- PlaVer View) OperaAon (MulA- PlaVer View) The disk surface spins at a fixed rotational rate The read/write head is attached to the end of the arm and flies over the disk surface on a thin cushion of air. Read/write heads move in unison from cylinder to cylinder Arm spindle spindle spindle spindle Spindle By moving radially, the arm can position the read/write head over any track
7 Structure - top view of single plaver Access Surface organized into tracks Tracks divided into sectors Head in position above a track Access Access Read Rotation is counter-clockwise About to read blue sector
8 Access Read Access Read After BLUE read After BLUE read After reading blue sector Red request scheduled next 29 3 Access Seek Access RotaAonal Latency After BLUE read Seek for RED After BLUE read Seek for RED Rotational latency Seek to red s track Wait for red sector to rotate around
9 Access Read Access Service Time Components After BLUE read Seek for RED Rotational latency After RED read After BLUE read Seek for RED Rotational latency After RED read Complete read of red Data transfer Seek RotaAonal latency Data transfer Access Time Access Time Example Average Ame to access some target sector approximated by : Taccess = Tavg seek + Tavg rota3on + Tavg transfer Seek Ame (Tavg seek) Time to posi3on heads over cylinder containing target sector. Typical Tavg seek is 3 9 ms RotaAonal latency (Tavg rotaaon) Time wai3ng for first bit of target sector to pass under r/w head. Tavg rota3on = 1/2 x 1/RPMs x 6 sec/1 min Typical Tavg rota3on = 72 RPMs Transfer Ame (Tavg transfer) Time to read the bits in the target sector. Tavg transfer = 1/RPM x 1/(avg # sectors/track) x 6 secs/1 min. 35 Given: Rota3onal rate = 7,2 RPM Average seek 3me = 9 ms. Avg # sectors/track = 4. Derived: Tavg rota3on = 1/2 x (6 secs/72 RPM) x 1 ms/sec = 4 ms. Tavg transfer = 6/72 RPM x 1/4 secs/track x 1 ms/sec =.2 ms Taccess = 9 ms + 4 ms +.2 ms Important points: Access 3me dominated by seek 3me and rota3onal latency. First bit in a sector is the most expensive, the rest are free. SRAM access 3me is about 4 ns/doubleword, DRAM about 6 ns is about 4, 3mes slower than SRAM, 2,5 3mes slower then DRAM. 36 9
10 Logical Blocks Modern disks present a simpler abstract view of the complex sector geometry: The set of available sectors is modeled as a sequence of b- sized logical blocks (, 1, 2,...) Mapping between logical blocks and actual (physical) sectors Maintained by hardware/firmware device called disk. Converts requests for logical blocks into (surface,track,sector) triples. Allows to set aside spare cylinders for each zone. Accounts for the difference in formaged capacity and maximum capacity. I/O Bus CPU chip USB Mouse Keyboard Graphics adapter Monitor System bus I/O bridge I/O bus Memory bus Main memory Expansion slots for other devices such as network adapters Reading a Sector (1) CPU chip CPU initiates a disk read by writing a command, logical block number, and destination memory address to a port (address) associated with disk. Reading a Sector (2) CPU chip reads the sector and performs a direct memory access (DMA) transfer into main memory. Main memory Main memory I/O bus I/O bus USB Graphics adapter USB Graphics adapter mouse keyboard Monitor 39 Mouse Keyboard Monitor 4 1
11 Reading a Sector (3) CPU chip When the DMA transfer completes, the disk notifies the CPU with an interrupt (i.e., asserts a special interrupt pin on the CPU) I/O bus Main memory Solid State s (SSDs) Solid State (SSD) I/O bus Flash memory Block Page Page 1 Page P-1 Flash translation layer Requests to read and write logical disk blocks Block B-1 Page Page 1 Page P-1 USB Mouse Keyboard Graphics adapter Monitor 41 Pages: 512KB to 4KB, Blocks: 32 to 128 pages Data read/wriven in units of pages. Page can be wriven only aier its block has been erased A block wears out aier 1, repeated writes. 42 SSD Performance CharacterisAcs SSD Tradeoffs vs RotaAng s SequenAal read tput 25 MB/s SequenAal write tput 17 MB/s Random read tput 14 MB/s Random write tput 14 MB/s Rand read access 3 us Random write access 3 us Why are random writes so slow? Erasing a block is slow (around 1 ms) Write to a page triggers a copy of all useful pages in the block Find an used block (new block) and erase it Write the page into the new block Copy other pages from old block to the new block Advantages No moving parts à faster, less power, more rugged Disadvantages Have the poten3al to wear out Mi3gated by wear leveling logic in flash transla3on layer E.g. Intel X25 guarantees 1 petabyte (115 bytes) of random writes before they wear out In 21, about 1 3mes more expensive per byte ApplicaAons MP3 players, smart phones, laptops Beginning to appear in desktops and servers
12 Storage Trends SRAM Metric :198 $/MB 19,2 2, access (ns) CPU Clock Rates InflecAon point in computer history when designers hit the Power Wall :198 CPU Pentium P-III P-4 Core 2 Core i7 --- DRAM Metric :198 $/MB 8, , access (ns) typical size (MB) , 8, 125, Metric :198 $/MB ,6, access (ms) typical size (MB) , 2, 16, 1,5, 1,5, 45 Clock rate (MHz) Cycle time (ns) Cores Effective cycle , time (ns) 46 The CPU- Memory Gap The gap between DRAM, disk, and CPU speeds. Locality to the Rescue! 1,,. 1,,. 1,,. 1,. SSD The key to bridging this CPU- Memory gap is a fundamental property of computer programs known as locality ns 1,. 1,. 1. DRAM seek time Flash SSD access time DRAM access time SRAM access time CPU cycle time Effective CPU cycle time CPU Year
13 Today Locality Storage technologies and trends Locality of reference Caching in the memory hierarchy Principle of Locality: Programs tend to use data and instrucaons with addresses near or equal to those they have used recently Temporal locality: Recently referenced items are likely to be referenced again in the near future SpaAal locality: Items with nearby addresses tend to be referenced close together in 3me 49 5 Locality Example sum = ; for (i = ; i < n; i++) sum += a[i]; return sum; QualitaAve EsAmates of Locality Claim: Being able to look at code and get a qualitaave sense of its locality is a key skill for a professional programmer. Data references Reference array elements in succession (stride- 1 reference pagern). Reference variable sum each itera3on. InstrucAon references Reference instruc3ons in sequence. Cycle through loop repeatedly. SpaAal locality Temporal locality SpaAal locality Temporal locality QuesAon: Does this funcaon have good locality with respect to array a? int sum_array_rows(int a[m][n]) { int i, j, sum = ; } for (i = ; i < M; i++) for (j = ; j < N; j++) sum += a[i][j]; return sum;
14 Locality Example QuesAon: Does this funcaon have good locality with respect to array a? int sum_array_cols(int a[m][n]) { int i, j, sum = ; } for (j = ; j < N; j++) for (i = ; i < M; i++) sum += a[i][j]; return sum; Locality Example QuesAon: Can you permute the loops so that the funcaon scans the 3- d array a with a stride- 1 reference pavern (and thus has good spaaal locality)? int sum_array_3d(int a[m][n][n]) { int i, j, k, sum = ; } for (i = ; i < M; i++) for (j = ; j < N; j++) for (k = ; k < N; k++) sum += a[k][i][j]; return sum; Memory Hierarchies Some fundamental and enduring properaes of hardware and soiware: Fast storage technologies cost more per byte, have less capacity, and require more power (heat!). The gap between CPU and main memory speed is widening. Well- wrigen programs tend to exhibit good locality. Today Storage technologies and trends Locality of reference Caching in the memory hierarchy These fundamental properaes complement each other beauafully. They suggest an approach for organizing memory and storage systems known as a memory hierarchy
15 An Example Memory Hierarchy Caches Smaller, faster, costlier per byte Larger, slower, cheaper per byte L5: L4: L3: L2: L1: L: Registers L1 cache (SRAM) L2 cache (SRAM) Main memory (DRAM) Local secondary storage (local disks) CPU registers hold words retrieved from L1 cache Remote secondary storage (tapes, distributed file systems, Web servers) L1 cache holds cache lines retrieved from L2 cache L2 cache holds cache lines retrieved from main memory Main memory holds disk blocks retrieved from local disks Local disks hold files retrieved from disks on remote network servers Cache: A smaller, faster storage device that acts as a staging area for a subset of the data in a larger, slower device. Fundamental idea of a memory hierarchy: For each k, the faster, smaller device at level k serves as a cache for the larger, slower device at level k+1. Why do memory hierarchies work? Because of locality, programs tend to access the data at level k more oben than they access the data at level k+1. Thus, the storage at level k+1 can be slower, and thus larger and cheaper per bit. Big Idea: The memory hierarchy creates a large pool of storage that costs as much as the cheap storage near the bovom, but that serves data to programs at the rate of the fast storage near the top General Cache Concepts General Cache Concepts: Hit Request: 14 Data in block b is needed Cache Smaller, faster, more expensive memory caches a subset of the blocks Cache Block b is in cache: Hit! 1 4 Data is copied in block- sized transfer units Memory Larger, slower, cheaper memory viewed as paraaoned into blocks Memory
16 General Cache Concepts: Miss General Caching Concepts: Types of Cache Misses Cache Memory Request: Request: Data in block b is needed Block b is not in cache: Miss! Block b is fetched from memory Block b is stored in cache Placement policy: determines where b goes Replacement policy: determines which block gets evicted (vic3m) Cold (compulsory) miss Cold misses occur because the cache is empty. Conflict miss Most caches limit blocks at level k+1 to a small subset (some3mes a singleton) of the block posi3ons at level k. E.g. Block i at level k+1 must be placed in block (i mod 4) at level k. Conflict misses occur when the level k cache is large enough, but mul3ple data objects all map to the same level k block. E.g. Referencing blocks, 8,, 8,, 8,... would miss every 3me. Capacity miss Occurs when the set of ac3ve cache blocks (working set) is larger than the cache Examples of Caching in the Hierarchy Summary Cache Type Registers TLB L1 cache L2 cache Virtual Memory Buffer cache Network buffer cache Browser cache What is Cached? 4-8 bytes words Address translaaons 64- bytes block 64- bytes block 4- KB page Parts of files Parts of files Web pages Where is it Cached? CPU core On- Chip TLB On- Chip L1 On/Off- Chip L2 Main memory Main memory Local disk Local disk Latency (cycles) ,, 1,, Managed By Compiler Hardware Hardware Hardware Hardware + OS cache sectors 1, firmware OS AFS/NFS client Web browser The speed gap between CPU, memory and mass storage conanues to widen. Well- wriven programs exhibit a property called locality. Memory hierarchies based on caching close the gap by exploiang locality. Web cache Web pages Remote server disks 1,,, Web proxy server
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