The Memory Hierarchy. Computer Organization 2/12/2015. CSC252 - Spring Memory. Conventional DRAM Organization. Reading DRAM Supercell (2,1)

Transcription

1 Computer Organization 115 The Hierarch Kai Shen Random access memor (RM) RM is traditionall packaged as a chip. Basic storage unit is normall a cell (one bit per cell). Multiple RM chips form a memor. Static RM (SRM) Each cell stores a bit with a four or six transistor circuit. Retains value indefinitel, as long as it is kept powered. Relativel insensitive to electrical noise, radiation, etc. Dnamic RM (DRM) Each cell stores bit with a capacitor. One transistor is used for access. Value must be refreshed ever 1 1 ms. More sensitive to disturbances (electrical noise, radiation, ) than SRM. Slower and cheaper than SRM. 1 Conventional DRM Organization dxwdrm: (tofrom CPU) dw total organized as d supercells of size w 16 x 8 DRM chip addr 8 data 1 rows 3 cols 1 3 supercell (,1) Reading DRM Supercell (,1) Step 1(a): Row access strobe (RS) selects row. Step 1(b): Row copied from DRM arra to row buffer. RS = addr 8 data 16 x 8 DRM chip 1 Rows 3 Cols 1 3 Internal row buffer 3 Internal row buffer 4 CSC5 - Spring 15 1

2 Computer Organization 115 Reading DRM Supercell (,1) Step (a): Column access strobe (CS) selects column 1. Step (b): Supercell (,1) copied from buffer to data lines, and eventuall back to the CPU. 16 x 8 DRM chip To CPU supercell (,1) CS = 1 addr 8 data 1 Rows 3 Cols 1 3 Modules addr (row = i, col = j) DRM DRM bit quadword at main memor address -7 : supercell (i,j) 64 MB memor module consisting of eight 8Mx8 DRMs supercell (,1) Internal row buffer 5 64-bit quadword 6 Nonvolatile Memories Uses of Nonvolatile Memories DRM and SRM are volatile memories Lose information if powered off. Nonvolatile memories retain value even if powered off Read onl memor (ROM): programmed during production Programmable ROM (PROM): can be programmed once Eraseable PROM (EPROM): can be bulk erased (UV, X Ra) Electricall eraseable PROM (EEPROM): electronic erase capabilit Flash memor: EEPROMs with partial (sector) erase capabilit Writes are slower than reads. Wears out after about 1, erasings. Phase change memories, memristors, STT MRM, Firmware programs stored in a ROM (BIOS, s for disks, network cards, graphics accelerators, securit subsstems, ) Solid state disks (replace rotating disks) Replacing DRM? 7 8 CSC5 - Spring 15

3 Computer Organization 115 Traditional Bus Structure Connecting CPU and bus is a collection of parallel wires that carr address, data, and control signals. Buses are tpicall shared b multiple devices. CPU chip Sstem bus bus Read Transaction (1) CPU places address on the memor bus. Load operation: movl, x High-speed bridge Main memor 9 1 Read Transaction () Read Transaction (3) reads from the memor bus, retrieves word x, and places it on the bus. CPU read word xfrom the bus and copies it into register. Load operation: movl, Load operation: movl, x x x x 11 1 CSC5 - Spring 15 3

4 Computer Organization 115 Write Transaction (1) Write Transaction () CPU places address on bus. reads it and waits for the corresponding data word to arrive. CPU places data word on the bus. Store operation: movl, Store operation: movl, Write Transaction (3) What s Inside Disk Drive? reads data word from the bus and stores it at address. rm Spindle Platters register file Store operation: movl, ctuator main memor bus interface SCSI connector Electronics (including a processor and memor!) Image courtes of Seagate Technolog CSC5 - Spring 15 4

5 Computer Organization 115 Disk Geometr Disk Operation Disks consist of platters, each with two surfaces. Each surface consists of concentric rings called tracks. Each track consists of sectors. Tracks Surface Track k The disk surface spins at a fixed rotational rate spindle spindle spindle spindle The readwrite head is attached to the end of the arm and flies over the disk surface on a thin cushion of air. Spindle B moving radiall, the arm can position the readwrite head over an track. Sectors Disk Geometr (Muliple Platter View) ligned tracks form a clinder. Clinder k Disk Operation (Multi Platter View) Readwrite heads move in unison from clinder to clinder Surface Surface 1 Surface Surface 3 Surface 4 Surface 5 Platter Platter 1 Platter Spindle rm Spindle 19 CSC5 - Spring 15 5

6 Computer Organization 115 Disk Seek and Rotation ccess to BLUE sector and then access to RED sector. Then access RED fter BLUE read Seek for RED Rotational latenc Disk ccess Time Time to access some target sector approximated b: Seek_time + Rotation_time + Transfer_time Seek time Time to position heads over clinder containing target sector. Tpicall 3 9 ms Rotational latenc Time waiting for first bit of target sector to pass under rw head. verage rotational latenc For a 1KRPM disk? Transfer time Time to read the in the target sector. 8MBs transfer speed. Time for transferring 4KB? ccess time dominated b seek time and rotational latenc! 1 CPU chip IO Bus Sstem bus Not Precise bus Main memor Search Northbridge on Wikipedia Flash based Solid State Disks (SSDs) Solid State Disk (SSD) IO bus Flash memor Block Page Page 1 Page P-1 Flash translation laer Requests to read and write logical disk blocks Block B-1 Page Page 1 Page P-1 USB Mouse Keboard Graphics adapter Monitor IO bus Disk Disk Expansion slots for other devices such as network adapters. 3 Pages: KB to 8KB, Blocks: 64 to 56 pages Data readwritten in units of pages. Page can be rewritten onl after an entire block has been erased block wears out after 1, repeated writes. 4 CSC5 - Spring 15 6

7 Computer Organization 115 SSD Performance Characteristics SSD Tradeoffs vs Rotating Disks Performance characteristics Sequential readswrites comparable (a bit faster) than disks Random reads are much faster than disks (.1ms vs. 1ms) Random writes are somewhat slower than reads (still much faster than disks) Wh are random writes slow? Erasing a block is slow (around 1 ms) and it forces a cop of all useful pages in the block dvantages No moving parts faster, less power, more rugged Disadvantages Have the potential to wear out Mitigated b wear leveling logic in flash translation laer 1 (or more) times more expensive per bte pplications MP3 plaers, smart phones, laptops Start to appear in desktops and servers 5 6 The CPU Gap Hierarch 1,,. ns 1,,. The gap 1,,. 1,. 1,. 1, between DRM, disk, and CPU speeds. Disk DRM SSD Disk seek time Flash SSD access time DRM access time SRM access time CPU ccle time Effective CPU ccle time Smaller, faster, costlier per bte Larger, slower, cheaper per bte L4: L3: L: L1: L: Registers L1 cache (SRM) L cache (SRM) (DRM) Local secondar storage (local disks) CPU registers hold words retrieved from L1 cache L1 cache holds cache lines retrieved from L cache L cache holds cache lines retrieved from main memor holds disk blocks retrieved from local disks Local disks hold files retrieved from disks on remote network servers.1. CPU Year 7 L5: Remote secondar storage (tapes, distributed file sstems, Web servers) 8 CSC5 - Spring 15 7

8 Computer Organization 115 Hierarch Localit Some fundamental and enduring properties of hardware and software: Fast storage technologies cost more per bte, have less capacit, and require more power (heat!). The gap between CPU and memorstorage speed is widening. Must pick between space or speed? Localit to the rescue Well written programs tend to exhibit good localit. Principle of Localit: Programs tend to use data and instructions with addresses near or equal to those the have used recentl Temporal localit: Recentl referenced items are likel to be referenced again in the near future Spatial localit: Items with nearb addresses tend to be referenced close together in time 9 3 Localit Example Qualitative Estimates of Localit Data references Reference arra elements in succession (stride 1 reference pattern). Reference variable sum each iteration. Instruction references sum = ; for (i = ; i < n; i++) sum += a[i]; return sum; Reference instructions in sequence. Ccle through loop repeatedl. Spatial localit Temporal localit Spatial localit Temporal localit Claim: Being able to look at code and get a qualitative sense of its localit is a ke skill for a professional programmer. Question: Does this function have good localit with respect to arra a? int sum_arra_rows(int a[m][n]) { int i, j, sum = ; } for (i = ; i < M; i++) for (j = ; j < N; j++) sum += a[i][j]; return sum; 31 3 CSC5 - Spring 15 8

9 Computer Organization 115 Localit Example Disclaimer Question: Does this function have good localit with respect to arra a? int sum_arra_cols(int a[m][n]) { int i, j, sum = ; These slides were adapted from the CMU course slides provided along with the textbook of Computer Sstems: programmer s Perspective b Brant and O Hallaron. The slides are intended for the sole purpose of teaching the computer organization course at the Universit of Rochester. } for (j = ; j < N; j++) for (i = ; i < M; i++) sum += a[i][j]; return sum; CSC5 - Spring 15 9