DRAM Disturbance Errors

Transcription

1 Flipping Bits in Memory Without Accessing Them An Experimental Study of DRAM Disturbance Errors Yoongu Kim Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu

2 Paper Overview Issue: Scaling down of DRAM process technology impacting on memory reliability ---> Disturbance Errors: reading from the same address repeatedly, it is possible to corrupt data in nearby addresses (ROW-HAMMER) Objective: Mimic the issue: demonstrate, characterize, analyze Solve it Method & Result: FPGA-based platform: 129 modules from 3 largest DRAM manufacturers 110 of 129 modules are vulnerable Affects modules of 2010 vintage or later Propose systematic solution: PARA(probabilistic adjacent row activation) Low power Low performance-overhead Average slowdown: 0.20% (for 29 benchmarks) Maximum slowdown: 0.75% 2

3 Outline Background - DRAM Flipping bits disturbance Demonstration (Real System) Characterization Solutions 3

4 DRAM Chip Row of Cells Row Victim Row Row Aggressor Row Row Victim Row Row Opened Closed Wordline V LOW HIGH Repeatedly opening and closing a row induces disturbance errors in adjacent rows 4

5 A Trip Down Memory Lane IBM s patent on DRAM Intel commercializes DRAM (Intel 1103) Suffered bitline-to-cell coupling Earliest DRAM with row-to-row coupling This paper mimicking row-to-row coupling Intel s patents mention Row Hammer 5

6 Mechanics of Disturbance Errors Cause 1: Electromagnetic coupling Toggling the wordline voltage briefly increases the voltage of adjacent wordlines Slightly opens adjacent rows Charge leakage Cause 2: Conductive bridges Cause 3: Hot-carrier injection Confirmed by at least one manufacturer 6

7 Outline Background - DRAM Flipping bits disturbance Demonstration (Real System) - How to Induce Errors Characterization Solutions 7

8 PCIe Infrastructure PC FPGA Board Test Engine DRAM Ctrl 8

9 Temperature Controller FPGAs Heater FPGAs PC

10 How to Induce Errors x86 CPU DRAM Module DDR3 1. Avoid cache hits Flush X from cache 2. Avoid row hits to X Read Y in another row X Y

11 How to Induce Errors x86 CPU DRAM Module DDR3 loop: mov (X), mov (Y), clflush (X) clflush (Y) mfence jmp loop X Y

12 Outline Background - DRAM Flipping bits disturbance Demonstration (Real System) - How to Induce Errors Characterization - result Solutions 12

13 Characterization: 13

14 Characterization Results 1. Most Modules Are at Risk 2. Errors vs. Vintage 3. Error = Charge Loss 4. Adjacency: Aggressor & Victim 5. Sensitivity Studies 14

15 1. Most Modules Are at Risk A company B company C company 86% (37/43) 83% (45/54) 88% (28/32) Up to errors Up to errors Up to errors 15

16 2. Errors vs. Vintage First Appearance All modules from are vulnerable 16

17 3. Error = Charge Loss Two types of errors A given cell suffers only one type Two types of cells True: Charged ( 1 ) Anti: Charged ( 0 ) Manufacturer s design choice True-cells have only 1 0 errors Anti-cells have only 0 1 errors Errors are manifestations of charge loss 17

18 Adjacent Adjacent Adjacent 4. Adjacency: Aggressor & Victim Non-Adjacent Non-Adjacent Note: For three modules with the most errors (only first bank) Most aggressors & victims are adjacent 18

19 Not Allowed 55ns 500ns 5. ❶ Access-Interval (Aggressor) Note: For three modules with the most errors (only first bank) Less frequent accesses Fewer errors 19

20 64ms 5. ❷ Refresh-Interval ~7x frequent Note: Using three modules with the most errors (only first bank) More frequent refreshes Fewer errors 20

21 5. ❸ Data-Pattern Solid RowStripe ~Solid ~RowStripe Errors affected by data stored in other cells 21

22 Outline Background - DRAM Flipping bits disturbance Demonstration (Real System) - How to Induce Errors Characterization - result Solutions - PARA 22

23 Several Potential Solutions Make better DRAM chips Cost Refresh frequently Power, Performance Sophisticated ECC Cost, Power Access counters Cost, Power, Complexity 23

24 Solution: PARA PARA: Probabilistic Adjacent Row Activation Key Idea After closing a row, we activate (i.e., refresh) one of its neighbors with a low probability: p = Reliability Guarantee When p=0.005, errors in one year: By adjusting the value of p, we can provide an arbitrarily strong protection against errors 24

25 Advantages of PARA PARA refreshes rows infrequently Low power Low performance-overhead Average slowdown: 0.20% (for 29 benchmarks) Maximum slowdown: 0.75% PARA is stateless Low cost Low complexity PARA is an effective and low-overhead solution to prevent disturbance errors 25

26 Flipping Bits in Memory Without Accessing Them An Experimental Study of DRAM Disturbance Errors 26